Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Grande-Risco-5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Grande-Risco-5
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5
Cloning into 'Grande-Risco-5'...
Submodule 'benchmarks/coremark' (https://github.com/eembc/coremark.git) registered for path 'benchmarks/coremark'
Cloning into '/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/benchmarks/coremark'...
Submodule path 'benchmarks/coremark': checked out 'd5fad6bd094899101a4e5fd53af7298160ced6ab'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] echo
simulation not supported for System Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
Trying to read file: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv
Cache-related signals in fifo_tb.sv
Possible cache file: i_cache_test.sv
Possible cache file: d_cache_test.sv
Cache-related signals in fifo.sv
Cache-related signals in uart.sv
Possible cache file: cache_request_multiplexer.sv
Possible cache file: d_cache.sv
Cache-related signals in d_cache.sv
Possible cache file: i_cache.sv
Results saved to /jenkins/processor_ci_utils/labels/Grande-Risco-5.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build Risco-5 #582 #582 since Apr 7, 2025, 1:11 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_arty_a7_100t]
The resource [digilent_arty_a7_100t] is locked by build Risco-5 #582 #582 since Apr 7, 2025, 1:11 AM.
[Resource: digilent_arty_a7_100t] is not free, waiting for execution ...
[Required resources: [digilent_arty_a7_100t]] added into queue at position 1
Lock acquired on [Resource: digilent_arty_a7_100t]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b digilent_arty_a7_100t
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv:8:28: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

2. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:49:59: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

3. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:50:74: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

4. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:81:40: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

5. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:25:22: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

6. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:74:63: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

7. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:77:11: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

8. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

9. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:6:72: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

10. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

11. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:46:95: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

12. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:130:63: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

13. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

14. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:3:77: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

15. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

16. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:7:60: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

17. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220:77: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

18. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

19. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

20. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:7:60: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

21. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 0

22. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:224:8: Non ASCII character detected, replaced by space.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 1

23. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/Grande-Risco-5.v
Parsing Verilog input from `/eda/processor_ci/rtl/Grande-Risco-5.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

24. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0301] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv:3:1: Compile package "opcodes_pkg".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1:1: Compile module "work@ALU_Control".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1:1: Compile module "work@Alu".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1:1: Compile module "work@Branch_Prediction".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1:1: Compile module "work@CSR_Unit".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1:1: Compile module "work@Cache_request_Multiplexer".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3:1: Compile module "work@Core".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1:1: Compile module "work@DCache".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3:1: Compile module "work@EXMEM".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1:1: Compile module "work@Forwarding_Unit".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1:1: Compile module "work@Grande_Risco5".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1:1: Compile module "work@ICache".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3:1: Compile module "work@IDEX".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3:1: Compile module "work@IFID".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3:1: Compile module "work@IR_Decompression".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1:1: Compile module "work@Immediate_Generator".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1:1: Compile module "work@Invalid_IR_Check".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4:1: Compile module "work@MDU".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3:1: Compile module "work@MEMWB".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1:1: Compile module "work@MUX".
[INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1:1: Compile module "work@Registers".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1:1: Top level module "work@Grande_Risco5".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 4.
[NTE:EL0510] Nb instances: 21.
[NTE:EL0511] Nb leaf instances: 0.
[INF:UH0706] Creating UHDM Model...
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 5
Generating RTLIL representation for module `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000'.
Generating RTLIL representation for module `\CSR_Unit'.
Generating RTLIL representation for module `\Registers'.
Generating RTLIL representation for module `\EXMEM'.
Generating RTLIL representation for module `\MDU'.
Generating RTLIL representation for module `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core'.
Generating RTLIL representation for module `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000'.
Generating RTLIL representation for module `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID'.
Generating RTLIL representation for module `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000'.
Generating RTLIL representation for module `\IDEX'.
Generating RTLIL representation for module `\IR_Decompression'.
Generating RTLIL representation for module `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer'.
Generating RTLIL representation for module `\Invalid_IR_Check'.
Generating RTLIL representation for module `\ALU_Control'.
Generating RTLIL representation for module `\MEMWB'.
Generating RTLIL representation for module `\Alu'.
Generating RTLIL representation for module `\Grande_Risco5'.
Generating RTLIL representation for module `\Immediate_Generator'.
Generating RTLIL representation for module `\Forwarding_Unit'.
Generating RTLIL representation for module `\MUX'.

25. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

26. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

27. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

28. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

29. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

30. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

31. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

32. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

33. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

34. Executing SYNTH_ECP5 pass.

34.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

34.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

34.3. Executing HIERARCHY pass (managing design hierarchy).

34.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \Grande_Risco5
Used module:         $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer
Used module:         $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core
Used module:             \CSR_Unit
Used module:             \Registers
Used module:             \MEMWB
Used module:             \EXMEM
Used module:             \IDEX
Used module:                 \MDU
Used module:                 \MUX
Used module:                 \Forwarding_Unit
Used module:                 \Immediate_Generator
Used module:                 \Alu
Used module:                 \ALU_Control
Used module:             $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID
Used module:                 \Invalid_IR_Check
Used module:                 $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000
Used module:                 \IR_Decompression
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

34.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

34.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

34.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

34.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

34.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

34.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

34.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

34.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

34.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

34.3.11. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \Grande_Risco5
Used module:         $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer
Used module:         $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core
Used module:             \CSR_Unit
Used module:             \Registers
Used module:             \MEMWB
Used module:             \EXMEM
Used module:             \IDEX
Used module:                 \MDU
Used module:                 \MUX
Used module:                 \Forwarding_Unit
Used module:                 \Immediate_Generator
Used module:                 \Alu
Used module:                 \ALU_Control
Used module:             $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID
Used module:                 \Invalid_IR_Check
Used module:                 $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000
Used module:                 \IR_Decompression
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

34.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

34.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

34.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

34.3.15. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \Grande_Risco5
Used module:         $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer
Used module:         $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core
Used module:             \CSR_Unit
Used module:             \Registers
Used module:             \MEMWB
Used module:             \EXMEM
Used module:             \IDEX
Used module:                 \MDU
Used module:                 \MUX
Used module:                 \Forwarding_Unit
Used module:                 \Immediate_Generator
Used module:                 \Alu
Used module:                 \ALU_Control
Used module:             $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID
Used module:                 \Invalid_IR_Check
Used module:                 $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000
Used module:                 \IR_Decompression
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

34.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

34.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

34.3.18. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \Grande_Risco5
Used module:         $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer
Used module:         $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core
Used module:             \CSR_Unit
Used module:             \Registers
Used module:             \MEMWB
Used module:             \EXMEM
Used module:             \IDEX
Used module:                 \MDU
Used module:                 \MUX
Used module:                 \Forwarding_Unit
Used module:                 \Immediate_Generator
Used module:                 \Alu
Used module:                 \ALU_Control
Used module:             $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID
Used module:                 \Invalid_IR_Check
Used module:                 $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000
Used module:                 \IR_Decompression
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

34.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \Grande_Risco5
Used module:         $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer
Used module:         $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000
Used module:         $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core
Used module:             \CSR_Unit
Used module:             \Registers
Used module:             \MEMWB
Used module:             \EXMEM
Used module:             \IDEX
Used module:                 \MDU
Used module:                 \MUX
Used module:                 \Forwarding_Unit
Used module:                 \Immediate_Generator
Used module:                 \Alu
Used module:                 \ALU_Control
Used module:             $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID
Used module:                 \Invalid_IR_Check
Used module:                 $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000
Used module:                 \IR_Decompression
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removed 14 unused modules.

34.4. Executing PROC pass (convert processes to netlists).

34.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1042'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1224'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1224'.
Cleaned up 2 empty switches.

34.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1149 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1404 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1396 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1595 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1587 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1584 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1578 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1568 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1559 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1546 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1544 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1536 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1522 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1511 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1498 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1453 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1445 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1445 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1440 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1435 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1430 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$1213 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$1202 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$1152 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644 in module MUX.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644 in module MUX.
Marked 6 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631 in module Forwarding_Unit.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$630 in module Immediate_Generator.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624 in module Grande_Risco5.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$585 in module Alu.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556 in module MEMWB.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73$552 in module MEMWB.
Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547 in module ALU_Control.
Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547 in module ALU_Control.
Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$544 in module Invalid_IR_Check.
Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535 in module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.
Removed 6 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522 in module IR_Decompression.
Marked 17 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522 in module IR_Decompression.
Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490 in module IDEX.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480 in module IDEX.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479 in module IDEX.
Marked 9 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351 in module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.
Marked 11 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301 in module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$294 in module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.
Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226 in module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.
Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196 in module MDU.
Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160 in module MDU.
Removed 2 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105 in module EXMEM.
Marked 16 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105 in module EXMEM.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91 in module Registers.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17 in module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.
Removed a total of 11 dead cases.

34.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 9 redundant assignments.
Promoted 159 assignments to connections.

34.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1150'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1429'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1599'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1552'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1504'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1482'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1452'.
  Set init value: \read_response = 1'0
  Set init value: \read_data = 0
  Set init value: \write_response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1159'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

34.4.5. Executing PROC_ARST pass (detect async resets in processes).

34.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~235 debug messages>

34.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1150'.
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1149'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101'.
     1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_EN[3:0]$1107
     2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_DATA[3:0]$1106
     3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_ADDR[3:0]$1105
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_EN[3:0]$1049
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_DATA[3:0]$1048
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_ADDR[3:0]$1047
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1042'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1429'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1416
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_DATA[7:0]$1415
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1414
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1410
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_DATA[7:0]$1409
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1408
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1396'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1599'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1595'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1587'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1584'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1578'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1568'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1559'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1552'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1546'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1544'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1536'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1522'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1511'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1504'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1498'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1482'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\address[31:0]
    27/28: $0\counter[7:0]
    28/28: $0\write_data[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1452'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1440'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1223'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1222
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_DATA[31:0]$1221
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_ADDR[31:0]$1220
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1202'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1159'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644'.
     1/1: $1\S_o[31:0]
Creating decoders for process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631'.
     1/6: $3\fwd_rs2_o[1:0]
     2/6: $2\fwd_rs2_o[1:0]
     3/6: $1\fwd_rs2_o[1:0]
     4/6: $3\fwd_rs1_o[1:0]
     5/6: $2\fwd_rs1_o[1:0]
     6/6: $1\fwd_rs1_o[1:0]
Creating decoders for process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$630'.
     1/2: $2\imm_o[31:0]
     2/2: $1\imm_o[31:0]
Creating decoders for process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624'.
     1/2: $0\peripheral_wr_through[0:0]
     2/2: $0\peripheral_access_lock[0:0]
Creating decoders for process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$585'.
     1/1: $1\ALU_RD_o[31:0]
Creating decoders for process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
     1/7: $0\MEMWB_IR[31:0]
     2/7: $0\instruction_finished_o[0:0]
     3/7: $0\mem_to_reg[0:0]
     4/7: $0\reg_wr_en_o[0:0]
     5/7: $0\MEMWBALUOut[31:0]
     6/7: $0\MEMWB_mem_read_data[31:0]
     7/7: $0\MEMWB_PC_o[31:0]
Creating decoders for process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73$552'.
     1/1: $1\read_data_normalized[31:0]
Creating decoders for process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547'.
     1/3: $3\ALU_OP_o[3:0]
     2/3: $2\ALU_OP_o[3:0]
     3/3: $1\ALU_OP_o[3:0]
Creating decoders for process `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$544'.
     1/5: $5\invalid_instruction_o[0:0]
     2/5: $4\invalid_instruction_o[0:0]
     3/5: $3\invalid_instruction_o[0:0]
     4/5: $2\invalid_instruction_o[0:0]
     5/5: $1\invalid_instruction_o[0:0]
Creating decoders for process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
     1/10: $0\d_cache_response[0:0]
     2/10: $0\i_cache_response[0:0]
     3/10: $0\d_cache_read_data[31:0]
     4/10: $0\i_cache_read_data[31:0]
     5/10: $0\access_pedding[0:0]
     6/10: $0\response_out[0:0]
     7/10: $0\requested_memory_addr[31:0]
     8/10: $0\write_request[0:0]
     9/10: $0\write_data[31:0]
    10/10: $0\read_request[0:0]
Creating decoders for process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522'.
     1/25: $11\instr_d_o[31:0]
     2/25: $10\instr_d_o[31:0]
     3/25: $14\instr_illegal_o[0:0]
     4/25: $9\instr_d_o[31:0]
     5/25: $13\instr_illegal_o[0:0]
     6/25: $12\instr_illegal_o[0:0]
     7/25: $8\instr_d_o[31:0]
     8/25: $11\instr_illegal_o[0:0]
     9/25: $10\instr_illegal_o[0:0]
    10/25: $9\instr_illegal_o[0:0]
    11/25: $7\instr_d_o[31:0]
    12/25: $6\instr_d_o[31:0]
    13/25: $8\instr_illegal_o[0:0]
    14/25: $7\instr_illegal_o[0:0]
    15/25: $6\instr_illegal_o[0:0]
    16/25: $5\instr_d_o[31:0]
    17/25: $5\instr_illegal_o[0:0]
    18/25: $4\instr_d_o[31:0]
    19/25: $3\instr_d_o[31:0]
    20/25: $4\instr_illegal_o[0:0]
    21/25: $3\instr_illegal_o[0:0]
    22/25: $2\instr_illegal_o[0:0]
    23/25: $2\instr_d_o[31:0]
    24/25: $1\instr_illegal_o[0:0]
    25/25: $1\instr_d_o[31:0]
Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
     1/8: $0\previous_instruction_is_lw[0:0]
     2/8: $0\mdu_start[0:0]
     3/8: $0\IDEXB[31:0]
     4/8: $0\IDEXA[31:0]
     5/8: $0\alu_op_o[3:0]
     6/8: $0\mdu_operation_o[0:0]
     7/8: $0\IDEXPC_o[31:0]
     8/8: $0\IDEXIR_o[31:0]
Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480'.
     1/2: $1\alu_input_b[31:0]
     2/2: $1\alu_input_a[31:0]
Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479'.
     1/2: $1\is_immediate_o[0:0]
     2/2: $1\aluop[1:0]
Creating decoders for process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
     1/56: $9$lookahead\prediction$350[1023:0]$467
     2/56: $5$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341[31:0]$466
     3/56: $8$lookahead\prediction$350[1023:0]$462
     4/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341[31:0]$458
     5/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$461
     6/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_DATA[31:0]$460
     7/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_ADDR[8:0]$459
     8/56: $7$lookahead\prediction$350[1023:0]$446
     9/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$340[31:0]$445
    10/56: $6$lookahead\prediction$350[1023:0]$441
    11/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$340[31:0]$433
    12/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$437
    13/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_DATA[31:0]$436
    14/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_ADDR[8:0]$435
    15/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$440
    16/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_DATA[31:0]$439
    17/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_ADDR[8:0]$438
    18/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341[31:0]$434
    19/56: $5$lookahead\prediction$350[1023:0]$421
    20/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$339[31:0]$420
    21/56: $4$lookahead\prediction$350[1023:0]$405
    22/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$338[31:0]$404
    23/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$399
    24/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_DATA[31:0]$398
    25/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_ADDR[8:0]$397
    26/56: $3$lookahead\prediction$350[1023:0]$400
    27/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$338[31:0]$395
    28/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$339[31:0]$396
    29/56: $2$lookahead\prediction$350[1023:0]$394
    30/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$387
    31/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_DATA[31:0]$386
    32/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_ADDR[8:0]$385
    33/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$339[31:0]$382
    34/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$338[31:0]$381
    35/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$393
    36/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_DATA[31:0]$392
    37/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_ADDR[8:0]$391
    38/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$390
    39/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_DATA[31:0]$389
    40/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_ADDR[8:0]$388
    41/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341[31:0]$384
    42/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$340[31:0]$383
    43/56: $1$lookahead\prediction$350[1023:0]$380
    44/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$379
    45/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_DATA[31:0]$378
    46/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_ADDR[8:0]$377
    47/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$376
    48/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_DATA[31:0]$375
    49/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_ADDR[8:0]$374
    50/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$373
    51/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_DATA[31:0]$372
    52/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_ADDR[8:0]$371
    53/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341[31:0]$370
    54/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$340[31:0]$369
    55/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$339[31:0]$368
    56/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$338[31:0]$367
Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
     1/11: $0\IFID_is_compressed_instruction_o[0:0]
     2/11: $0\jump_is_predicted[0:0]
     3/11: $0\flush_bus_o[0:0]
     4/11: $0\instruction_request_o[0:0]
     5/11: $0\temp_pc[31:0]
     6/11: $0\temp_instruction[31:0]
     7/11: $0\finish_unaligned_pc[0:0]
     8/11: $0\pc_is_unaligned[0:0]
     9/11: $0\PC[31:0]
    10/11: $0\IFID_IR_o[31:0]
    11/11: $0\IFID_PC_o[31:0]
Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$294'.
     1/1: $1\is_jump[0:0]
Creating decoders for process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
     1/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$283
     2/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_DATA[31:0]$282
     3/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_ADDR[2:0]$281
     4/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$280
     5/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_DATA[26:0]$279
     6/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_ADDR[2:0]$278
     7/33: $3$lookahead\cache_valid$225[7:0]$284
     8/33: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$211[31:0]$277
     9/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$267
    10/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_DATA[31:0]$266
    11/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_ADDR[2:0]$265
    12/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$264
    13/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_DATA[26:0]$263
    14/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_ADDR[2:0]$262
    15/33: $2$lookahead\cache_valid$225[7:0]$268
    16/33: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$210[31:0]$261
    17/33: $1$lookahead\cache_valid$225[7:0]$257
    18/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$256
    19/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_DATA[31:0]$255
    20/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_ADDR[2:0]$254
    21/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$253
    22/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_DATA[26:0]$252
    23/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_ADDR[2:0]$251
    24/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$250
    25/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_DATA[31:0]$249
    26/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_ADDR[2:0]$248
    27/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$247
    28/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_DATA[26:0]$246
    29/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_ADDR[2:0]$245
    30/33: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$211[31:0]$244
    31/33: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$210[31:0]$243
    32/33: $0\miss_finished[0:0]
    33/33: $0\write_through[0:0]
Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:291$205'.
Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
     1/6: $0\state_mul[1:0]
     2/6: $0\mul_ready_o[0:0]
     3/6: $0\acumulador[63:0]
     4/6: $0\Data_Y[31:0]
     5/6: $0\Data_X[31:0]
     6/6: $0\MUL_RD[31:0]
Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
     1/8: $0\state_div[1:0]
     2/8: $0\div_ready_o[0:0]
     3/8: $0\divisor[62:0]
     4/8: $0\DIV_RD[31:0]
     5/8: $0\quociente_msk[31:0]
     6/8: $0\quociente[31:0]
     7/8: $0\dividendo[31:0]
     8/8: $0\negativo[0:0]
Creating decoders for process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
     1/17: $0\unaligned_access_o[0:0]
     2/17: $0\memory_read[0:0]
     3/17: $0\memory_write[0:0]
     4/17: $0\memory_operation_o[0:0]
     5/17: $0\Merged_Word_o[31:0]
     6/17: $0\IMMEDIATE_REG_o[31:0]
     7/17: $0\EXMEMPC_o[31:0]
     8/17: $0\EXMEMIR_o[31:0]
     9/17: $0\EXMEMALUOut_o[31:0]
    10/17: $0\Data_Address[31:0]
    11/17: $0\Second_Word[31:0]
    12/17: $0\First_Word[31:0]
    13/17: $0\unaligned_access_state[3:0]
    14/17: $0\subword[0:0]
    15/17: $0\unaligned_access_in_progress[0:0]
    16/17: $0\EXMEM_mem_data_value[31:0]
    17/17: $0\subword_store[0:0]
Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
     1/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$98
     2/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_DATA[31:0]$97
     3/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_ADDR[4:0]$96
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
     1/8: $0\MSCRATCH_reg[31:0]
     2/8: $0\MTVEC_reg[31:0]
     3/8: $0\MIE_reg[31:0]
     4/8: $0\MIP_reg[31:0]
     5/8: $0\MTVAL_reg[31:0]
     6/8: $0\MCAUSE_reg[31:0]
     7/8: $0\MSTATUS_reg[31:0]
     8/8: $0\MEPC_reg[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'.
     1/2: $0\MCYCLE_reg[63:0]
     2/2: $0\MINSTRET_reg[63:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'.
     1/1: $1\csr_read_data[31:0]
Creating decoders for process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
     1/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$54
     2/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA[31:0]$53
     3/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR[2:0]$52
     4/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$51
     5/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA[26:0]$50
     6/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR[2:0]$49
     7/19: $2$lookahead\cache_valid$16[7:0]$55
     8/19: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5[31:0]$48
     9/19: $1$lookahead\cache_valid$16[7:0]$34
    10/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$33
    11/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA[31:0]$32
    12/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR[2:0]$31
    13/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$30
    14/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA[26:0]$29
    15/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR[2:0]$28
    16/19: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5[31:0]$27
    17/19: $0\miss_finished[0:0]
    18/19: $0\clear_response[0:0]
    19/19: $0\request_to_memory[0:0]

34.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1568'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1511'.
No latch inferred for signal `\MUX.\S_o' from process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644'.
No latch inferred for signal `\Forwarding_Unit.\fwd_rs1_o' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631'.
No latch inferred for signal `\Forwarding_Unit.\fwd_rs2_o' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631'.
No latch inferred for signal `\Immediate_Generator.\imm_o' from process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$630'.
No latch inferred for signal `\Alu.\ALU_RD_o' from process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$585'.
No latch inferred for signal `\MEMWB.\read_data_normalized' from process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73$552'.
No latch inferred for signal `\ALU_Control.\ALU_OP_o' from process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547'.
No latch inferred for signal `\Invalid_IR_Check.\invalid_instruction_o' from process `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$544'.
No latch inferred for signal `\IR_Decompression.\instr_d_o' from process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522'.
No latch inferred for signal `\IR_Decompression.\instr_illegal_o' from process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522'.
No latch inferred for signal `\IDEX.\alu_input_a' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480'.
No latch inferred for signal `\IDEX.\alu_input_b' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480'.
No latch inferred for signal `\IDEX.\is_immediate_o' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479'.
No latch inferred for signal `\IDEX.\aluop' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479'.
No latch inferred for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_jump' from process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$294'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'.
No latch inferred for signal `\CSR_Unit.\csr_read_data' from process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'.

34.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1149'.
  created $dff cell `$procdff$5223' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1085_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1086_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1087_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1088_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1089_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1090_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1091_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1092_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1093_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1094_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1095_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1096_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1097_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1098_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1099_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101'.
  created $dff cell `$procdff$5224' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101'.
  created $dff cell `$procdff$5225' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1100_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101'.
  created $dff cell `$procdff$5226' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1025_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1026_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1027_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1028_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1029_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1030_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1031_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1032_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1033_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1034_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1035_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1036_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1037_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1038_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1039_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1040_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043'.
  created $dff cell `$procdff$5227' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043'.
  created $dff cell `$procdff$5228' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1041_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043'.
  created $dff cell `$procdff$5229' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
  created $dff cell `$procdff$5230' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
  created $dff cell `$procdff$5231' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
  created $dff cell `$procdff$5232' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
  created $dff cell `$procdff$5233' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1396'.
  created $dff cell `$procdff$5234' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1396'.
  created $dff cell `$procdff$5235' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597'.
  created $dff cell `$procdff$5236' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597'.
  created $dff cell `$procdff$5237' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1595'.
  created $dff cell `$procdff$5238' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1587'.
  created $dff cell `$procdff$5239' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1584'.
  created $dff cell `$procdff$5240' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1578'.
  created $dff cell `$procdff$5241' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573'.
  created $dff cell `$procdff$5242' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573'.
  created $dff cell `$procdff$5243' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1559'.
  created $dff cell `$procdff$5244' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1546'.
  created $dff cell `$procdff$5245' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1544'.
  created $dff cell `$procdff$5246' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1536'.
  created $dff cell `$procdff$5247' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1522'.
  created $dff cell `$procdff$5248' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516'.
  created $dff cell `$procdff$5249' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516'.
  created $dff cell `$procdff$5250' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1498'.
  created $dff cell `$procdff$5251' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489'.
  created $dff cell `$procdff$5252' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489'.
  created $dff cell `$procdff$5253' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5254' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5255' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5256' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5257' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5258' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5259' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5260' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5261' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5262' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5263' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5264' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5265' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5266' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5267' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5268' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5269' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5270' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5271' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5272' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5273' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5274' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5275' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5276' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5277' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5278' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5279' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5280' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
  created $dff cell `$procdff$5281' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
  created $dff cell `$procdff$5282' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
  created $dff cell `$procdff$5283' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
  created $dff cell `$procdff$5284' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
  created $dff cell `$procdff$5285' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1440'.
  created $dff cell `$procdff$5286' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1440'.
  created $dff cell `$procdff$5287' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5288' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5289' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5290' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5291' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5292' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
  created $dff cell `$procdff$5293' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
  created $dff cell `$procdff$5294' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
  created $dff cell `$procdff$5295' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
  created $dff cell `$procdff$5296' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
  created $dff cell `$procdff$5297' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
  created $dff cell `$procdff$5298' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1223'.
  created $dff cell `$procdff$5299' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1223'.
  created $dff cell `$procdff$5300' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
  created $dff cell `$procdff$5301' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
  created $dff cell `$procdff$5302' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
  created $dff cell `$procdff$5303' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
  created $dff cell `$procdff$5304' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1202'.
  created $dff cell `$procdff$5305' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
  created $dff cell `$procdff$5306' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
  created $dff cell `$procdff$5307' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
  created $dff cell `$procdff$5308' with positive edge clock.
Creating register for signal `\Grande_Risco5.\peripheral_access_lock' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624'.
  created $dff cell `$procdff$5309' with positive edge clock.
Creating register for signal `\Grande_Risco5.\peripheral_wr_through' using process `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624'.
  created $dff cell `$procdff$5310' with positive edge clock.
Creating register for signal `\MEMWB.\instruction_finished_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5311' with positive edge clock.
Creating register for signal `\MEMWB.\reg_wr_en_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5312' with positive edge clock.
Creating register for signal `\MEMWB.\MEMWB_PC_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5313' with positive edge clock.
Creating register for signal `\MEMWB.\mem_to_reg' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5314' with positive edge clock.
Creating register for signal `\MEMWB.\MEMWB_mem_read_data' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5315' with positive edge clock.
Creating register for signal `\MEMWB.\MEMWBALUOut' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5316' with positive edge clock.
Creating register for signal `\MEMWB.\MEMWB_IR' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
  created $dff cell `$procdff$5317' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\read_request' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5318' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\write_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5319' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\write_request' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5320' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\requested_memory_addr' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5321' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\response_out' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5322' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\access_pedding' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5323' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\i_cache_read_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5324' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\d_cache_read_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5325' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\i_cache_response' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5326' with positive edge clock.
Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\d_cache_response' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
  created $dff cell `$procdff$5327' with positive edge clock.
Creating register for signal `\IDEX.\take_jalr_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5328' with positive edge clock.
Creating register for signal `\IDEX.\is_branch_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5329' with positive edge clock.
Creating register for signal `\IDEX.\is_jalr_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5330' with positive edge clock.
Creating register for signal `\IDEX.\IDEX_is_compressed_instruction_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5331' with positive edge clock.
Creating register for signal `\IDEX.\BRANCH_ADDRESS_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5332' with positive edge clock.
Creating register for signal `\IDEX.\NON_BRANCH_ADDRESS_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5333' with positive edge clock.
Creating register for signal `\IDEX.\IDEXIR_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5334' with positive edge clock.
Creating register for signal `\IDEX.\IDEXPC_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5335' with positive edge clock.
Creating register for signal `\IDEX.\mdu_operation_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5336' with positive edge clock.
Creating register for signal `\IDEX.\mdu_start' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5337' with positive edge clock.
Creating register for signal `\IDEX.\is_immediate_reg_not' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5338' with positive edge clock.
Creating register for signal `\IDEX.\alu_op_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5339' with positive edge clock.
Creating register for signal `\IDEX.\previous_instruction_is_lw' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5340' with positive edge clock.
Creating register for signal `\IDEX.\IDEXA' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5341' with positive edge clock.
Creating register for signal `\IDEX.\IDEXB' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
  created $dff cell `$procdff$5342' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.\prediction' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5343' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$338' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5344' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$339' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5345' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$340' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5346' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$341' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5347' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5348' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5349' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5350' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5351' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5352' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5353' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5354' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5355' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5356' with positive edge clock.
Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$lookahead\prediction$350' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
  created $dff cell `$procdff$5357' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\take_jal_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5358' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_jal_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5359' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_is_compressed_instruction_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5360' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_PC_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5361' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_IR_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5362' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\flush_bus_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5363' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\instruction_request_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5364' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5365' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\jump_is_predicted' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5366' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_different_branch_address' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5367' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\pc_is_unaligned' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5368' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\finish_unaligned_pc' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5369' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_different_no_branch_address' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5370' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\temp_instruction' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5371' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\temp_pc' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5372' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\JAL_PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5373' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\JALR_PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
  created $dff cell `$procdff$5374' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\miss_finished' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5375' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\cache_valid' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5376' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\write_through' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5377' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$210' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5378' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$211' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5379' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5380' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5381' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5382' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5383' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5384' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5385' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5386' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5387' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5388' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5389' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5390' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5391' with positive edge clock.
Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$lookahead\cache_valid$225' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
  created $dff cell `$procdff$5392' with positive edge clock.
Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.\software_interruption' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:291$205'.
  created $dff cell `$procdff$5393' with positive edge clock.
Creating register for signal `\MDU.\mul_ready_o' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5394' with positive edge clock.
Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5395' with positive edge clock.
Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5396' with positive edge clock.
Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5397' with positive edge clock.
Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5398' with positive edge clock.
Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
  created $dff cell `$procdff$5399' with positive edge clock.
Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5400' with positive edge clock.
Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5401' with positive edge clock.
Creating register for signal `\MDU.\div_ready_o' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5402' with positive edge clock.
Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5403' with positive edge clock.
Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5404' with positive edge clock.
Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5405' with positive edge clock.
Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5406' with positive edge clock.
Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
  created $dff cell `$procdff$5407' with positive edge clock.
Creating register for signal `\EXMEM.\subword_store' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5408' with positive edge clock.
Creating register for signal `\EXMEM.\memory_read' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5409' with positive edge clock.
Creating register for signal `\EXMEM.\memory_write' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5410' with positive edge clock.
Creating register for signal `\EXMEM.\EXMEM_mem_data_value' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5411' with positive edge clock.
Creating register for signal `\EXMEM.\unaligned_access_in_progress' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5412' with positive edge clock.
Creating register for signal `\EXMEM.\subword' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5413' with positive edge clock.
Creating register for signal `\EXMEM.\unaligned_access_state' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5414' with positive edge clock.
Creating register for signal `\EXMEM.\First_Word' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5415' with positive edge clock.
Creating register for signal `\EXMEM.\Second_Word' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5416' with positive edge clock.
Creating register for signal `\EXMEM.\Data_Address' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5417' with positive edge clock.
Creating register for signal `\EXMEM.\EXMEMALUOut_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5418' with positive edge clock.
Creating register for signal `\EXMEM.\EXMEMIR_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5419' with positive edge clock.
Creating register for signal `\EXMEM.\EXMEMPC_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5420' with positive edge clock.
Creating register for signal `\EXMEM.\IMMEDIATE_REG_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5421' with positive edge clock.
Creating register for signal `\EXMEM.\Merged_Word_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5422' with positive edge clock.
Creating register for signal `\EXMEM.\memory_operation_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5423' with positive edge clock.
Creating register for signal `\EXMEM.\unaligned_access_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
  created $dff cell `$procdff$5424' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_ADDR' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
  created $dff cell `$procdff$5425' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_DATA' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
  created $dff cell `$procdff$5426' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
  created $dff cell `$procdff$5427' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:28$78_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
  created $dff cell `$procdff$5428' with positive edge clock.
Creating register for signal `\CSR_Unit.\MEPC_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5429' with positive edge clock.
Creating register for signal `\CSR_Unit.\MSTATUS_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5430' with positive edge clock.
Creating register for signal `\CSR_Unit.\MCAUSE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5431' with positive edge clock.
Creating register for signal `\CSR_Unit.\MTVAL_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5432' with positive edge clock.
Creating register for signal `\CSR_Unit.\MIP_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5433' with positive edge clock.
Creating register for signal `\CSR_Unit.\MIE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5434' with positive edge clock.
Creating register for signal `\CSR_Unit.\MTVEC_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5435' with positive edge clock.
Creating register for signal `\CSR_Unit.\MSCRATCH_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
  created $dff cell `$procdff$5436' with positive edge clock.
Creating register for signal `\CSR_Unit.\MCYCLE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'.
  created $dff cell `$procdff$5437' with positive edge clock.
Creating register for signal `\CSR_Unit.\MINSTRET_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'.
  created $dff cell `$procdff$5438' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\request_to_memory' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5439' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\clear_response' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5440' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\miss_finished' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5441' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\cache_valid' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5442' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5443' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5444' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5445' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5446' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5447' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5448' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5449' with positive edge clock.
Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$lookahead\cache_valid$16' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
  created $dff cell `$procdff$5450' with positive edge clock.

34.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

34.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1150'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1149'.
Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1149'.
Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1124'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1101'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1067'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1043'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1042'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1429'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1404'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1396'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1396'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1599'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1597'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1595'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1595'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1587'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1587'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1584'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1584'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1578'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1578'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1573'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1568'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1568'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1559'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1559'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1552'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1546'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1546'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1544'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1544'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1536'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1536'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1522'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1522'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1516'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1511'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1511'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1504'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1498'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1498'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1489'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1482'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1453'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1452'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1445'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1440'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1440'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1435'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1430'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1223'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1213'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1202'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1202'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1159'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1152'.
Found and cleaned up 1 empty switch in `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644'.
Removing empty process `MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$644'.
Found and cleaned up 6 empty switches in `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631'.
Removing empty process `Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$631'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$630'.
Removing empty process `Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$630'.
Found and cleaned up 3 empty switches in `\Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624'.
Removing empty process `Grande_Risco5.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:156$624'.
Found and cleaned up 1 empty switch in `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$585'.
Removing empty process `Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$585'.
Found and cleaned up 3 empty switches in `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
Removing empty process `MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:37$556'.
Found and cleaned up 1 empty switch in `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73$552'.
Removing empty process `MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73$552'.
Found and cleaned up 3 empty switches in `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547'.
Removing empty process `ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$547'.
Found and cleaned up 5 empty switches in `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$544'.
Removing empty process `Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$544'.
Found and cleaned up 6 empty switches in `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
Removing empty process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$535'.
Found and cleaned up 17 empty switches in `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522'.
Removing empty process `IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$522'.
Found and cleaned up 3 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$490'.
Found and cleaned up 2 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480'.
Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$480'.
Found and cleaned up 2 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479'.
Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$479'.
Found and cleaned up 9 empty switches in `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
Removing empty process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$351'.
Found and cleaned up 18 empty switches in `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$301'.
Found and cleaned up 1 empty switch in `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$294'.
Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$294'.
Found and cleaned up 4 empty switches in `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
Removing empty process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$226'.
Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:291$205'.
Found and cleaned up 4 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$196'.
Found and cleaned up 6 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$160'.
Found and cleaned up 32 empty switches in `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
Removing empty process `EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:86$105'.
Found and cleaned up 1 empty switch in `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'.
Found and cleaned up 2 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'.
Found and cleaned up 5 empty switches in `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
Removing empty process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'.
Cleaned up 235 empty switches.

34.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Forwarding_Unit.
Optimizing module Immediate_Generator.
Optimizing module Grande_Risco5.
<suppressed ~4 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module MEMWB.
<suppressed ~2 debug messages>
Optimizing module ALU_Control.
<suppressed ~1 debug messages>
Optimizing module Invalid_IR_Check.
<suppressed ~5 debug messages>
Optimizing module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.
<suppressed ~16 debug messages>
Optimizing module IR_Decompression.
<suppressed ~35 debug messages>
Optimizing module IDEX.
Optimizing module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.
<suppressed ~57 debug messages>
Optimizing module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.
<suppressed ~15 debug messages>
Optimizing module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.
<suppressed ~33 debug messages>
Optimizing module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.
Optimizing module MDU.
<suppressed ~29 debug messages>
Optimizing module EXMEM.
<suppressed ~17 debug messages>
Optimizing module Registers.
Optimizing module CSR_Unit.
<suppressed ~11 debug messages>
Optimizing module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.
<suppressed ~19 debug messages>
Optimizing module processorci_top.

34.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module MUX.
Deleting now unused module Forwarding_Unit.
Deleting now unused module Immediate_Generator.
Deleting now unused module Grande_Risco5.
Deleting now unused module Alu.
Deleting now unused module MEMWB.
Deleting now unused module ALU_Control.
Deleting now unused module Invalid_IR_Check.
Deleting now unused module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.
Deleting now unused module IR_Decompression.
Deleting now unused module IDEX.
Deleting now unused module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.
Deleting now unused module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.
Deleting now unused module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.
Deleting now unused module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.
Deleting now unused module MDU.
Deleting now unused module EXMEM.
Deleting now unused module Registers.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.
<suppressed ~32 debug messages>

34.6. Executing TRIBUF pass.

34.7. Executing DEMINOUT pass (demote inout ports to input or output).

34.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~266 debug messages>

34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 255 unused cells and 1753 unused wires.
<suppressed ~289 debug messages>

34.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_memory_data is used but has no driver.
Warning: Wire processorci_top.\Controller.core_read_memory_data is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [0] is used but has no driver.
Found and reported 69 problems.

34.11. Executing OPT pass (performing simple optimizations).

34.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~1329 debug messages>
Removed a total of 443 cells.

34.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $flatten\Processor.\N1.\First_Stage.$procmux$4157: \Processor.N1.First_Stage.finish_unaligned_pc -> 1'0
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1627.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1633.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1639.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1627.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1633.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1639.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4319.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4325.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4331.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4337.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4343.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4349.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4355.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4367.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4373.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4379.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4385.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4391.
    dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4397.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5132.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5138.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5144.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5150.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5156.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5162.
    dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5168.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3606.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3609.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3612.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3615.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3636.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3639.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3642.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3660.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3663.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3666.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3672.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3675.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3678.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3684.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3687.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3690.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3696.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3699.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3702.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3720.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3723.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3738.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3741.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3747.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3750.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3756.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3759.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3765.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3768.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3774.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3777.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3783.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3786.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3802.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3804.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3807.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3826.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3828.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3831.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3849.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3852.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3858.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3861.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3867.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3870.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3876.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3903.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3915.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3921.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3939.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3945.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3951.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3957.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3963.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3969.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3255.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3258.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3260.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3262.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3271.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3273.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3275.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3285.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3287.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3289.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3291.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3300.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3302.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3304.
    dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3313.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3315.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3317.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3325.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3327.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3335.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3346.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3348.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3358.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3360.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3369.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3378.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3389.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3391.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3393.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3404.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3406.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3408.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3418.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3420.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3422.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3431.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3433.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3442.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3444.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3453.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3455.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3464.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3466.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3477.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3488.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3499.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3501.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3511.
    dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3521.
    dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3063.
    dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3074.
    dead port 1/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2942.
    dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2948.
    dead port 1/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2957.
    dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2963.
    dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2977.
Removed 140 multiplexer ports.
<suppressed ~256 debug messages>

34.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4316:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4316_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4316_Y [0]
      New connections: $flatten\Processor.\DCache.$procmux$4316_Y [31:1] = { $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] $flatten\Processor.\DCache.$procmux$4316_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4334:
      Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4334_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4334_Y [0]
      New connections: $flatten\Processor.\DCache.$procmux$4334_Y [26:1] = { $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] $flatten\Processor.\DCache.$procmux$4334_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4364:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4364_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4364_Y [0]
      New connections: $flatten\Processor.\DCache.$procmux$4364_Y [31:1] = { $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] $flatten\Processor.\DCache.$procmux$4364_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4382:
      Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4382_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4382_Y [0]
      New connections: $flatten\Processor.\DCache.$procmux$4382_Y [26:1] = { $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] $flatten\Processor.\DCache.$procmux$4382_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5129:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\ICache.$procmux$5129_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\ICache.$procmux$5129_Y [0]
      New connections: $flatten\Processor.\ICache.$procmux$5129_Y [31:1] = { $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] $flatten\Processor.\ICache.$procmux$5129_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5147:
      Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\ICache.$procmux$5147_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\ICache.$procmux$5147_Y [0]
      New connections: $flatten\Processor.\ICache.$procmux$5147_Y [26:1] = { $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] $flatten\Processor.\ICache.$procmux$5147_Y [0] }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5049: $auto$opt_reduce.cc:137:opt_pmux$5497
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5110: { $auto$opt_reduce.cc:137:opt_pmux$5505 $auto$opt_reduce.cc:137:opt_pmux$5503 $auto$opt_reduce.cc:137:opt_pmux$5501 $auto$opt_reduce.cc:137:opt_pmux$5499 $flatten\Processor.\N1.\CSR.$procmux$5119_CMP $flatten\Processor.\N1.\CSR.$procmux$5085_CMP $flatten\Processor.\N1.\CSR.$procmux$5051_CMP $flatten\Processor.\N1.\CSR.$procmux$5043_CMP $flatten\Processor.\N1.\CSR.$procmux$5031_CMP $flatten\Processor.\N1.\CSR.$procmux$5095_CMP $flatten\Processor.\N1.\CSR.$procmux$5071_CMP $flatten\Processor.\N1.\CSR.$procmux$5062_CMP $flatten\Processor.\N1.\CSR.$procmux$5050_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2063: $auto$opt_reduce.cc:137:opt_pmux$5507
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2087: $auto$opt_reduce.cc:137:opt_pmux$5509
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2109: $auto$opt_reduce.cc:137:opt_pmux$5511
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2120: $auto$opt_reduce.cc:137:opt_pmux$5513
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2168: $auto$opt_reduce.cc:137:opt_pmux$5515
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2210: $auto$opt_reduce.cc:137:opt_pmux$5517
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2235: { $flatten\Controller.\Interpreter.$procmux$2003_CMP $auto$opt_reduce.cc:137:opt_pmux$5519 $flatten\Controller.\Interpreter.$procmux$1993_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2288: { $auto$opt_reduce.cc:137:opt_pmux$5523 $auto$opt_reduce.cc:137:opt_pmux$5521 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3398: { $auto$opt_reduce.cc:137:opt_pmux$5525 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3384_CTRL }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2357: $auto$opt_reduce.cc:137:opt_pmux$5527
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2382: { $flatten\Controller.\Interpreter.$procmux$2003_CMP $auto$opt_reduce.cc:137:opt_pmux$5529 $flatten\Controller.\Interpreter.$procmux$1993_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2873:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2410: { $flatten\Controller.\Interpreter.$procmux$1989_CMP $flatten\Controller.\Interpreter.$procmux$1982_CMP $flatten\Controller.\Interpreter.$procmux$1971_CMP $flatten\Controller.\Interpreter.$procmux$1965_CMP $auto$opt_reduce.cc:137:opt_pmux$5531 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3481: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364_CMP [1] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3261_CMP $auto$opt_reduce.cc:137:opt_pmux$5533 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2442: { $auto$opt_reduce.cc:137:opt_pmux$5537 $auto$opt_reduce.cc:137:opt_pmux$5535 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3506: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3359_CMP $auto$opt_reduce.cc:137:opt_pmux$5539 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3507_CTRL }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2524: { $flatten\Controller.\Interpreter.$procmux$1983_CMP $auto$opt_reduce.cc:137:opt_pmux$5541 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2535: { $flatten\Controller.\Interpreter.$procmux$2124_CMP $flatten\Controller.\Interpreter.$procmux$2023_CMP $auto$opt_reduce.cc:137:opt_pmux$5543 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2545: { $flatten\Controller.\Interpreter.$procmux$2022_CMP $auto$opt_reduce.cc:137:opt_pmux$5547 $auto$opt_reduce.cc:137:opt_pmux$5545 }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\RegisterBank.$procmux$5013:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94
      New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0]
      New connections: $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [31:1] = { $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2599: { $auto$opt_reduce.cc:137:opt_pmux$5549 $flatten\Controller.\Interpreter.$procmux$2089_CMP $flatten\Controller.\Interpreter.$procmux$2008_CMP $flatten\Controller.\Interpreter.$procmux$2003_CMP $flatten\Controller.\Interpreter.$procmux$1993_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1963: { $flatten\Controller.\Interpreter.$procmux$2057_CMP $flatten\Controller.\Interpreter.$procmux$2053_CMP $flatten\Controller.\Interpreter.$procmux$2049_CMP $flatten\Controller.\Interpreter.$procmux$2023_CMP $flatten\Controller.\Interpreter.$procmux$2022_CMP $flatten\Controller.\Interpreter.$procmux$2018_CMP $flatten\Controller.\Interpreter.$procmux$2017_CMP $flatten\Controller.\Interpreter.$procmux$2013_CMP $flatten\Controller.\Interpreter.$procmux$2003_CMP $flatten\Controller.\Interpreter.$procmux$1999_CMP $auto$opt_reduce.cc:137:opt_pmux$5557 $flatten\Controller.\Interpreter.$procmux$1994_CMP $flatten\Controller.\Interpreter.$procmux$1993_CMP $auto$opt_reduce.cc:137:opt_pmux$5555 $flatten\Controller.\Interpreter.$procmux$1988_CMP $flatten\Controller.\Interpreter.$procmux$1987_CMP $flatten\Controller.\Interpreter.$procmux$1982_CMP $flatten\Controller.\Interpreter.$procmux$1978_CMP $flatten\Controller.\Interpreter.$procmux$1977_CMP $auto$opt_reduce.cc:137:opt_pmux$5553 $flatten\Controller.\Interpreter.$procmux$1971_CMP $flatten\Controller.\Interpreter.$procmux$1970_CMP $flatten\Controller.\Interpreter.$procmux$1969_CMP $auto$opt_reduce.cc:137:opt_pmux$5551 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2653: { $auto$opt_reduce.cc:137:opt_pmux$5559 $flatten\Controller.\Interpreter.$procmux$2022_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2677: { $flatten\Controller.\Interpreter.$procmux$2090_CMP $flatten\Controller.\Interpreter.$procmux$2089_CMP $auto$opt_reduce.cc:137:opt_pmux$5561 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2980: { $flatten\Processor.\N1.\Second_Stage.$0\is_branch_o[0:0] $flatten\Processor.\N1.\First_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:89$302_Y $auto$opt_reduce.cc:137:opt_pmux$5565 $flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP [0] $auto$opt_reduce.cc:137:opt_pmux$5563 $flatten\Processor.\N1.\Second_Stage.$procmux$3600_CMP [1] $flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP [2] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2873:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_EN[31:0]$1216 [0] }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4650: { $auto$opt_reduce.cc:137:opt_pmux$5567 $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4678: $auto$opt_reduce.cc:137:opt_pmux$5569
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4850: { $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP $auto$opt_reduce.cc:137:opt_pmux$5571 }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2741: $auto$opt_reduce.cc:137:opt_pmux$5573
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4868: { $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4626_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4623_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP $auto$opt_reduce.cc:137:opt_pmux$5575 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4957: { $flatten\Processor.\N1.\Third_Stage.$procmux$4965_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4964_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4963_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4962_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4961_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4960_CMP $auto$opt_reduce.cc:137:opt_pmux$5577 }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2805: $auto$opt_reduce.cc:137:opt_pmux$5579
    New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5532: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3365_CMP $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364_CMP [3:2] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364_CMP [0] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3359_CMP $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3347_CMP }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4415:
      Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$283, B=0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240
      New ports: A=$flatten\Processor.\DCache.$procmux$4316_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0]
      New connections: $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [31:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$215_EN[31:0]$240 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4424:
      Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$280, B=27'000000000000000000000000000, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237
      New ports: A=$flatten\Processor.\DCache.$procmux$4334_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0]
      New connections: $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [26:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$214_EN[26:0]$237 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4433:
      Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$267, B=0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234
      New ports: A=$flatten\Processor.\DCache.$procmux$4364_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0]
      New connections: $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [31:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$213_EN[31:0]$234 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4442:
      Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$264, B=27'000000000000000000000000000, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231
      New ports: A=$flatten\Processor.\DCache.$procmux$4382_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0]
      New connections: $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [26:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$212_EN[26:0]$231 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5180:
      Old ports: A=$flatten\Processor.\ICache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$54, B=0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24
      New ports: A=$flatten\Processor.\ICache.$procmux$5129_Y [0], B=1'0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0]
      New connections: $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [31:1] = { $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5189:
      Old ports: A=$flatten\Processor.\ICache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$51, B=27'000000000000000000000000000, Y=$flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21
      New ports: A=$flatten\Processor.\ICache.$procmux$5147_Y [0], B=1'0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0]
      New connections: $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [26:1] = { $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1642:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1416, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1624_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$461, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1642:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1416, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1624_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_EN[7:0]$1407 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906:
      Old ports: A=0, B=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$399, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y
      New ports: A=1'0, B=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3847_Y [0], Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$437, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$440, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3762_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3996:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$390, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3954_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$343_EN[31:0]$361 [0] }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$4005:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$387, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3906_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$342_EN[31:0]$358 [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3987:
      Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$393, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364
      New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0]
      New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$344_EN[31:0]$364 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 62 changes.

34.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~126 debug messages>
Removed a total of 42 cells.

34.11.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $flatten\Processor.\N1.\First_Stage.$procdff$5364 ($dff) from module processorci_top.

34.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 620 unused wires.
<suppressed ~23 debug messages>

34.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~2 debug messages>

34.11.9. Rerunning OPT passes. (Maybe there is more to do..)

34.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~259 debug messages>

34.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2235: { $auto$opt_reduce.cc:137:opt_pmux$5519 $auto$opt_reduce.cc:137:opt_pmux$5581 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2382: { $auto$opt_reduce.cc:137:opt_pmux$5519 $auto$opt_reduce.cc:137:opt_pmux$5583 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2599: { $auto$opt_reduce.cc:137:opt_pmux$5549 $flatten\Controller.\Interpreter.$procmux$2089_CMP $flatten\Controller.\Interpreter.$procmux$2008_CMP $auto$opt_reduce.cc:137:opt_pmux$5585 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3007: { $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3021_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3020_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3019_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3018_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3017_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3016_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3015_CMP $auto$opt_reduce.cc:137:opt_pmux$5589 $auto$opt_reduce.cc:137:opt_pmux$5587 $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3010_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3009_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3008_CMP }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4622: { $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP $auto$opt_reduce.cc:137:opt_pmux$5591 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4650: { $auto$opt_reduce.cc:137:opt_pmux$5567 $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP $auto$opt_reduce.cc:137:opt_pmux$5593 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4818: $auto$opt_reduce.cc:137:opt_pmux$5595
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4838: $auto$opt_reduce.cc:137:opt_pmux$5597
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4850: { $auto$opt_reduce.cc:137:opt_pmux$5599 $auto$opt_reduce.cc:137:opt_pmux$5571 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4868: { $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP $auto$opt_reduce.cc:137:opt_pmux$5601 $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP $auto$opt_reduce.cc:137:opt_pmux$5575 }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4937: { $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP $auto$opt_reduce.cc:137:opt_pmux$5603 }
  Optimizing cells in module \processorci_top.
Performed a total of 11 changes.

34.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

34.11.13. Executing OPT_DFF pass (perform DFF optimizations).

34.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

34.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.11.16. Rerunning OPT passes. (Maybe there is more to do..)

34.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~259 debug messages>

34.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.11.20. Executing OPT_DFF pass (perform DFF optimizations).

34.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.11.23. Finished OPT passes. (There is nothing left to do.)

34.12. Executing FSM pass (extract and optimize FSM).

34.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.Processor.N1.CSR.MIP_reg as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Processor.N1.Second_Stage.Mdu.state_div.
Found FSM state register processorci_top.Processor.N1.Second_Stage.Mdu.state_mul.
Not marking processorci_top.Processor.N1.Second_Stage.alu_op_o as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Processor.N1.Third_Stage.unaligned_access_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

34.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$5238
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1563_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1576_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1589_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1575_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1589_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1580_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1576_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1575_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1563_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1563_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1575_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1576_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1580_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1589_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$5285
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2702_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2697_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2704_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2691_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1449_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2691_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2697_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2702_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2704_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1449_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2704_CMP $flatten\Controller.\Uart.$procmux$2702_CMP $flatten\Controller.\Uart.$procmux$2697_CMP $flatten\Controller.\Uart.$procmux$2691_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000
Extracting FSM `\Processor.N1.Second_Stage.Mdu.state_div' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5400
  root of input selection tree: $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4535_CMP
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4539_CMP
  found state code: 2'00
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$181_Y
  found state code: 2'01
  found state code: 2'10
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$162_Y
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4535_CMP
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4539_CMP
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4545_CMP
  ctrl inputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$181_Y $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$162_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4545_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4539_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4535_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] }
  transition:       2'00 3'-00 ->       2'00 5'01000
  transition:       2'00 3'-10 ->       2'01 5'01001
  transition:       2'00 3'--1 ->       2'00 5'01000
  transition:       2'10 3'--0 ->       2'00 5'10000
  transition:       2'10 3'--1 ->       2'00 5'10000
  transition:       2'01 3'0-0 ->       2'01 5'00101
  transition:       2'01 3'1-0 ->       2'10 5'00110
  transition:       2'01 3'--1 ->       2'00 5'00100
Extracting FSM `\Processor.N1.Second_Stage.Mdu.state_mul' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5396
  root of input selection tree: $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4475_CMP
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4479_CMP
  found state code: 2'00
  found state code: 2'10
  found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$199_Y
  found state code: 2'01
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4475_CMP
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4479_CMP
  found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4485_CMP
  ctrl inputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$199_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4485_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4479_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4475_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] }
  transition:       2'00 2'00 ->       2'00 5'01000
  transition:       2'00 2'10 ->       2'01 5'01001
  transition:       2'00 2'-1 ->       2'00 5'01000
  transition:       2'10 2'-0 ->       2'00 5'10000
  transition:       2'10 2'-1 ->       2'00 5'10000
  transition:       2'01 2'-0 ->       2'10 5'00110
  transition:       2'01 2'-1 ->       2'00 5'00100
Extracting FSM `\Processor.N1.Third_Stage.unaligned_access_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Processor.\N1.\Third_Stage.$procdff$5414
  root of input selection tree: $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0]
  found reset state: 4'0000 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:98$108_Y
  found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5575
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP
  found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5591
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP
  found state code: 4'1001
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:248$124_Y
  found state code: 4'1101
  found state code: 4'0110
  found ctrl input: \Processor.N1.Third_Stage.data_memory_response
  found state code: 4'0000
  found state code: 4'1100
  found ctrl input: \Processor.N1.Third_Stage.subword
  found state code: 4'1000
  found state code: 4'1111
  found state code: 4'0111
  found state code: 4'0101
  found state code: 4'1110
  found state code: 4'1010
  found state code: 4'0011
  found state code: 4'0010
  found ctrl input: \Processor.N1.Third_Stage.subword_store
  found ctrl input: $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:59$572_Y
  found ctrl input: $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:106$110_Y
  found state code: 4'0100
  found state code: 4'0001
  found state code: 4'1011
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4684_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4679_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4626_CMP
  found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4623_CMP
  ctrl inputs: { $auto$opt_reduce.cc:137:opt_pmux$5575 $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:59$572_Y \Processor.N1.Third_Stage.subword_store \Processor.N1.Third_Stage.subword \Processor.N1.Third_Stage.data_memory_response $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:98$108_Y $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:106$110_Y $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:248$124_Y $auto$opt_reduce.cc:137:opt_pmux$5591 \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] $flatten\Processor.\N1.\Third_Stage.$procmux$4623_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4626_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4679_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4684_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP }
  transition:     4'0000 10'-----0---0 ->     4'0000 20'00000000000001000000
  transition:     4'0000 10'-00--10--0 ->     4'0000 20'00000000000001000000
  transition:     4'0000 10'-00--11--0 ->     4'0100 20'01000000000001000000
  transition:     4'0000 10'-10--1---0 ->     4'0001 20'00010000000001000000
  transition:     4'0000 10'--1--1---0 ->     4'1011 20'10110000000001000000
  transition:     4'0000 10'---------1 ->     4'0000 20'00000000000001000000
  transition:     4'1000 10'-----0---0 ->     4'1000 20'10000000000000000100
  transition:     4'1000 10'-----1--00 ->     4'1001 20'10010000000000000100
  transition:     4'1000 10'---------1 ->     4'0000 20'00000000000000000100
  transition:     4'0100 10'-----0---0 ->     4'0100 20'01000000001000000000
  transition:     4'0100 10'----01---0 ->     4'0100 20'01000000001000000000
  transition:     4'0100 10'---011---0 ->     4'0101 20'01010000001000000000
  transition:     4'0100 10'---111---0 ->     4'1110 20'11100000001000000000
  transition:     4'0100 10'---------1 ->     4'0000 20'00000000001000000000
  transition:     4'1100 10'-----0---0 ->     4'1100 20'11000000000000001000
  transition:     4'1100 10'-----1---0 ->     4'1101 20'11010000000000001000
  transition:     4'1100 10'---------1 ->     4'0000 20'00000000000000001000
  transition:     4'0010 10'-----0---0 ->     4'0010 20'00100000000100000000
  transition:     4'0010 10'----01---0 ->     4'0010 20'00100000000100000000
  transition:     4'0010 10'----11---0 ->     4'0011 20'00110000000100000000
  transition:     4'0010 10'---------1 ->     4'0000 20'00000000000100000000
  transition:     4'1010 10'-----0---0 ->     4'1010 20'10100010000000000000
  transition:     4'1010 10'-----1---0 ->     4'0000 20'00000010000000000000
  transition:     4'1010 10'---------1 ->     4'0000 20'00000010000000000000
  transition:     4'0110 10'-----0---0 ->     4'0110 20'01100000010000000000
  transition:     4'0110 10'----01---0 ->     4'0110 20'01100000010000000000
  transition:     4'0110 10'----11---0 ->     4'0111 20'01110000010000000000
  transition:     4'0110 10'---------1 ->     4'0000 20'00000000010000000000
  transition:     4'1110 10'-----0---0 ->     4'1110 20'11100000000000010000
  transition:     4'1110 10'-----1-0-0 ->     4'1101 20'11010000000000010000
  transition:     4'1110 10'-----1-1-0 ->     4'0110 20'01100000000000010000
  transition:     4'1110 10'---------1 ->     4'0000 20'00000000000000010000
  transition:     4'0001 10'-----0---0 ->     4'0001 20'00010000000010000000
  transition:     4'0001 10'----01---0 ->     4'0001 20'00010000000010000000
  transition:     4'0001 10'----11---0 ->     4'0010 20'00100000000010000000
  transition:     4'0001 10'---------1 ->     4'0000 20'00000000000010000000
  transition:     4'1001 10'-----0---0 ->     4'1001 20'10010100000000000000
  transition:     4'1001 10'----01---0 ->     4'1001 20'10010100000000000000
  transition:     4'1001 10'----11---0 ->     4'0000 20'00000100000000000000
  transition:     4'1001 10'---------1 ->     4'0000 20'00000100000000000000
  transition:     4'0101 10'-----0---0 ->     4'0101 20'01010000000000000010
  transition:     4'0101 10'-----1---0 ->     4'0110 20'01100000000000000010
  transition:     4'0101 10'---------1 ->     4'0000 20'00000000000000000010
  transition:     4'1101 10'-----0---0 ->     4'1101 20'11011000000000000000
  transition:     4'1101 10'----01---0 ->     4'1101 20'11011000000000000000
  transition:     4'1101 10'----11---0 ->     4'0000 20'00001000000000000000
  transition:     4'1101 10'---------1 ->     4'0000 20'00001000000000000000
  transition:     4'0011 10'-----0---0 ->     4'0011 20'00110000000000000001
  transition:     4'0011 10'-----1---0 ->     4'1010 20'10100000000000000001
  transition:     4'0011 10'---------1 ->     4'0000 20'00000000000000000001
  transition:     4'1011 10'-----0---0 ->     4'1011 20'10110001000000000000
  transition:     4'1011 10'----01---0 ->     4'1011 20'10110001000000000000
  transition:     4'1011 10'----11---0 ->     4'1100 20'11000001000000000000
  transition:     4'1011 10'---------1 ->     4'0000 20'00000001000000000000
  transition:     4'0111 10'-----0---0 ->     4'0111 20'01110000100000000000
  transition:     4'0111 10'----01---0 ->     4'0111 20'01110000100000000000
  transition:     4'0111 10'---011---0 ->     4'1000 20'10000000100000000000
  transition:     4'0111 10'---111---0 ->     4'1111 20'11110000100000000000
  transition:     4'0111 10'---------1 ->     4'0000 20'00000000100000000000
  transition:     4'1111 10'-----0---0 ->     4'1111 20'11110000000000100000
  transition:     4'1111 10'-----1--00 ->     4'1001 20'10010000000000100000
  transition:     4'1111 10'---------1 ->     4'0000 20'00000000000000100000

34.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627' from module `\processorci_top'.
  Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5575.
Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622' from module `\processorci_top'.
  Merging pattern 2'-0 and 2'-1 from group (1 0 5'10000).
  Merging pattern 2'-1 and 2'-0 from group (1 0 5'10000).
Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617' from module `\processorci_top'.
  Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000).
  Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5611' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5604' from module `\processorci_top'.

34.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 64 unused cells and 64 unused wires.
<suppressed ~65 debug messages>

34.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5604' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5611' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2702_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2704_CMP.
Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617' from module `\processorci_top'.
  Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] [0].
  Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] [1].
Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622' from module `\processorci_top'.
  Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] [0].
  Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] [1].
Optimizing FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627' from module `\processorci_top'.
  Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [0].
  Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [1].
  Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [2].
  Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [3].

34.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5604' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5611' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---
Recoding FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  0000 -> ---------------1
  1000 -> --------------1-
  0100 -> -------------1--
  1100 -> ------------1---
  0010 -> -----------1----
  1010 -> ----------1-----
  0110 -> ---------1------
  1110 -> --------1-------
  0001 -> -------1--------
  1001 -> ------1---------
  0101 -> -----1----------
  1101 -> ----1-----------
  0011 -> ---1------------
  1011 -> --1-------------
  0111 -> -1--------------
  1111 -> 1---------------

34.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5604' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$5604 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1589_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1580_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1576_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1575_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1563_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5611' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$5611 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1449_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2691_CMP
    1: $flatten\Controller.\Uart.$procmux$2697_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617 (\Processor.N1.Second_Stage.Mdu.state_div):

  Number of input signals:    3
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$162_Y
    2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$181_Y

  Output signals:
    0: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4535_CMP
    1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4539_CMP
    2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4545_CMP

  State encoding:
    0:      3'--1  <RESET STATE>
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 3'-00   ->     0 3'010
      1:     0 3'--1   ->     0 3'010
      2:     0 3'-10   ->     2 3'010
      3:     1 3'---   ->     0 3'100
      4:     2 3'--1   ->     0 3'001
      5:     2 3'1-0   ->     1 3'001
      6:     2 3'0-0   ->     2 3'001

-------------------------------------

FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622 (\Processor.N1.Second_Stage.Mdu.state_mul):

  Number of input signals:    2
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$199_Y

  Output signals:
    0: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4475_CMP
    1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4479_CMP
    2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4485_CMP

  State encoding:
    0:      3'--1  <RESET STATE>
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 3'010
      1:     0 2'-1   ->     0 3'010
      2:     0 2'10   ->     2 3'010
      3:     1 2'--   ->     0 3'100
      4:     2 2'-1   ->     0 3'001
      5:     2 2'-0   ->     1 3'001

-------------------------------------

FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627 (\Processor.N1.Third_Stage.unaligned_access_state):

  Number of input signals:    9
  Number of output signals:  16
  Number of state bits:      16

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $auto$opt_reduce.cc:137:opt_pmux$5591
    2: $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:248$124_Y
    3: $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:106$110_Y
    4: $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:98$108_Y
    5: \Processor.N1.Third_Stage.data_memory_response
    6: \Processor.N1.Third_Stage.subword
    7: \Processor.N1.Third_Stage.subword_store
    8: $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:59$572_Y

  Output signals:
    0: $flatten\Processor.\N1.\Third_Stage.$procmux$4748_CMP
    1: $flatten\Processor.\N1.\Third_Stage.$procmux$4685_CMP
    2: $flatten\Processor.\N1.\Third_Stage.$procmux$4684_CMP
    3: $flatten\Processor.\N1.\Third_Stage.$procmux$4682_CMP
    4: $flatten\Processor.\N1.\Third_Stage.$procmux$4680_CMP
    5: $flatten\Processor.\N1.\Third_Stage.$procmux$4679_CMP
    6: $flatten\Processor.\N1.\Third_Stage.$procmux$4663_CMP
    7: $flatten\Processor.\N1.\Third_Stage.$procmux$4662_CMP
    8: $flatten\Processor.\N1.\Third_Stage.$procmux$4661_CMP
    9: $flatten\Processor.\N1.\Third_Stage.$procmux$4660_CMP
   10: $flatten\Processor.\N1.\Third_Stage.$procmux$4657_CMP
   11: $flatten\Processor.\N1.\Third_Stage.$procmux$4654_CMP
   12: $flatten\Processor.\N1.\Third_Stage.$procmux$4651_CMP
   13: $flatten\Processor.\N1.\Third_Stage.$procmux$4627_CMP
   14: $flatten\Processor.\N1.\Third_Stage.$procmux$4626_CMP
   15: $flatten\Processor.\N1.\Third_Stage.$procmux$4623_CMP

  State encoding:
    0: 16'---------------1  <RESET STATE>
    1: 16'--------------1-
    2: 16'-------------1--
    3: 16'------------1---
    4: 16'-----------1----
    5: 16'----------1-----
    6: 16'---------1------
    7: 16'--------1-------
    8: 16'-------1--------
    9: 16'------1---------
   10: 16'-----1----------
   11: 16'----1-----------
   12: 16'---1------------
   13: 16'--1-------------
   14: 16'-1--------------
   15: 16'1---------------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 9'00--10--0   ->     0 16'0000000001000000
      1:     0 9'----0---0   ->     0 16'0000000001000000
      2:     0 9'--------1   ->     0 16'0000000001000000
      3:     0 9'00--11--0   ->     2 16'0000000001000000
      4:     0 9'10--1---0   ->     8 16'0000000001000000
      5:     0 9'-1--1---0   ->    13 16'0000000001000000
      6:     1 9'--------1   ->     0 16'0000000000000100
      7:     1 9'----0---0   ->     1 16'0000000000000100
      8:     1 9'----1--00   ->     9 16'0000000000000100
      9:     2 9'--------1   ->     0 16'0000001000000000
     10:     2 9'----0---0   ->     2 16'0000001000000000
     11:     2 9'---01---0   ->     2 16'0000001000000000
     12:     2 9'--111---0   ->     7 16'0000001000000000
     13:     2 9'--011---0   ->    10 16'0000001000000000
     14:     3 9'--------1   ->     0 16'0000000000001000
     15:     3 9'----0---0   ->     3 16'0000000000001000
     16:     3 9'----1---0   ->    11 16'0000000000001000
     17:     4 9'--------1   ->     0 16'0000000100000000
     18:     4 9'----0---0   ->     4 16'0000000100000000
     19:     4 9'---01---0   ->     4 16'0000000100000000
     20:     4 9'---11---0   ->    12 16'0000000100000000
     21:     5 9'----1---0   ->     0 16'0010000000000000
     22:     5 9'--------1   ->     0 16'0010000000000000
     23:     5 9'----0---0   ->     5 16'0010000000000000
     24:     6 9'--------1   ->     0 16'0000010000000000
     25:     6 9'----0---0   ->     6 16'0000010000000000
     26:     6 9'---01---0   ->     6 16'0000010000000000
     27:     6 9'---11---0   ->    14 16'0000010000000000
     28:     7 9'--------1   ->     0 16'0000000000010000
     29:     7 9'----1-1-0   ->     6 16'0000000000010000
     30:     7 9'----0---0   ->     7 16'0000000000010000
     31:     7 9'----1-0-0   ->    11 16'0000000000010000
     32:     8 9'--------1   ->     0 16'0000000010000000
     33:     8 9'---11---0   ->     4 16'0000000010000000
     34:     8 9'----0---0   ->     8 16'0000000010000000
     35:     8 9'---01---0   ->     8 16'0000000010000000
     36:     9 9'---11---0   ->     0 16'0100000000000000
     37:     9 9'--------1   ->     0 16'0100000000000000
     38:     9 9'----0---0   ->     9 16'0100000000000000
     39:     9 9'---01---0   ->     9 16'0100000000000000
     40:    10 9'--------1   ->     0 16'0000000000000010
     41:    10 9'----1---0   ->     6 16'0000000000000010
     42:    10 9'----0---0   ->    10 16'0000000000000010
     43:    11 9'---11---0   ->     0 16'1000000000000000
     44:    11 9'--------1   ->     0 16'1000000000000000
     45:    11 9'----0---0   ->    11 16'1000000000000000
     46:    11 9'---01---0   ->    11 16'1000000000000000
     47:    12 9'--------1   ->     0 16'0000000000000001
     48:    12 9'----1---0   ->     5 16'0000000000000001
     49:    12 9'----0---0   ->    12 16'0000000000000001
     50:    13 9'--------1   ->     0 16'0001000000000000
     51:    13 9'---11---0   ->     3 16'0001000000000000
     52:    13 9'----0---0   ->    13 16'0001000000000000
     53:    13 9'---01---0   ->    13 16'0001000000000000
     54:    14 9'--------1   ->     0 16'0000100000000000
     55:    14 9'--011---0   ->     1 16'0000100000000000
     56:    14 9'----0---0   ->    14 16'0000100000000000
     57:    14 9'---01---0   ->    14 16'0000100000000000
     58:    14 9'--111---0   ->    15 16'0000100000000000
     59:    15 9'--------1   ->     0 16'0000000000100000
     60:    15 9'----1--00   ->     9 16'0000000000100000
     61:    15 9'----0---0   ->    15 16'0000000000100000

-------------------------------------

34.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5604' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5611' from module `\processorci_top'.
Mapping FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5617' from module `\processorci_top'.
Mapping FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5622' from module `\processorci_top'.
Mapping FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5627' from module `\processorci_top'.

34.13. Executing OPT pass (performing simple optimizations).

34.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~32 debug messages>

34.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~105 debug messages>
Removed a total of 35 cells.

34.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~254 debug messages>

34.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5308 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5306 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5424 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4622_Y, Q = \Processor.N1.Third_Stage.unaligned_access_o, rval = 1'0).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5423 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4715_Y, Q = \Processor.N1.Third_Stage.memory_operation_o).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5422 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y [7:0], Q = \Processor.N1.Third_Stage.Merged_Word_o [7:0]).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5422 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y [15:8], Q = \Processor.N1.Third_Stage.Merged_Word_o [15:8]).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5422 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y [31:16], Q = \Processor.N1.Third_Stage.Merged_Word_o [31:16]).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5421 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.IMMEDIATE_i, Q = \Processor.N1.Third_Stage.IMMEDIATE_REG_o).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5420 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4772_Y, Q = \Processor.N1.Third_Stage.EXMEMPC_o, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6040 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4769_Y, Q = \Processor.N1.Third_Stage.EXMEMPC_o).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5419 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4784_Y, Q = \Processor.N1.Third_Stage.EXMEMIR_o, rval = 51).
Adding EN signal on $auto$ff.cc:266:slice$6048 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4781_Y, Q = \Processor.N1.Third_Stage.EXMEMIR_o).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5418 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:279$149_Y, Q = \Processor.N1.Third_Stage.EXMEMALUOut_o).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5417 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4823_Y, Q = \Processor.N1.Third_Stage.Data_Address).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5416 ($dff) from module processorci_top (D = \Processor.N1.Fourth_Stage.read_data_i, Q = \Processor.N1.Third_Stage.Second_Word).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5415 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4850_Y, Q = \Processor.N1.Third_Stage.First_Word).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5413 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4921_Y, Q = \Processor.N1.Third_Stage.subword, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6094 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$logic_not$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:223$172_Y, Q = \Processor.N1.Third_Stage.subword).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5412 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4943_Y, Q = \Processor.N1.Third_Stage.unaligned_access_in_progress, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6104 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4943_Y, Q = \Processor.N1.Third_Stage.unaligned_access_in_progress).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5411 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4989_Y [7:0], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0]).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5411 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4989_Y [15:8], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:8]).
Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5411 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4989_Y [31:16], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [31:16]).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5410 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4686_Y, Q = \Processor.N1.Third_Stage.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5409 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4664_Y, Q = \Processor.N1.Third_Stage.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5408 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$5007_Y, Q = \Processor.N1.Third_Stage.subword_store, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6175 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$5007_Y, Q = \Processor.N1.Third_Stage.subword_store).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5407 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4551_Y, Q = \Processor.N1.Second_Stage.Mdu.divisor).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5406 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4562_Y, Q = \Processor.N1.Second_Stage.Mdu.DIV_RD).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5405 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4571_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente_msk).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5404 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4584_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6210 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4584_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5403 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4597_Y, Q = \Processor.N1.Second_Stage.Mdu.dividendo).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5402 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4544_Y, Q = \Processor.N1.Second_Stage.Mdu.div_ready_o, rval = 1'0).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5401 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:223$180_Y, Q = \Processor.N1.Second_Stage.Mdu.negativo).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5399 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201_Y, Q = \Processor.N1.Second_Stage.Mdu.acumulador).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5398 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4504_Y, Q = \Processor.N1.Second_Stage.Mdu.Data_Y, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6242 ($sdff) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.MDU_RS2_i, Q = \Processor.N1.Second_Stage.Mdu.Data_Y).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5397 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4518_Y, Q = \Processor.N1.Second_Stage.Mdu.Data_X, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6246 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_data_in, Q = \Processor.N1.Second_Stage.Mdu.Data_X).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5395 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4524_Y, Q = \Processor.N1.Second_Stage.Mdu.MUL_RD, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6250 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:97$203_Y, Q = \Processor.N1.Second_Stage.Mdu.MUL_RD).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5394 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4484_Y, Q = \Processor.N1.Second_Stage.Mdu.mul_ready_o, rval = 1'0).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5342 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y, Q = \Processor.N1.Second_Stage.IDEXB).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5341 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y, Q = \Processor.N1.Second_Stage.IDEXA).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5340 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3534_Y, Q = \Processor.N1.Second_Stage.previous_instruction_is_lw, rval = 1'0).
Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5339 ($dff) from module processorci_top (D = \Processor.N1.Second_Stage.aluop_out, Q = \Processor.N1.Second_Stage.alu_op_o).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5337 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3541_Y, Q = \Processor.N1.Second_Stage.mdu_start, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5336 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3570_Y, Q = \Processor.N1.Second_Stage.mdu_operation_o, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6266 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3541_Y, Q = \Processor.N1.Second_Stage.mdu_operation_o).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5335 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3576_Y, Q = \Processor.N1.Second_Stage.IDEXPC_o, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6268 ($sdff) from module processorci_top (D = \Processor.N1.First_Stage.IFID_PC_o, Q = \Processor.N1.Second_Stage.IDEXPC_o).
Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5334 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3582_Y, Q = \Processor.N1.Second_Stage.IDEXIR_o, rval = 51).
Adding EN signal on $auto$ff.cc:266:slice$6270 ($sdff) from module processorci_top (D = \Processor.N1.First_Stage.IFID_IR_o, Q = \Processor.N1.Second_Stage.IDEXIR_o).
Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5317 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEMIR_o, Q = \Processor.N1.Fourth_Stage.MEMWB_IR, rval = 51).
Adding EN signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5316 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEMALUOut_o, Q = \Processor.N1.Fourth_Stage.MEMWBALUOut).
Adding EN signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5315 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y, Q = \Processor.N1.Fourth_Stage.MEMWB_mem_read_data).
Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5314 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$procmux$3028_Y, Q = \Processor.N1.Fourth_Stage.mem_to_reg, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5312 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$procmux$3033_Y, Q = \Processor.N1.Fourth_Stage.reg_wr_en_o, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procdff$5343 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$lookahead\prediction$350[1023:0]$394, Q = \Processor.N1.First_Stage.Branch_Prediction.prediction, rval = 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6277 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$lookahead\prediction$350[1023:0]$394, Q = \Processor.N1.First_Stage.Branch_Prediction.prediction).
Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5372 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.PC, Q = \Processor.N1.First_Stage.temp_pc).
Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5371 ($dff) from module processorci_top (D = { 16'0000000000000000 \Processor.N1.First_Stage.instruction_data_i [31:16] }, Q = \Processor.N1.First_Stage.temp_instruction).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5369 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4165_Y, Q = \Processor.N1.First_Stage.finish_unaligned_pc, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6317 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4160_Y, Q = \Processor.N1.First_Stage.finish_unaligned_pc).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5368 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4209_Y, Q = \Processor.N1.First_Stage.pc_is_unaligned, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6325 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4209_Y, Q = \Processor.N1.First_Stage.pc_is_unaligned).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5365 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4244_Y, Q = \Processor.N1.First_Stage.PC, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6335 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4244_Y, Q = \Processor.N1.First_Stage.PC).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5363 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4093_Y, Q = \Processor.N1.First_Stage.flush_bus_o, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5362 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4262_Y, Q = \Processor.N1.First_Stage.IFID_IR_o, rval = 51).
Adding EN signal on $auto$ff.cc:266:slice$6346 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4260_Y, Q = \Processor.N1.First_Stage.IFID_IR_o).
Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5361 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4304_Y, Q = \Processor.N1.First_Stage.IFID_PC_o).
Adding SRST signal on $auto$ff.cc:266:slice$6350 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4292_Y, Q = \Processor.N1.First_Stage.IFID_PC_o, rval = 0).
Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5360 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.is_compressed_instruction, Q = \Processor.N1.First_Stage.IFID_is_compressed_instruction_o, rval = 1'0).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5438 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5104_Y, Q = \Processor.N1.CSR.MINSTRET_reg, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6365 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68_Y, Q = \Processor.N1.CSR.MINSTRET_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5437 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67_Y, Q = \Processor.N1.CSR.MCYCLE_reg, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5436 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5032_Y, Q = \Processor.N1.CSR.MSCRATCH_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6368 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MSCRATCH_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5435 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5044_Y, Q = \Processor.N1.CSR.MTVEC_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6372 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MTVEC_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5434 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5052_Y, Q = \Processor.N1.CSR.MIE_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6376 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MIE_reg).
Adding EN signal on $flatten\Processor.\N1.\CSR.$procdff$5433 ($dff) from module processorci_top (D = 0, Q = \Processor.N1.CSR.MIP_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5432 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5063_Y, Q = \Processor.N1.CSR.MTVAL_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6381 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MTVAL_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5431 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5072_Y, Q = \Processor.N1.CSR.MCAUSE_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6385 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MCAUSE_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5430 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5086_Y, Q = \Processor.N1.CSR.MSTATUS_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6389 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MSTATUS_reg).
Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5429 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5096_Y, Q = \Processor.N1.CSR.MEPC_reg, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6393 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MEPC_reg).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5327 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3153_Y, Q = \Processor.M1.d_cache_response, rval = 1'0).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5326 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3161_Y, Q = \Processor.M1.i_cache_response, rval = 1'0).
Adding EN signal on $flatten\Processor.\M1.$procdff$5325 ($dff) from module processorci_top (D = \Processor.M1.memory_read_data, Q = \Processor.M1.d_cache_read_data).
Adding EN signal on $flatten\Processor.\M1.$procdff$5324 ($dff) from module processorci_top (D = \Processor.M1.memory_read_data, Q = \Processor.M1.i_cache_read_data).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5323 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3191_Y, Q = \Processor.M1.access_pedding, rval = 1'0).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5322 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3201_Y, Q = \Processor.M1.response_out, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6420 ($sdff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3199_Y, Q = \Processor.M1.response_out).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5321 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3211_Y, Q = \Processor.M1.requested_memory_addr, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6428 ($sdff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3209_Y, Q = \Processor.M1.requested_memory_addr).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5320 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3223_Y, Q = \Processor.M1.write_request, rval = 1'0).
Adding EN signal on $flatten\Processor.\M1.$procdff$5319 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEM_mem_data_value, Q = \Processor.M1.write_data).
Adding SRST signal on $flatten\Processor.\M1.$procdff$5318 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3243_Y, Q = \Processor.M1.read_request, rval = 1'0).
Adding SRST signal on $flatten\Processor.\ICache.$procdff$5442 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$2$lookahead\cache_valid$16[7:0]$55, Q = \Processor.ICache.cache_valid, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6445 ($sdff) from module processorci_top (D = $flatten\Processor.\ICache.$or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$63_Y, Q = \Processor.ICache.cache_valid).
Adding SRST signal on $flatten\Processor.\ICache.$procdff$5440 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$procmux$5206_Y, Q = \Processor.ICache.clear_response, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6447 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.ICache.clear_response).
Adding SRST signal on $flatten\Processor.\ICache.$procdff$5439 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$procmux$5213_Y, Q = \Processor.ICache.request_to_memory, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6451 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.ICache.request_to_memory).
Adding SRST signal on $flatten\Processor.\DCache.$procdff$5377 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$procmux$4465_Y, Q = \Processor.DCache.write_through, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6455 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.DCache.write_through).
Adding SRST signal on $flatten\Processor.\DCache.$procdff$5376 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$3$lookahead\cache_valid$225[7:0]$284, Q = \Processor.DCache.cache_valid, rval = 8'00000000).
Adding SRST signal on $flatten\Processor.\DCache.$procdff$5375 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$procmux$4459_Y, Q = \Processor.DCache.miss_finished, rval = 1'0).
Adding SRST signal on $flatten\Processor.$procdff$5310 ($dff) from module processorci_top (D = $flatten\Processor.$procmux$2993_Y, Q = \Processor.peripheral_wr_through, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6461 ($sdff) from module processorci_top (D = $flatten\Processor.$procmux$2993_Y, Q = \Processor.peripheral_wr_through).
Adding SRST signal on $flatten\Processor.$procdff$5309 ($dff) from module processorci_top (D = $flatten\Processor.$procmux$3001_Y, Q = \Processor.peripheral_access_lock, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6465 ($sdff) from module processorci_top (D = $flatten\Processor.$procmux$3001_Y, Q = \Processor.peripheral_access_lock).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5250 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1913_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1907_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1898_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1889_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1880_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1871_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1853_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1862_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6469 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$6469 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1907_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1898_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1889_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1880_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1871_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1853_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1862_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5248 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1829_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6474 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1829_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5247 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1818_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6480 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1543_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5246 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5245 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1807_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$6485 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1807_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5244 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1796_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6491 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5242 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1773_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1764_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1755_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1746_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1737_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1728_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1710_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1719_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6493 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5241 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1692_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6497 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1583_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5240 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1687_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6501 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5239 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1679_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6503 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1594_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5237 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5236 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5235 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1656_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6509 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5234 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1400_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5230 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1651_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6516 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5235 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1656_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6518 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5234 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1400_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5230 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1651_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6525 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5298 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2827_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6527 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2827_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5297 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2852_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6531 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2852_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5296 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2816_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5295 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2867_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6548 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2865_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5294 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2805_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5293 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2749_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6555 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2749_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5292 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2771_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6559 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2771_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5291 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2785_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6569 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2785_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5290 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2799_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6579 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5289 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2731_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5288 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2741_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5287 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2722_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6593 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5286 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2717_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5284 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2712_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6596 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5283 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2688_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$5282 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2696_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5281 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2235_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5280 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2278_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6613 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2278_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$6613 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2278_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5279 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2288_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6628 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2288_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5278 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5277 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2329_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5276 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2357_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6644 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5275 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2382_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5274 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2404_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6655 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5273 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2410_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6657 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2410_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5272 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2434_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5271 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2442_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6672 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2442_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5270 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2482_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6676 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2482_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5268 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2524_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6680 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2524_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5267 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2063_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5266 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2535_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5265 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2168_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5264 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2545_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6693 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2545_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5263 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5262 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2187_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5261 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2210_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5260 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2599_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5259 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2120_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5258 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2653_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6718 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2653_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5257 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1963_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5256 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2677_Y, Q = \Controller.Interpreter.write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5255 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2087_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5254 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2109_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$5251 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1937_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6732 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1937_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$5305 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2888_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6740 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2888_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6632 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6380 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6302 ($dffe) from module processorci_top.

34.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 304 unused cells and 375 unused wires.
<suppressed ~305 debug messages>

34.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~44 debug messages>

34.13.9. Rerunning OPT passes. (Maybe there is more to do..)

34.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~194 debug messages>

34.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6499: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
    New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5110: { $auto$opt_reduce.cc:137:opt_pmux$5505 $auto$opt_reduce.cc:137:opt_pmux$5503 $auto$opt_reduce.cc:137:opt_pmux$5501 $auto$opt_reduce.cc:137:opt_pmux$5499 $flatten\Processor.\N1.\CSR.$procmux$5119_CMP $flatten\Processor.\N1.\CSR.$procmux$5085_CMP $flatten\Processor.\N1.\CSR.$procmux$5051_CMP $flatten\Processor.\N1.\CSR.$procmux$5043_CMP $flatten\Processor.\N1.\CSR.$procmux$5031_CMP $flatten\Processor.\N1.\CSR.$procmux$5095_CMP $flatten\Processor.\N1.\CSR.$procmux$5071_CMP $flatten\Processor.\N1.\CSR.$procmux$5062_CMP }
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

34.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~336 debug messages>
Removed a total of 112 cells.

34.13.13. Executing OPT_DFF pass (perform DFF optimizations).

34.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 113 unused wires.
<suppressed ~2 debug messages>

34.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.13.16. Rerunning OPT passes. (Maybe there is more to do..)

34.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~196 debug messages>

34.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.13.20. Executing OPT_DFF pass (perform DFF optimizations).

34.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.13.23. Finished OPT passes. (There is nothing left to do.)

34.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$5452 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1210 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$5452 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1210 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5451 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1400 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5451 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1400 (Controller.Uart.TX_FIFO.memory).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Processor.\N1.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$5461 (Processor.N1.RegisterBank.registers).
Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6000 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5665 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5654 ($eq).
Removed top 2 bits (of 5) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5789 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5981 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5679 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1501 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1458 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1462 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1465 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1474 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1479 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1481 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1964_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1965_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1967 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1969_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1970_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1971_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1972_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1973_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1975 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1977_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1978_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1980 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1982_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1983_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1987_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1988_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1989_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1991 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1993_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1994_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1995_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1997 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1999_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2001 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2003_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2004_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2005_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2006_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2007_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2008_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2009_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2011 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2013_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2015 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2017_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2018_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2020 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2022_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2023_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2026_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2025 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2027_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2028_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2029_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2030_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2031_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2032_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2033_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2034_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2035_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2036_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2037_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2038_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2039_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2040_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2041_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2043_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2044_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2045_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2046_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2047_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2048_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2049_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2051 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2053_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2055 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2089_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2090_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2091_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2124_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2279_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2280_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2281_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2324_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2450_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2483_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2484_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2557_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2558_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1432 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1437 ($lt).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5962 ($ne).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2736_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2742_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2743_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2755_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2757 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2806_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2807_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2821_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2829_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2837 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1648 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1636 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1417 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1401 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1648 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1636 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1417 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1401 ($eq).
Removed top 2 bits (of 5) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5759 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1572 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1571 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1570 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1569 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1564 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1562 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1538 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1530 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1528 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1525 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1524 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1520 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1515 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1514 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1513 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1512 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1508 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1506 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2879 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2879 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$1187 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1171 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1170 ($mux).
Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5891 ($eq).
Removed top 4 bits (of 5) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5990 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6109 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6043 ($ne).
Removed top 2 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6069 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6075 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6122 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6180 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6191 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6217 ($ne).
Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6282 ($ne).
Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6332 ($ne).
Removed top 2 bits (of 6) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6330 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5939 ($eq).
Removed top 28 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\DCache.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$217 ($shiftx).
Removed top 29 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270 ($neg).
Converting cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270 ($neg) from signed to unsigned.
Removed top 1 bits (of 4) from port A of cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270 ($neg).
Removed top 28 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\ICache.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$9 ($shiftx).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5704 ($eq).
Removed top 29 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg).
Converting cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg) from signed to unsigned.
Removed top 1 bits (of 4) from port A of cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg).
Removed top 29 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$481 ($mux).
Removed top 22 bits (of 32) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$347 ($add).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$347 ($add).
Removed top 21 bits (of 32) from port Y of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$347 ($add).
Removed top 20 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$348 ($shiftx).
Removed top 21 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$402 ($shiftx).
Removed top 22 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407 ($neg).
Converting cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407 ($neg) from signed to unsigned.
Removed top 1 bits (of 11) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407 ($neg).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$413 ($add).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$429 ($sub).
Removed top 21 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$464 ($shiftx).
Removed top 22 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469 ($neg).
Converting cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469 ($neg) from signed to unsigned.
Removed top 1 bits (of 11) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469 ($neg).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$475 ($add).
Removed top 3 bits (of 5) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:104$525 ($eq).
Removed top 11 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3252 ($mux).
Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3268 ($mux).
Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3298 ($mux).
Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3333 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3347_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364_CMP1 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3385_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3386_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3387_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3394_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3419_CMP1 ($eq).
Removed top 3 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3462 ($mux).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335 ($add).
Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$315 ($add).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$181 ($eq).
Removed top 31 bits (of 63) from port Y of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183 ($sub).
Removed top 31 bits (of 63) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183 ($sub).
Removed top 32 bits (of 64) from port A of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201 ($mul).
Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201 ($mul).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ForwardBMUX.$procmux$2936_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ForwardAMUX.$procmux$2936_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2939 ($mux).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2946 ($mux).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2954 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ne$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:26$583 ($ne).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$594 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$596 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$600 ($mux).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3008_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3009_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3010_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3015_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3019_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3020_CMP0 ($eq).
Removed top 2 bits (of 4) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$551 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3059_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3060_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3061_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3075_CMP0 ($eq).
Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6272 ($sdff).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP4 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP3 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP2 ($eq).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP1 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3597_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3589_CMP3 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3589_CMP2 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3589_CMP1 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3589_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:104$517 ($eq).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:97$516 ($eq).
Removed top 22 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6041 ($sdffe).
Removed top 17 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6049 ($sdffe).
Removed top 16 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4968 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6735 ($ne).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4964_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4963_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4962_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6745 ($ne).
Removed top 17 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4781 ($mux).
Removed top 17 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4778 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4769 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4766 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:129$112 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:118$111 ($add).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:106$110 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$procmux$3051_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:59$572 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:58$570 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:56$563 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:55$561 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:54$560 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5119_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5095_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5085_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5071_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5062_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5051_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5050_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5043_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5031_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5025_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2905_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1157 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1155 ($lt).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1170_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_ADDR[31:0]$1214.
Removed top 2 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1210_DATA.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1967_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1975_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1980_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1991_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1997_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2001_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2011_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2015_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2020_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2025_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2051_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2055_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1208_ADDR[31:0]$1214.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2757_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2837_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1405.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1414.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1405.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1395_ADDR[5:0]$1414.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1403_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1419_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1569_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1570_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1571_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1572_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1512_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1513_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1514_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1515_Y.
Removed top 21 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$347_Y.
Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$10\instr_d_o[31:0].
Removed top 11 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$11\instr_d_o[31:0].
Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$8\instr_d_o[31:0].
Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$9\instr_d_o[31:0].
Removed top 29 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$481_Y.
Removed top 2 bits (of 4) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$551_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$594_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$596_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$600_Y.
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$2\fwd_rs1_o[1:0].
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$3\fwd_rs1_o[1:0].
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$3\fwd_rs2_o[1:0].
Removed top 31 bits (of 63) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4766_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4769_Y.
Removed top 17 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4778_Y.
Removed top 17 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4781_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156_Y.

34.15. Executing PEEPOPT pass (run peephole optimizers).
shiftadd pattern in processorci_top: shift=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$348, add/sub=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$347, offset: 1

34.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 58 unused wires.
<suppressed ~2 debug messages>

34.17. Executing SHARE pass (SAT-based resource sharing).
Found 9 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3008_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3009_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$3010_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:20$89 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y }.
    Found 1 candidates: $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83
    Analyzing resource sharing with $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83 ($memrd):
      Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y }.
      Activation pattern for cell $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:20$89: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y } = 2'01
      Activation pattern for cell $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y } = 2'01
      Size of SAT problem: 0 cells, 616 variables, 1461 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y } = 3'001
  Analyzing resource sharing options for $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$memrd$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:82$345 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Processor.N1.Second_Stage.branch_flush_i \Processor.N1.Second_Stage.take_jalr_o \Processor.N1.First_Stage.pc_is_unaligned \Processor.N1.First_Stage.finish_unaligned_pc \Processor.N1.First_Stage.take_jal_o $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:151$327_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$332_Y \Processor.N1.First_Stage.Branch_Prediction.prediction_taken_o }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Processor.\DCache.$memrd$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:79$224 ($memrd):
    Found 1 activation_patterns using ctrl signal \Processor.N1.Third_Stage.Data_Address [31].
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1210 ($memrd):
    Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$2007_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1210 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$2007_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

34.18. Executing TECHMAP pass (map to technology primitives).

34.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v
Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

34.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~223 debug messages>

34.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

34.21. Executing TECHMAP pass (map to technology primitives).

34.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v
Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

34.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

34.21.3. Continuing TECHMAP pass.
Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul.
Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul.
Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul.
Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul.
Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul.
Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul.
Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul.
Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~670 debug messages>

34.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6819 ($add).
  creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6816 ($add).
  creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.$add$/usr/local/share/synlig/mul2dsp.v:173$6813 ($add).
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1502 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1457 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1461 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1462 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1465 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1472 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1476 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1464 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1439 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1434 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1583 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1594 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1532 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1543 ($add).
  creating $macc model for $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270 ($neg).
  creating $macc model for $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg).
  creating $macc model for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67 ($add).
  creating $macc model for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$308 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$312 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$315 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$413 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$475 ($add).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407 ($neg).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469 ($neg).
  creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$429 ($sub).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$588 ($add).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$589 ($sub).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$165 ($neg).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$169 ($neg).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$189 ($neg).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$191 ($neg).
  creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183 ($sub).
  creating $macc model for $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:118$111 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156.
  creating $alu model for $macc $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:118$111.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$191.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$189.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$169.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$165.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$589.
  creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$588.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$429.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$475.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$413.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$315.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$312.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$308.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335.
  creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334.
  creating $alu model for $macc $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68.
  creating $alu model for $macc $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67.
  creating $alu model for $macc $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57.
  creating $alu model for $macc $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1543.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1532.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1594.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1583.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1434.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1439.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1464.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1476.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1472.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1465.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1462.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1461.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1457.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1502.
  creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.$add$/usr/local/share/synlig/mul2dsp.v:173$6813.
  creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6816.
  creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6819.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1501 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1481 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1474 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1481.
  creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$599 ($ge): new $alu
  creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$595 ($lt): merged with $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$599.
  creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$le$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:240$182 ($le): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1155 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1479 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1481.
  creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$593 ($eq): merged with $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$599.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1157 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1155.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1155, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1157: $auto$alumacc.cc:485:replace_alu$6833
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$le$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:240$182: $auto$alumacc.cc:485:replace_alu$6844
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1481, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1474, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1479: $auto$alumacc.cc:485:replace_alu$6857
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1501: $auto$alumacc.cc:485:replace_alu$6870
  creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6819: $auto$alumacc.cc:485:replace_alu$6875
  creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6816: $auto$alumacc.cc:485:replace_alu$6878
  creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$201.$add$/usr/local/share/synlig/mul2dsp.v:173$6813: $auto$alumacc.cc:485:replace_alu$6881
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1502: $auto$alumacc.cc:485:replace_alu$6884
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1457: $auto$alumacc.cc:485:replace_alu$6887
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1461: $auto$alumacc.cc:485:replace_alu$6890
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1462: $auto$alumacc.cc:485:replace_alu$6893
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1465: $auto$alumacc.cc:485:replace_alu$6896
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1472: $auto$alumacc.cc:485:replace_alu$6899
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1476: $auto$alumacc.cc:485:replace_alu$6902
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1464: $auto$alumacc.cc:485:replace_alu$6905
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1439: $auto$alumacc.cc:485:replace_alu$6908
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1434: $auto$alumacc.cc:485:replace_alu$6911
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402: $auto$alumacc.cc:485:replace_alu$6914
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418: $auto$alumacc.cc:485:replace_alu$6917
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420: $auto$alumacc.cc:485:replace_alu$6920
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1402: $auto$alumacc.cc:485:replace_alu$6923
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1418: $auto$alumacc.cc:485:replace_alu$6926
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1420: $auto$alumacc.cc:485:replace_alu$6929
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1583: $auto$alumacc.cc:485:replace_alu$6932
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1594: $auto$alumacc.cc:485:replace_alu$6935
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1532: $auto$alumacc.cc:485:replace_alu$6938
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1543: $auto$alumacc.cc:485:replace_alu$6941
  creating $alu cell for $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$270: $auto$alumacc.cc:485:replace_alu$6944
  creating $alu cell for $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57: $auto$alumacc.cc:485:replace_alu$6947
  creating $alu cell for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67: $auto$alumacc.cc:485:replace_alu$6950
  creating $alu cell for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68: $auto$alumacc.cc:485:replace_alu$6953
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334: $auto$alumacc.cc:485:replace_alu$6956
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335: $auto$alumacc.cc:485:replace_alu$6959
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$308: $auto$alumacc.cc:485:replace_alu$6962
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$312: $auto$alumacc.cc:485:replace_alu$6965
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$315: $auto$alumacc.cc:485:replace_alu$6968
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$413: $auto$alumacc.cc:485:replace_alu$6971
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$475: $auto$alumacc.cc:485:replace_alu$6974
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$407: $auto$alumacc.cc:485:replace_alu$6977
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$469: $auto$alumacc.cc:485:replace_alu$6980
  creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$429: $auto$alumacc.cc:485:replace_alu$6983
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$599, $flatten\Processor.\N1.\Second_Stage.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$595, $flatten\Processor.\N1.\Second_Stage.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$593: $auto$alumacc.cc:485:replace_alu$6986
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$588: $auto$alumacc.cc:485:replace_alu$6999
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$589: $auto$alumacc.cc:485:replace_alu$7002
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$165: $auto$alumacc.cc:485:replace_alu$7005
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$169: $auto$alumacc.cc:485:replace_alu$7008
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$189: $auto$alumacc.cc:485:replace_alu$7011
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$191: $auto$alumacc.cc:485:replace_alu$7014
  creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$183: $auto$alumacc.cc:485:replace_alu$7017
  creating $alu cell for $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:118$111: $auto$alumacc.cc:485:replace_alu$7020
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1156: $auto$alumacc.cc:485:replace_alu$7023
  created 51 $alu and 0 $macc cells.

34.23. Executing OPT pass (performing simple optimizations).

34.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

34.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~196 debug messages>

34.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

34.23.6. Executing OPT_DFF pass (perform DFF optimizations).

34.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 64 unused wires.
<suppressed ~2 debug messages>

34.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.23.9. Rerunning OPT passes. (Maybe there is more to do..)

34.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~196 debug messages>

34.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.23.13. Executing OPT_DFF pass (perform DFF optimizations).

34.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.23.16. Finished OPT passes. (There is nothing left to do.)

34.24. Executing MEMORY pass.

34.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

34.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

34.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.Processor.DCache.cache_data write port 0.
  Analyzing processorci_top.Processor.DCache.cache_data write port 1.
  Analyzing processorci_top.Processor.DCache.cache_tag write port 0.
  Analyzing processorci_top.Processor.DCache.cache_tag write port 1.
  Analyzing processorci_top.Processor.ICache.cache_data write port 0.
  Analyzing processorci_top.Processor.ICache.cache_tag write port 0.
  Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 0.
  Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 1.
  Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 2.
  Analyzing processorci_top.Processor.N1.RegisterBank.registers write port 0.
  Analyzing processorci_top.Processor.N1.RegisterBank.registers write port 1.

34.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

34.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Processor.DCache.cache_data'[0] in module `\processorci_top': no output FF found.
Checking read port `\Processor.DCache.cache_tag'[0] in module `\processorci_top': no output FF found.
Checking read port `\Processor.ICache.cache_data'[0] in module `\processorci_top': no output FF found.
Checking read port `\Processor.ICache.cache_tag'[0] in module `\processorci_top': no output FF found.
Checking read port `\Processor.N1.First_Stage.Branch_Prediction.address_to_jump'[0] in module `\processorci_top': no output FF found.
Checking read port `\Processor.N1.RegisterBank.registers'[0] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic.
Checking read port `\Processor.N1.RegisterBank.registers'[1] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Processor.DCache.cache_data'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.DCache.cache_tag'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.ICache.cache_data'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.ICache.cache_tag'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.N1.First_Stage.Branch_Prediction.address_to_jump'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.N1.RegisterBank.registers'[0] in module `\processorci_top': merged address FF to cell.
Checking read port address `\Processor.N1.RegisterBank.registers'[1] in module `\processorci_top': merged address FF to cell.

34.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

34.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating write ports of memory processorci_top.Processor.DCache.cache_data by address:
  Merging ports 0, 1 (address \Processor.N1.Third_Stage.Data_Address [4:2]).
Consolidating write ports of memory processorci_top.Processor.DCache.cache_tag by address:
  Merging ports 0, 1 (address \Processor.N1.Third_Stage.Data_Address [4:2]).
Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump by address:
  Merging ports 0, 1 (address \Processor.N1.Second_Stage.IDEXPC_o [9:1]).
Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump by address:
Consolidating read ports of memory processorci_top.Processor.N1.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Processor.N1.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump using sat-based resource sharing:
  Checking group clocked with posedge \Processor.DCache.clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 86 cells.
  Size of unconstrained SAT problem: 6204 variables, 16405 clauses
  Merging port 1 into port 0.

34.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

34.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 10 unused cells and 10 unused wires.
<suppressed ~11 debug messages>

34.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

34.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Processor.DCache.cache_data via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of processorci_top.Processor.DCache.cache_data: $\Processor.DCache.cache_data$rdreg[0]
mapping memory processorci_top.Processor.DCache.cache_tag via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of processorci_top.Processor.DCache.cache_tag: $\Processor.DCache.cache_tag$rdreg[0]
mapping memory processorci_top.Processor.ICache.cache_data via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of processorci_top.Processor.ICache.cache_data: $\Processor.ICache.cache_data$rdreg[0]
mapping memory processorci_top.Processor.ICache.cache_tag via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of processorci_top.Processor.ICache.cache_tag: $\Processor.ICache.cache_tag$rdreg[0]
mapping memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump via $__ECP5_PDPW16KD_
using FF mapping for memory processorci_top.Processor.N1.RegisterBank.registers
<suppressed ~3395 debug messages>

34.27. Executing TECHMAP pass (map to technology primitives).

34.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

34.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

34.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150\$__ECP5_PDPW16KD_ for cells of type $__ECP5_PDPW16KD_.
No more expansions possible.
<suppressed ~1100 debug messages>

34.28. Executing OPT pass (performing simple optimizations).

34.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~351 debug messages>

34.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

34.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$5307 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$8299 ($dffe) from module processorci_top.
Adding SRST signal on $\Processor.ICache.cache_data$rdreg[0] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$7063, Q = $\Processor.ICache.cache_data$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$6665 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1476_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6604 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2235_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding EN signal on $auto$ff.cc:266:slice$6336 ($sdffe) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4244_Y [0], Q = \Processor.N1.First_Stage.PC [0]).
Adding SRST signal on $auto$ff.cc:266:slice$6201 ($dffe) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.quociente_msk [31:1], Q = \Processor.N1.Second_Stage.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$6187 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4554_Y [62], Q = \Processor.N1.Second_Stage.Mdu.divisor [62], rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6067 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4823_Y [1:0], Q = \Processor.N1.Third_Stage.Data_Address [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$5977 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y, Q = \Processor.N1.Third_Stage.memory_operation_o, rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$5956 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2902_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

34.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 13 unused cells and 7603 unused wires.
<suppressed ~14 debug messages>

34.28.5. Rerunning OPT passes. (Removed registers in this run.)

34.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~11 debug messages>

34.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

34.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$9600 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$6806 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Adding SRST signal on $auto$ff.cc:266:slice$9592 ($dffe) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.divisor [31:1], Q = \Processor.N1.Second_Stage.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000).

34.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 8 unused wires.
<suppressed ~2 debug messages>

34.28.10. Rerunning OPT passes. (Removed registers in this run.)

34.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.28.13. Executing OPT_DFF pass (perform DFF optimizations).

34.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.28.15. Finished fast OPT passes.

34.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \Processor.N1.RegisterBank.registers in module \processorci_top:
  created 32 $dff cells and 0 static cells of width 32.
Extracted addr FF from read port 0 of processorci_top.Processor.N1.RegisterBank.registers: $\Processor.N1.RegisterBank.registers$rdreg[0]
Extracted addr FF from read port 1 of processorci_top.Processor.N1.RegisterBank.registers: $\Processor.N1.RegisterBank.registers$rdreg[1]
  read interface: 2 $dff and 62 $mux cells.
  write interface: 64 write mux blocks.

34.30. Executing OPT pass (performing simple optimizations).

34.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~88 debug messages>

34.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$7105: $auto$rtlil.cc:2728:ReduceOr$7099 -> 1'1
  Analyzing evaluation results.
    dead port 1/2 on $mux $memory\Processor.N1.RegisterBank.registers$wrmux[0][0][0]$9878.
    dead port 2/2 on $mux $memory\Processor.N1.RegisterBank.registers$wrmux[0][0][0]$9878.
Removed 2 multiplexer ports.
<suppressed ~171 debug messages>

34.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9597: { $auto$opt_dff.cc:194:make_patterns_logic$9594 $auto$fsm_map.cc:74:implement_pattern_cache$5746 $auto$opt_dff.cc:194:make_patterns_logic$6074 $auto$opt_dff.cc:194:make_patterns_logic$6072 $auto$opt_dff.cc:194:make_patterns_logic$6068 $auto$opt_dff.cc:194:make_patterns_logic$5980 }
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9575: { $auto$opt_dff.cc:194:make_patterns_logic$9572 $auto$opt_dff.cc:194:make_patterns_logic$6607 $auto$opt_dff.cc:194:make_patterns_logic$6605 $auto$fsm_map.cc:74:implement_pattern_cache$5699 }
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9587: { $auto$opt_dff.cc:194:make_patterns_logic$9578 $auto$opt_dff.cc:194:make_patterns_logic$9580 $auto$opt_dff.cc:194:make_patterns_logic$9582 $auto$opt_dff.cc:194:make_patterns_logic$9584 $auto$opt_dff.cc:194:make_patterns_logic$6329 $auto$opt_dff.cc:194:make_patterns_logic$6327 $auto$opt_dff.cc:194:make_patterns_logic$6331 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1170:
      Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$6750 [11:0]
      New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$6750 [11:6]
      New connections: $auto$wreduce.cc:461:run$6750 [5:0] = \Controller.core_address_memory [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1975:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$6754 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$6754 [2] $auto$wreduce.cc:461:run$6754 [0] }
      New connections: $auto$wreduce.cc:461:run$6754 [1] = $auto$wreduce.cc:461:run$6754 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1980:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$6755 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6755 [1:0]
      New connections: $auto$wreduce.cc:461:run$6755 [6:2] = { $auto$wreduce.cc:461:run$6755 [1] 3'010 $auto$wreduce.cc:461:run$6755 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1991:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$6756 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6756 [2]
      New connections: { $auto$wreduce.cc:461:run$6756 [3] $auto$wreduce.cc:461:run$6756 [1:0] } = { $auto$wreduce.cc:461:run$6756 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2001:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$6758 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6758 [0]
      New connections: $auto$wreduce.cc:461:run$6758 [3:1] = { $auto$wreduce.cc:461:run$6758 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2015:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$6760 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6760 [0]
      New connections: $auto$wreduce.cc:461:run$6760 [6:1] = { $auto$wreduce.cc:461:run$6760 [0] 1'0 $auto$wreduce.cc:461:run$6760 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2410:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2410_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2410_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2410_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2535:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2535_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2535_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2535_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2545: $auto$opt_reduce.cc:137:opt_pmux$5547
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2749:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$6766 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2749_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$6766 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2749_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2749_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2757:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$6766 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6766 [2]
      New connections: $auto$wreduce.cc:461:run$6766 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2833:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2833_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2833_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2833_Y [3] $flatten\Controller.\Uart.$procmux$2833_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1791:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$6780 [0] 1'0 $auto$wreduce.cc:461:run$6781 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$6783 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$6780 [0] $auto$wreduce.cc:461:run$6781 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$6783 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1572:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6783 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6783 [0]
      New connections: $auto$wreduce.cc:461:run$6783 [1] = $auto$wreduce.cc:461:run$6783 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1928:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$6785 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$6787 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$6785 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$6787 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1515:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6787 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6787 [0]
      New connections: $auto$wreduce.cc:461:run$6787 [1] = $auto$wreduce.cc:461:run$6787 [0]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.$procmux$4218:
      Old ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335_Y [31:2] \Processor.N1.First_Stage.PC [1] 1'x }, B={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334_Y [31:1] 1'x }, Y=$flatten\Processor.\N1.\First_Stage.$procmux$4218_Y
      New ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335_Y [31:2] \Processor.N1.First_Stage.PC [1] }, B=$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334_Y [31:1], Y=$flatten\Processor.\N1.\First_Stage.$procmux$4218_Y [31:1]
      New connections: $flatten\Processor.\N1.\First_Stage.$procmux$4218_Y [0] = 1'x
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.$procmux$4225:
      Old ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335_Y [31:2] \Processor.N1.First_Stage.PC [1] 1'x }, B={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334_Y [31:1] 1'x }, Y=$flatten\Processor.\N1.\First_Stage.$procmux$4225_Y
      New ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$335_Y [31:2] \Processor.N1.First_Stage.PC [1] }, B=$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$334_Y [31:1], Y=$flatten\Processor.\N1.\First_Stage.$procmux$4225_Y [31:1]
      New connections: $flatten\Processor.\N1.\First_Stage.$procmux$4225_Y [0] = 1'x
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3252:
      Old ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 15'000000011100111 }, B=21'100000000000001110011, Y=$auto$wreduce.cc:461:run$6790 [20:0]
      New ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 2'01 }, B=7'0000010, Y={ $auto$wreduce.cc:461:run$6790 [19:15] $auto$wreduce.cc:461:run$6790 [4] $auto$wreduce.cc:461:run$6790 [2] }
      New connections: { $auto$wreduce.cc:461:run$6790 [20] $auto$wreduce.cc:461:run$6790 [14:5] $auto$wreduce.cc:461:run$6790 [3] $auto$wreduce.cc:461:run$6790 [1:0] } = { $auto$wreduce.cc:461:run$6790 [4] 7'0000000 $auto$wreduce.cc:461:run$6790 [2] 5'11011 }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3298:
      Old ports: A={ 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 15'000000001100111 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 8'00000000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110011 }, Y=$auto$wreduce.cc:461:run$6792 [24:0]
      New ports: A={ 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0000001 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 2'10 }, Y={ $auto$wreduce.cc:461:run$6792 [24:15] $auto$wreduce.cc:461:run$6792 [11:7] $auto$wreduce.cc:461:run$6792 [4] $auto$wreduce.cc:461:run$6792 [2] }
      New connections: { $auto$wreduce.cc:461:run$6792 [14:12] $auto$wreduce.cc:461:run$6792 [6:5] $auto$wreduce.cc:461:run$6792 [3] $auto$wreduce.cc:461:run$6792 [1:0] } = { 3'000 $auto$wreduce.cc:461:run$6792 [2] 4'1011 }
    Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3383:
      Old ports: A={ 9'010000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'00001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0110011 }, B={ 9'000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'10001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 16'0110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 16'0110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0110011 \Processor.N1.First_Stage.IR_Decompression.instr_c_i }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0]
      New ports: A={ 9'010000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'000010110011 }, B={ 9'000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 21'100010110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 21'110010110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'111010110011 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [31:10] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:0] }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [6:0] }
      New connections: $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [9:7] = \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3462:
      Old ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110111 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:3] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [5] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6] 24'000000010000000100010011 }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [28:0]
      New ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 1'1 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:3] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [5] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6] 12'010000000100 }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [28:24] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17:7] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [2] }
      New connections: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [23:18] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [6:3] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [1:0] } = { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] 1'0 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [2] 4'1011 }
    Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Fourth_Stage.$procmux$3048:
      Old ports: A=\Processor.N1.Fourth_Stage.read_data_i, B={ \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7:0] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15:0] 24'000000000000000000000000 \Processor.N1.Fourth_Stage.read_data_i [7:0] 16'0000000000000000 \Processor.N1.Fourth_Stage.read_data_i [15:0] }, Y=\Processor.N1.Fourth_Stage.read_data_normalized
      New ports: A=\Processor.N1.Fourth_Stage.read_data_i [31:8], B={ \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15:8] 40'0000000000000000000000000000000000000000 \Processor.N1.Fourth_Stage.read_data_i [15:8] }, Y=\Processor.N1.Fourth_Stage.read_data_normalized [31:8]
      New connections: \Processor.N1.Fourth_Stage.read_data_normalized [7:0] = \Processor.N1.Fourth_Stage.read_data_i [7:0]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$481:
      Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:461:run$6793 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6793 [2:1]
      New connections: $auto$wreduce.cc:461:run$6793 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$550:
      Old ports: A=4'1010, B=4'0010, Y=$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$550_Y
      New ports: A=1'1, B=1'0, Y=$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$550_Y [3]
      New connections: $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$550_Y [2:0] = 3'010
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$551:
      Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:461:run$6794 [1:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6794 [1]
      New connections: $auto$wreduce.cc:461:run$6794 [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2973:
      Old ports: A={ \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31:20] }, B={ \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24:20] 20'00000000000000000000 \Processor.N1.First_Stage.IFID_IR_o [31:20] 27'000000000000000000000000000 \Processor.N1.First_Stage.IFID_IR_o [24:20] }, Y=$flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0]
      New ports: A={ \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31:25] }, B={ \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] 1'0 \Processor.N1.First_Stage.IFID_IR_o [31:25] 8'00000000 }, Y=$flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12:5]
      New connections: { $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [31:13] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [4:0] } = { $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] \Processor.N1.First_Stage.IFID_IR_o [24:20] }
    Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4733:
      Old ports: A={ \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] 8'x }, B={ \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] 80'xxxxxxxxxxxxxxxx000000000000000000000000xxxxxxxx0000000000000000xxxxxxxxxxxxxxxx }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y
      New ports: A={ \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] }, B={ \Processor.N1.Third_Stage.Merged_Word_o [15] 5'x000x }, Y={ $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] }
      New connections: { $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [31:17] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [15:9] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [7:0] } = { $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4733_Y [8] 8'x }
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4974:
      Old ports: A={ \Processor.N1.Third_Stage.Second_Word [31:24] \Processor.N1.Third_Stage.First_Word [31:8] }, B={ \Processor.N1.Third_Stage.Second_Word [31:16] \Processor.N1.Third_Stage.First_Word [31:16] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4974_Y
      New ports: A=\Processor.N1.Third_Stage.First_Word [31:8], B={ \Processor.N1.Third_Stage.Second_Word [23:16] \Processor.N1.Third_Stage.First_Word [31:16] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4974_Y [23:0]
      New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4974_Y [31:24] = \Processor.N1.Third_Stage.Second_Word [31:24]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4983:
      Old ports: A={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:0] }, B={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [15:0] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4983_Y
      New ports: A={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:16] }, B=\Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0], Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4983_Y [31:16]
      New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4983_Y [15:0] = \Processor.N1.Third_Stage.First_Word [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2913: { $flatten\ResetBootSystem.$procmux$2906_CMP $flatten\ResetBootSystem.$procmux$2905_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2916:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2916_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2916_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2916_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2827:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2833_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2827_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2833_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2827_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2827_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3268:
      Old ports: A={ 4'0000 $auto$wreduce.cc:461:run$6790 [20:0] }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 3'000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110011 }, Y=$auto$wreduce.cc:461:run$6789 [24:0]
      New ports: A={ 4'0000 $auto$wreduce.cc:461:run$6790 [4] $auto$wreduce.cc:461:run$6790 [19:15] 4'0000 $auto$wreduce.cc:461:run$6790 [2] 1'1 $auto$wreduce.cc:461:run$6790 [4] $auto$wreduce.cc:461:run$6790 [2] }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 3'010 }, Y={ $auto$wreduce.cc:461:run$6789 [24:15] $auto$wreduce.cc:461:run$6789 [11:6] $auto$wreduce.cc:461:run$6789 [4] $auto$wreduce.cc:461:run$6789 [2] }
      New connections: { $auto$wreduce.cc:461:run$6789 [14:12] $auto$wreduce.cc:461:run$6789 [5] $auto$wreduce.cc:461:run$6789 [3] $auto$wreduce.cc:461:run$6789 [1:0] } = 7'0001011
    Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3438:
      Old ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [10] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'10101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0010011 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0010011 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0]
      New ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [10] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'101010010011 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'111010010011 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [6:0] }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [6:0] }
      New connections: $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [9:7] = \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4977:
      Old ports: A=$flatten\Processor.\N1.\Third_Stage.$procmux$4974_Y, B={ \Processor.N1.Third_Stage.Second_Word [31:8] \Processor.N1.Third_Stage.First_Word [31:24] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4977_Y
      New ports: A=$flatten\Processor.\N1.\Third_Stage.$procmux$4974_Y [23:0], B={ \Processor.N1.Third_Stage.Second_Word [23:8] \Processor.N1.Third_Stage.First_Word [31:24] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4977_Y [23:0]
      New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4977_Y [31:24] = \Processor.N1.Third_Stage.Second_Word [31:24]
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4986:
      Old ports: A=$flatten\Processor.\N1.\Third_Stage.$procmux$4983_Y, B={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [23:0] \Processor.N1.Third_Stage.First_Word [7:0] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4986_Y
      New ports: A={ $flatten\Processor.\N1.\Third_Stage.$procmux$4983_Y [31:16] \Processor.N1.Third_Stage.First_Word [15:8] }, B=\Processor.N1.Third_Stage.EXMEM_mem_data_value [23:0], Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4986_Y [31:8]
      New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4986_Y [7:0] = \Processor.N1.Third_Stage.First_Word [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2922:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2916_Y, Y=$flatten\ResetBootSystem.$procmux$2922_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2916_Y [1], Y=$flatten\ResetBootSystem.$procmux$2922_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2922_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3333:
      Old ports: A=$auto$wreduce.cc:461:run$6792 [24:0], B=$auto$wreduce.cc:461:run$6789 [24:0], Y=$auto$wreduce.cc:461:run$6791 [24:0]
      New ports: A={ $auto$wreduce.cc:461:run$6792 [24:15] $auto$wreduce.cc:461:run$6792 [11:7] $auto$wreduce.cc:461:run$6792 [2] $auto$wreduce.cc:461:run$6792 [4] $auto$wreduce.cc:461:run$6792 [2] }, B={ $auto$wreduce.cc:461:run$6789 [24:15] $auto$wreduce.cc:461:run$6789 [11:6] $auto$wreduce.cc:461:run$6789 [4] $auto$wreduce.cc:461:run$6789 [2] }, Y={ $auto$wreduce.cc:461:run$6791 [24:15] $auto$wreduce.cc:461:run$6791 [11:6] $auto$wreduce.cc:461:run$6791 [4] $auto$wreduce.cc:461:run$6791 [2] }
      New connections: { $auto$wreduce.cc:461:run$6791 [14:12] $auto$wreduce.cc:461:run$6791 [5] $auto$wreduce.cc:461:run$6791 [3] $auto$wreduce.cc:461:run$6791 [1:0] } = 7'0001011
  Optimizing cells in module \processorci_top.
Performed a total of 42 changes.

34.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

34.30.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\Processor.N1.RegisterBank.registers$rdreg[0] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$7078, Q = $\Processor.N1.RegisterBank.registers$rdreg[0]$q, rval = 5'00000).
Adding SRST signal on $\Processor.N1.RegisterBank.registers$rdreg[1] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$7083, Q = $\Processor.N1.RegisterBank.registers$rdreg[1]$q, rval = 5'00000).
Setting constant 0-bit at position 0 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 1 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 2 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 3 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 4 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 5 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 6 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 7 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 8 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 9 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 10 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 11 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 12 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 13 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 14 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 15 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 16 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 17 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 18 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 19 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 20 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 21 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 22 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 23 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 24 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 25 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 26 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 27 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 28 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 29 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 30 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.
Setting constant 0-bit at position 31 on $memory\Processor.N1.RegisterBank.registers[0]$9608 ($dff) from module processorci_top.

34.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 4 unused cells and 185 unused wires.
<suppressed ~5 debug messages>

34.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

34.30.9. Rerunning OPT passes. (Maybe there is more to do..)

34.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~171 debug messages>

34.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[9]$9626 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[9]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[8]$9624 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[8]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[7]$9622 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[7]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[6]$9620 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[6]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[5]$9618 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[5]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[4]$9616 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[4]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[3]$9614 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[3]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[31]$9670 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[31]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[30]$9668 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[30]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[2]$9612 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[2]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[29]$9666 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[29]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[28]$9664 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[28]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[27]$9662 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[27]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[26]$9660 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[26]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[25]$9658 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[25]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[24]$9656 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[24]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[23]$9654 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[23]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[22]$9652 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[22]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[21]$9650 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[21]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[20]$9648 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[20]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[1]$9610 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[1]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[19]$9646 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[19]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[18]$9644 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[18]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[17]$9642 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[17]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[16]$9640 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[16]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[15]$9638 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[15]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[14]$9636 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[14]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[13]$9634 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[13]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[12]$9632 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[12]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[11]$9630 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[11]).
Adding EN signal on $memory\Processor.N1.RegisterBank.registers[10]$9628 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[10]).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6484 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6528 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6556 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6658 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6658 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6658 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6685 ($dffe) from module processorci_top.

34.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 31 unused cells and 31 unused wires.
<suppressed ~32 debug messages>

34.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

34.30.16. Rerunning OPT passes. (Maybe there is more to do..)

34.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>

34.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1985:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1985_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1985_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1985_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1963:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$6764 [0] 6'000000 $auto$wreduce.cc:461:run$6757 [1:0] 1'0 $auto$wreduce.cc:461:run$6762 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$6761 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$6760 [6] 1'0 $auto$wreduce.cc:461:run$6760 [6] 3'011 $auto$wreduce.cc:461:run$6760 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$6756 [3] 2'00 $auto$wreduce.cc:461:run$6756 [3] 6'000010 $auto$wreduce.cc:461:run$6757 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$6756 [3] $auto$wreduce.cc:461:run$6756 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1985_Y 1'0 $auto$wreduce.cc:461:run$6755 [6] 3'010 $auto$wreduce.cc:461:run$6755 [2] $auto$wreduce.cc:461:run$6755 [6] $auto$wreduce.cc:461:run$6755 [2] 13'0001001100010 $auto$wreduce.cc:461:run$6754 [2:1] $auto$wreduce.cc:461:run$6754 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$6753 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1963_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$6764 [0] 5'00000 $auto$wreduce.cc:461:run$6757 [1:0] $auto$wreduce.cc:461:run$6762 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$6761 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$6760 [6] 1'0 $auto$wreduce.cc:461:run$6760 [6] 3'011 $auto$wreduce.cc:461:run$6760 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$6756 [3] 2'00 $auto$wreduce.cc:461:run$6756 [3] 5'00010 $auto$wreduce.cc:461:run$6757 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$6756 [3] $auto$wreduce.cc:461:run$6756 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1985_Y [4:0] $auto$wreduce.cc:461:run$6755 [6] 3'010 $auto$wreduce.cc:461:run$6755 [2] $auto$wreduce.cc:461:run$6755 [6] $auto$wreduce.cc:461:run$6755 [2] 11'00100110010 $auto$wreduce.cc:461:run$6754 [2:1] $auto$wreduce.cc:461:run$6754 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$6753 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1963_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1963_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

34.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.30.20. Executing OPT_DFF pass (perform DFF optimizations).

34.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.30.23. Rerunning OPT passes. (Maybe there is more to do..)

34.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>

34.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6722 ($sdff) from module processorci_top.

34.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

34.30.30. Rerunning OPT passes. (Maybe there is more to do..)

34.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>

34.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.30.34. Executing OPT_DFF pass (perform DFF optimizations).

34.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.30.37. Finished OPT passes. (There is nothing left to do.)

34.31. Executing TECHMAP pass (map to technology primitives).

34.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

34.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

34.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $lut.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $or.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$e9679b690548ba55b1f1b57f80da909b90290ccf\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:de64642e95807af510ec2f372d99917387e547b5$paramod$2cd5a0fc12c713b111b124c014c3805512a5d620\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:51fb3526f3621c6ba109a6fa670766d42e57f474$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:02e205211af79b2de8410595a9b352a9c0a22e28$paramod$8a857a6eaa058823edfcd7a5ef47a9d072c90c39\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:7d50daff0345024d4d0c5d6b0021827b46f8ee12$paramod$46fb6c6807392d1f812af275dc46f0337caa65d5\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$40ec39fdbb40e313957832362e47914160e3dfcb\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:d44722790a942a23012b84b456a3acf7a7153600$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx for cells of type $shift.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Analyzing pattern of constant bits for this cell:
Creating constmapped module `$paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx'.

34.31.94. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $procmux$22633.
    dead port 2/2 on $mux $procmux$22627.
    dead port 2/2 on $mux $procmux$22621.
    dead port 2/2 on $mux $procmux$22615.
    dead port 2/2 on $mux $procmux$22609.
    dead port 2/2 on $mux $procmux$22603.
    dead port 2/2 on $mux $procmux$22597.
    dead port 2/2 on $mux $procmux$22591.
    dead port 2/2 on $mux $procmux$22585.
    dead port 2/2 on $mux $procmux$22579.
    dead port 2/2 on $mux $procmux$22573.
Removed 11 multiplexer ports.
<suppressed ~2493 debug messages>

34.31.95. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx.
<suppressed ~23 debug messages>
Removed 0 unused cells and 16 unused wires.
Using template $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx for cells of type $shift.
Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux.
Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux.
Using template $paramod$a75cda08a00cd2ec286ea508f3ad43ec36b77618\_90_pmux for cells of type $pmux.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$3aec434ea322cab681ad20f744a80c5503010ba7\_90_pmux for cells of type $pmux.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$e765c459d3029c22a22a27989e94858fd9ebfa9c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$788c3d57e5abb3a3f89aea6d4acd665be37f4e9b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$b6b58933bcf3c8b9e3e5de18c2637bd0e12c7c47\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~7597 debug messages>

34.32. Executing OPT pass (performing simple optimizations).

34.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~221052 debug messages>

34.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6918 debug messages>
Removed a total of 2306 cells.

34.32.3. Executing OPT_DFF pass (perform DFF optimizations).

34.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 32971 unused cells and 9427 unused wires.
<suppressed ~32977 debug messages>

34.32.5. Finished fast OPT passes.

34.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

34.35. Executing TECHMAP pass (map to technology primitives).

34.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

34.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
No more expansions possible.
<suppressed ~4413 debug messages>

34.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~99 debug messages>

34.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

34.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

34.39. Executing ATTRMVCP pass (move or copy attributes).

34.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 23364 unused wires.
<suppressed ~1 debug messages>

34.41. Executing TECHMAP pass (map to technology primitives).

34.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

34.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

34.42. Executing ABC9 pass.

34.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.3. Executing PROC pass (convert processes to netlists).

34.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330873'.
Cleaned up 1 empty switch.

34.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

34.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

34.42.3.4. Executing PROC_INIT pass (extract init attributes).

34.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

34.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

34.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874'.
     1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_EN[3:0]$330880
     2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_DATA[3:0]$330879
     3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_ADDR[3:0]$330878
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330873'.

34.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

34.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330871_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330865_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330859_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330856_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330860_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330861_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330862_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330866_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330867_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330857_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330868_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330858_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330863_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330864_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330869_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330870_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874'.
  created $dff cell `$procdff$330924' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874'.
  created $dff cell `$procdff$330925' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330872_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874'.
  created $dff cell `$procdff$330926' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330873'.
  created direct connection (no actual register cell created).

34.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

34.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330898'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330874'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330873'.
Cleaned up 1 empty switch.

34.42.3.12. Executing OPT_EXPR pass (perform const folding).

34.42.4. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$21313 $auto$simplemap.cc:225:simplemap_logbin$22044 $auto$simplemap.cc:225:simplemap_logbin$22046 $auto$ff.cc:266:slice$22246 $auto$simplemap.cc:126:simplemap_reduce$21315 $auto$simplemap.cc:225:simplemap_logbin$22050 $auto$simplemap.cc:225:simplemap_logbin$22048 $auto$simplemap.cc:225:simplemap_logbin$22047
Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$38921 $auto$simplemap.cc:75:simplemap_bitop$40015 $auto$ff.cc:266:slice$42116 $auto$simplemap.cc:75:simplemap_bitop$40014 $auto$ff.cc:266:slice$42115 $auto$simplemap.cc:126:simplemap_reduce$40020 $auto$simplemap.cc:75:simplemap_bitop$40013 $auto$simplemap.cc:126:simplemap_reduce$45702 $auto$ff.cc:266:slice$42114 $auto$simplemap.cc:75:simplemap_bitop$40012 $auto$ff.cc:266:slice$42113 $auto$simplemap.cc:196:simplemap_lognot$40026 $auto$simplemap.cc:126:simplemap_reduce$40024 $auto$simplemap.cc:126:simplemap_reduce$40022 $auto$simplemap.cc:126:simplemap_reduce$40019 $auto$simplemap.cc:75:simplemap_bitop$40011 $auto$opt_expr.cc:617:replace_const_cells$324741 $auto$simplemap.cc:225:simplemap_logbin$40034 $auto$simplemap.cc:126:simplemap_reduce$40033 $auto$simplemap.cc:126:simplemap_reduce$45708 $auto$simplemap.cc:126:simplemap_reduce$45701 $auto$ff.cc:266:slice$42112 $auto$simplemap.cc:75:simplemap_bitop$42721 $auto$ff.cc:266:slice$42111 $auto$simplemap.cc:75:simplemap_bitop$42720 $auto$ff.cc:266:slice$42110 $auto$simplemap.cc:126:simplemap_reduce$39984 $auto$simplemap.cc:126:simplemap_reduce$42726 $auto$simplemap.cc:75:simplemap_bitop$42719 $auto$ff.cc:266:slice$42109 $auto$simplemap.cc:75:simplemap_bitop$42718 $auto$ff.cc:266:slice$42108 $auto$simplemap.cc:126:simplemap_reduce$39988 $auto$simplemap.cc:126:simplemap_reduce$39986 $auto$simplemap.cc:126:simplemap_reduce$39983 $auto$opt_expr.cc:617:replace_const_cells$324687 $auto$simplemap.cc:225:simplemap_logbin$39989 $auto$simplemap.cc:196:simplemap_lognot$42732 $auto$simplemap.cc:126:simplemap_reduce$42730 $auto$simplemap.cc:126:simplemap_reduce$42728 $auto$simplemap.cc:126:simplemap_reduce$42725 $auto$simplemap.cc:75:simplemap_bitop$42717 $auto$ff.cc:266:slice$42107 $auto$opt_expr.cc:617:replace_const_cells$324727 $auto$ff.cc:266:slice$42098 $auto$opt_expr.cc:617:replace_const_cells$324729 $auto$ff.cc:266:slice$42097 $auto$simplemap.cc:126:simplemap_reduce$42428 $auto$simplemap.cc:126:simplemap_reduce$42425 $auto$simplemap.cc:126:simplemap_reduce$42450 $auto$simplemap.cc:126:simplemap_reduce$42447 $auto$opt_expr.cc:617:replace_const_cells$324719 $auto$simplemap.cc:126:simplemap_reduce$42560 $auto$simplemap.cc:126:simplemap_reduce$42557 $auto$simplemap.cc:126:simplemap_reduce$42406 $auto$simplemap.cc:126:simplemap_reduce$42689 $auto$simplemap.cc:126:simplemap_reduce$42686 $auto$ff.cc:266:slice$42096 $auto$opt_expr.cc:617:replace_const_cells$324707 $auto$ff.cc:266:slice$42095 $auto$simplemap.cc:126:simplemap_reduce$42556 $auto$simplemap.cc:126:simplemap_reduce$42351 $auto$simplemap.cc:126:simplemap_reduce$42685 $auto$opt_expr.cc:617:replace_const_cells$324725 $auto$ff.cc:266:slice$42094 $auto$opt_expr.cc:617:replace_const_cells$324723 $auto$ff.cc:266:slice$42093 $auto$ff.cc:266:slice$42091 $auto$ff.cc:266:slice$42090 $auto$ff.cc:266:slice$42089 $auto$ff.cc:266:slice$42088 $auto$ff.cc:266:slice$42087 $auto$ff.cc:266:slice$42086 $auto$ff.cc:266:slice$42085 $auto$ff.cc:266:slice$42084 $auto$ff.cc:266:slice$42083 $auto$ff.cc:266:slice$42082 $auto$ff.cc:266:slice$42081 $auto$ff.cc:266:slice$42080 $auto$ff.cc:266:slice$42079 $auto$ff.cc:266:slice$42078 $auto$ff.cc:266:slice$42077 $auto$ff.cc:266:slice$42076 $auto$ff.cc:266:slice$42075 $auto$ff.cc:266:slice$42074 $auto$ff.cc:266:slice$42073 $auto$ff.cc:266:slice$42072 $auto$ff.cc:266:slice$42071 $auto$ff.cc:266:slice$42070 $auto$ff.cc:266:slice$42069 $auto$ff.cc:266:slice$42068 $auto$ff.cc:266:slice$42067 $auto$ff.cc:266:slice$42066 $auto$ff.cc:266:slice$42065 $auto$ff.cc:266:slice$42064 $auto$ff.cc:266:slice$42063 $auto$ff.cc:266:slice$42062 $auto$ff.cc:266:slice$42061 $auto$simplemap.cc:196:simplemap_lognot$42359 $auto$simplemap.cc:126:simplemap_reduce$42357 $auto$simplemap.cc:126:simplemap_reduce$42354 $auto$simplemap.cc:196:simplemap_lognot$42388 $auto$simplemap.cc:126:simplemap_reduce$42386 $auto$simplemap.cc:126:simplemap_reduce$42362 $auto$simplemap.cc:196:simplemap_lognot$42410 $auto$simplemap.cc:126:simplemap_reduce$42408 $auto$simplemap.cc:196:simplemap_lognot$42564 $auto$simplemap.cc:126:simplemap_reduce$42562 $auto$simplemap.cc:126:simplemap_reduce$42559 $auto$simplemap.cc:196:simplemap_lognot$42432 $auto$simplemap.cc:126:simplemap_reduce$42430 $auto$simplemap.cc:126:simplemap_reduce$42333 $auto$simplemap.cc:75:simplemap_bitop$190934 $auto$simplemap.cc:75:simplemap_bitop$190935 $auto$simplemap.cc:75:simplemap_bitop$190936 $auto$simplemap.cc:75:simplemap_bitop$190937 $auto$simplemap.cc:75:simplemap_bitop$190938 $auto$simplemap.cc:75:simplemap_bitop$190939 $auto$simplemap.cc:75:simplemap_bitop$190940 $auto$simplemap.cc:75:simplemap_bitop$190941 $auto$simplemap.cc:75:simplemap_bitop$190942 $auto$simplemap.cc:75:simplemap_bitop$190943 $auto$simplemap.cc:75:simplemap_bitop$190944 $auto$simplemap.cc:75:simplemap_bitop$190945 $auto$simplemap.cc:75:simplemap_bitop$190946 $auto$simplemap.cc:75:simplemap_bitop$190947 $auto$simplemap.cc:75:simplemap_bitop$190948 $auto$simplemap.cc:75:simplemap_bitop$190949 $auto$simplemap.cc:75:simplemap_bitop$190950 $auto$simplemap.cc:75:simplemap_bitop$190951 $auto$simplemap.cc:75:simplemap_bitop$190952 $auto$simplemap.cc:75:simplemap_bitop$190953 $auto$simplemap.cc:75:simplemap_bitop$190954 $auto$simplemap.cc:75:simplemap_bitop$190955 $auto$simplemap.cc:75:simplemap_bitop$190956 $auto$simplemap.cc:75:simplemap_bitop$190957 $auto$simplemap.cc:75:simplemap_bitop$190958 $auto$simplemap.cc:75:simplemap_bitop$190959 $auto$simplemap.cc:75:simplemap_bitop$190960 $auto$simplemap.cc:75:simplemap_bitop$190961 $auto$simplemap.cc:75:simplemap_bitop$190962 $auto$simplemap.cc:75:simplemap_bitop$190963 $auto$simplemap.cc:75:simplemap_bitop$190964 $auto$simplemap.cc:75:simplemap_bitop$190965 $auto$simplemap.cc:126:simplemap_reduce$42366 $auto$simplemap.cc:126:simplemap_reduce$42364 $auto$simplemap.cc:126:simplemap_reduce$42361 $auto$simplemap.cc:196:simplemap_lognot$42454 $auto$simplemap.cc:126:simplemap_reduce$42452 $auto$simplemap.cc:75:simplemap_bitop$190545 $auto$simplemap.cc:75:simplemap_bitop$190546 $auto$simplemap.cc:75:simplemap_bitop$190547 $auto$simplemap.cc:75:simplemap_bitop$190548 $auto$simplemap.cc:75:simplemap_bitop$190549 $auto$simplemap.cc:75:simplemap_bitop$190550 $auto$simplemap.cc:75:simplemap_bitop$190551 $auto$simplemap.cc:75:simplemap_bitop$190552 $auto$simplemap.cc:75:simplemap_bitop$190553 $auto$simplemap.cc:75:simplemap_bitop$190554 $auto$simplemap.cc:75:simplemap_bitop$190555 $auto$simplemap.cc:75:simplemap_bitop$190556 $auto$simplemap.cc:75:simplemap_bitop$190557 $auto$simplemap.cc:75:simplemap_bitop$190558 $auto$simplemap.cc:75:simplemap_bitop$190559 $auto$simplemap.cc:75:simplemap_bitop$190560 $auto$simplemap.cc:75:simplemap_bitop$190561 $auto$simplemap.cc:75:simplemap_bitop$190562 $auto$simplemap.cc:75:simplemap_bitop$190563 $auto$simplemap.cc:75:simplemap_bitop$190564 $auto$simplemap.cc:75:simplemap_bitop$190565 $auto$simplemap.cc:75:simplemap_bitop$190566 $auto$simplemap.cc:75:simplemap_bitop$190567 $auto$simplemap.cc:75:simplemap_bitop$190568 $auto$simplemap.cc:75:simplemap_bitop$190569 $auto$simplemap.cc:75:simplemap_bitop$190570 $auto$simplemap.cc:75:simplemap_bitop$190571 $auto$simplemap.cc:75:simplemap_bitop$190572 $auto$simplemap.cc:75:simplemap_bitop$190573 $auto$simplemap.cc:75:simplemap_bitop$190574 $auto$simplemap.cc:75:simplemap_bitop$190575 $auto$simplemap.cc:126:simplemap_reduce$190641 $auto$simplemap.cc:126:simplemap_reduce$42335 $auto$simplemap.cc:126:simplemap_reduce$191001 $auto$simplemap.cc:75:simplemap_bitop$190967 $auto$simplemap.cc:126:simplemap_reduce$191003 $auto$simplemap.cc:75:simplemap_bitop$190968 $auto$simplemap.cc:126:simplemap_reduce$191063 $auto$simplemap.cc:126:simplemap_reduce$42337 $auto$simplemap.cc:196:simplemap_lognot$42693 $auto$simplemap.cc:126:simplemap_reduce$42691 $auto$simplemap.cc:126:simplemap_reduce$42688 $auto$simplemap.cc:126:simplemap_reduce$42684 $auto$opt_expr.cc:617:replace_const_cells$324721 $auto$ff.cc:266:slice$42092 $auto$simplemap.cc:75:simplemap_bitop$190544 $auto$ff.cc:266:slice$42060 $auto$simplemap.cc:225:simplemap_logbin$42772 $auto$ff.cc:266:slice$42059 $auto$simplemap.cc:75:simplemap_bitop$190284 $auto$simplemap.cc:75:simplemap_bitop$190285 $auto$simplemap.cc:75:simplemap_bitop$190286 $auto$simplemap.cc:75:simplemap_bitop$190287 $auto$simplemap.cc:75:simplemap_bitop$190288 $auto$simplemap.cc:75:simplemap_bitop$190289 $auto$simplemap.cc:75:simplemap_bitop$190290 $auto$simplemap.cc:75:simplemap_bitop$190291 $auto$simplemap.cc:75:simplemap_bitop$190292 $auto$simplemap.cc:75:simplemap_bitop$190293 $auto$simplemap.cc:75:simplemap_bitop$190294 $auto$simplemap.cc:75:simplemap_bitop$190295 $auto$simplemap.cc:75:simplemap_bitop$190296 $auto$simplemap.cc:75:simplemap_bitop$190297 $auto$simplemap.cc:75:simplemap_bitop$190298 $auto$simplemap.cc:75:simplemap_bitop$190299 $auto$simplemap.cc:75:simplemap_bitop$190300 $auto$simplemap.cc:75:simplemap_bitop$190301 $auto$simplemap.cc:75:simplemap_bitop$190302 $auto$simplemap.cc:75:simplemap_bitop$190303 $auto$simplemap.cc:75:simplemap_bitop$190304 $auto$simplemap.cc:75:simplemap_bitop$190305 $auto$simplemap.cc:75:simplemap_bitop$190306 $auto$simplemap.cc:75:simplemap_bitop$190307 $auto$simplemap.cc:75:simplemap_bitop$190308 $auto$simplemap.cc:75:simplemap_bitop$190309 $auto$simplemap.cc:75:simplemap_bitop$190310 $auto$simplemap.cc:75:simplemap_bitop$190311 $auto$simplemap.cc:75:simplemap_bitop$190312 $auto$simplemap.cc:75:simplemap_bitop$190313 $auto$simplemap.cc:75:simplemap_bitop$190314 $auto$simplemap.cc:75:simplemap_bitop$190315 $auto$simplemap.cc:196:simplemap_lognot$39971 $auto$simplemap.cc:126:simplemap_reduce$39969 $auto$simplemap.cc:196:simplemap_lognot$39981 $auto$simplemap.cc:126:simplemap_reduce$39979 $auto$simplemap.cc:126:simplemap_reduce$190479 $auto$simplemap.cc:126:simplemap_reduce$190477 $auto$simplemap.cc:196:simplemap_lognot$42714 $auto$simplemap.cc:126:simplemap_reduce$42712 $auto$opt_expr.cc:617:replace_const_cells$324685 $auto$simplemap.cc:225:simplemap_logbin$42573 $auto$simplemap.cc:225:simplemap_logbin$42575 $auto$simplemap.cc:196:simplemap_lognot$38619 $auto$opt_expr.cc:617:replace_const_cells$325433 $auto$simplemap.cc:75:simplemap_bitop$39996 $auto$simplemap.cc:75:simplemap_bitop$40041 $auto$ff.cc:266:slice$42058 $auto$simplemap.cc:75:simplemap_bitop$39995 $auto$simplemap.cc:75:simplemap_bitop$40040 $auto$ff.cc:266:slice$42057 $auto$simplemap.cc:126:simplemap_reduce$40001 $auto$simplemap.cc:75:simplemap_bitop$39994 $auto$simplemap.cc:126:simplemap_reduce$40046 $auto$simplemap.cc:75:simplemap_bitop$40039 $auto$ff.cc:266:slice$42056 $auto$simplemap.cc:75:simplemap_bitop$39993 $auto$simplemap.cc:75:simplemap_bitop$40038 $auto$ff.cc:266:slice$42055 $auto$simplemap.cc:225:simplemap_logbin$40008 $auto$simplemap.cc:196:simplemap_lognot$40007 $auto$simplemap.cc:126:simplemap_reduce$40005 $auto$simplemap.cc:126:simplemap_reduce$40003 $auto$simplemap.cc:126:simplemap_reduce$40000 $auto$simplemap.cc:75:simplemap_bitop$39992 $auto$simplemap.cc:75:simplemap_bitop$190706 $auto$simplemap.cc:75:simplemap_bitop$190707 $auto$simplemap.cc:75:simplemap_bitop$190708 $auto$simplemap.cc:75:simplemap_bitop$190709 $auto$simplemap.cc:75:simplemap_bitop$190710 $auto$simplemap.cc:75:simplemap_bitop$190711 $auto$simplemap.cc:75:simplemap_bitop$190712 $auto$simplemap.cc:75:simplemap_bitop$190713 $auto$simplemap.cc:75:simplemap_bitop$190714 $auto$simplemap.cc:75:simplemap_bitop$190715 $auto$simplemap.cc:75:simplemap_bitop$190716 $auto$simplemap.cc:75:simplemap_bitop$190717 $auto$simplemap.cc:75:simplemap_bitop$190718 $auto$simplemap.cc:75:simplemap_bitop$190719 $auto$simplemap.cc:75:simplemap_bitop$190720 $auto$simplemap.cc:75:simplemap_bitop$190721 $auto$simplemap.cc:75:simplemap_bitop$190722 $auto$simplemap.cc:75:simplemap_bitop$190723 $auto$simplemap.cc:75:simplemap_bitop$190724 $auto$simplemap.cc:75:simplemap_bitop$190725 $auto$simplemap.cc:75:simplemap_bitop$190726 $auto$simplemap.cc:75:simplemap_bitop$190727 $auto$simplemap.cc:75:simplemap_bitop$190728 $auto$simplemap.cc:75:simplemap_bitop$190729 $auto$simplemap.cc:75:simplemap_bitop$190730 $auto$simplemap.cc:75:simplemap_bitop$190731 $auto$simplemap.cc:75:simplemap_bitop$190732 $auto$simplemap.cc:75:simplemap_bitop$190733 $auto$simplemap.cc:75:simplemap_bitop$190734 $auto$simplemap.cc:75:simplemap_bitop$190735 $auto$simplemap.cc:75:simplemap_bitop$190736 $auto$simplemap.cc:75:simplemap_bitop$190737 $auto$simplemap.cc:196:simplemap_lognot$39951 $auto$simplemap.cc:126:simplemap_reduce$39949 $auto$simplemap.cc:196:simplemap_lognot$39961 $auto$simplemap.cc:126:simplemap_reduce$39959 $auto$simplemap.cc:126:simplemap_reduce$190901 $auto$simplemap.cc:126:simplemap_reduce$190899 $auto$simplemap.cc:196:simplemap_lognot$42704 $auto$simplemap.cc:126:simplemap_reduce$42702 $auto$opt_expr.cc:617:replace_const_cells$324739 $auto$simplemap.cc:225:simplemap_logbin$42775 $auto$simplemap.cc:126:simplemap_reduce$42777 $auto$simplemap.cc:267:simplemap_mux$40056 $auto$simplemap.cc:225:simplemap_logbin$40053 $auto$simplemap.cc:196:simplemap_lognot$40052 $auto$simplemap.cc:126:simplemap_reduce$40050 $auto$simplemap.cc:126:simplemap_reduce$40048 $auto$simplemap.cc:126:simplemap_reduce$40045 $auto$simplemap.cc:75:simplemap_bitop$40037 $auto$ff.cc:266:slice$42054 $auto$simplemap.cc:38:simplemap_not$315781 $auto$simplemap.cc:75:simplemap_bitop$316709 $auto$simplemap.cc:267:simplemap_mux$190673 $auto$simplemap.cc:267:simplemap_mux$190511 $auto$simplemap.cc:126:simplemap_reduce$190475 $auto$simplemap.cc:75:simplemap_bitop$190347 $auto$simplemap.cc:75:simplemap_bitop$316357 $auto$simplemap.cc:75:simplemap_bitop$40104 $auto$simplemap.cc:75:simplemap_bitop$316517 $auto$simplemap.cc:38:simplemap_not$40200 $auto$simplemap.cc:126:simplemap_reduce$315852 $auto$simplemap.cc:75:simplemap_bitop$316389 $auto$simplemap.cc:75:simplemap_bitop$40136 $auto$simplemap.cc:75:simplemap_bitop$191255 $auto$simplemap.cc:126:simplemap_reduce$315850 $auto$simplemap.cc:75:simplemap_bitop$316485 $auto$simplemap.cc:75:simplemap_bitop$315845 $auto$simplemap.cc:267:simplemap_mux$191095 $auto$simplemap.cc:267:simplemap_mux$190933 $auto$simplemap.cc:126:simplemap_reduce$190897 $auto$simplemap.cc:75:simplemap_bitop$190769 $auto$simplemap.cc:267:simplemap_mux$22292 $auto$simplemap.cc:38:simplemap_not$191190 $auto$simplemap.cc:267:simplemap_mux$190672 $auto$simplemap.cc:267:simplemap_mux$190510 $auto$simplemap.cc:126:simplemap_reduce$190471 $auto$simplemap.cc:75:simplemap_bitop$190346 $auto$simplemap.cc:75:simplemap_bitop$316356 $auto$simplemap.cc:225:simplemap_logbin$315716 $auto$simplemap.cc:75:simplemap_bitop$316516 $auto$simplemap.cc:38:simplemap_not$40199 $auto$simplemap.cc:126:simplemap_reduce$315867 $auto$simplemap.cc:75:simplemap_bitop$316388 $auto$simplemap.cc:225:simplemap_logbin$315748 $auto$simplemap.cc:126:simplemap_reduce$16070 $auto$simplemap.cc:75:simplemap_bitop$191254 $auto$simplemap.cc:126:simplemap_reduce$315865 $auto$simplemap.cc:75:simplemap_bitop$316484 $auto$simplemap.cc:75:simplemap_bitop$315844 $auto$simplemap.cc:267:simplemap_mux$191094 $auto$simplemap.cc:267:simplemap_mux$190932 $auto$simplemap.cc:126:simplemap_reduce$190893 $auto$simplemap.cc:75:simplemap_bitop$190768 $auto$simplemap.cc:267:simplemap_mux$22291 $auto$simplemap.cc:38:simplemap_not$191189 $auto$simplemap.cc:267:simplemap_mux$190671 $auto$simplemap.cc:267:simplemap_mux$190509 $auto$simplemap.cc:126:simplemap_reduce$190467 $auto$simplemap.cc:75:simplemap_bitop$190345 $auto$simplemap.cc:75:simplemap_bitop$316355 $auto$simplemap.cc:75:simplemap_bitop$40102 $auto$simplemap.cc:75:simplemap_bitop$316515 $auto$simplemap.cc:38:simplemap_not$40198 $auto$simplemap.cc:126:simplemap_reduce$315882 $auto$simplemap.cc:75:simplemap_bitop$316387 $auto$simplemap.cc:75:simplemap_bitop$40134 $auto$simplemap.cc:75:simplemap_bitop$191253 $auto$simplemap.cc:126:simplemap_reduce$315880 $auto$simplemap.cc:75:simplemap_bitop$316483 $auto$simplemap.cc:75:simplemap_bitop$315843 $auto$simplemap.cc:267:simplemap_mux$191093 $auto$simplemap.cc:267:simplemap_mux$190931 $auto$simplemap.cc:126:simplemap_reduce$190889 $auto$simplemap.cc:75:simplemap_bitop$190767 $auto$simplemap.cc:267:simplemap_mux$22290 $auto$simplemap.cc:38:simplemap_not$191188 $auto$simplemap.cc:267:simplemap_mux$190670 $auto$simplemap.cc:267:simplemap_mux$190508 $auto$simplemap.cc:126:simplemap_reduce$190463 $auto$simplemap.cc:75:simplemap_bitop$190344 $auto$simplemap.cc:75:simplemap_bitop$316354 $auto$simplemap.cc:225:simplemap_logbin$315714 $auto$simplemap.cc:75:simplemap_bitop$316514 $auto$simplemap.cc:38:simplemap_not$40197 $auto$simplemap.cc:126:simplemap_reduce$315897 $auto$simplemap.cc:75:simplemap_bitop$316386 $auto$simplemap.cc:225:simplemap_logbin$315746 $auto$simplemap.cc:126:simplemap_reduce$16079 $auto$simplemap.cc:126:simplemap_reduce$16069 $auto$simplemap.cc:75:simplemap_bitop$191252 $auto$simplemap.cc:126:simplemap_reduce$315895 $auto$simplemap.cc:75:simplemap_bitop$316482 $auto$simplemap.cc:75:simplemap_bitop$315842 $auto$simplemap.cc:267:simplemap_mux$191092 $auto$simplemap.cc:267:simplemap_mux$190930 $auto$simplemap.cc:126:simplemap_reduce$190885 $auto$simplemap.cc:75:simplemap_bitop$190766 $auto$simplemap.cc:267:simplemap_mux$22289 $auto$simplemap.cc:38:simplemap_not$191187 $auto$simplemap.cc:267:simplemap_mux$190669 $auto$simplemap.cc:267:simplemap_mux$190507 $auto$simplemap.cc:126:simplemap_reduce$190459 $auto$simplemap.cc:75:simplemap_bitop$190343 $auto$simplemap.cc:75:simplemap_bitop$40100 $auto$simplemap.cc:75:simplemap_bitop$316513 $auto$simplemap.cc:38:simplemap_not$40196 $auto$simplemap.cc:75:simplemap_bitop$316385 $auto$simplemap.cc:75:simplemap_bitop$40132 $auto$simplemap.cc:75:simplemap_bitop$191251 $auto$simplemap.cc:126:simplemap_reduce$315910 $auto$simplemap.cc:75:simplemap_bitop$316481 $auto$simplemap.cc:75:simplemap_bitop$315841 $auto$simplemap.cc:267:simplemap_mux$191091 $auto$simplemap.cc:267:simplemap_mux$190929 $auto$simplemap.cc:126:simplemap_reduce$190881 $auto$simplemap.cc:75:simplemap_bitop$190765 $auto$simplemap.cc:267:simplemap_mux$22288 $auto$simplemap.cc:38:simplemap_not$191186 $auto$simplemap.cc:267:simplemap_mux$190668 $auto$simplemap.cc:267:simplemap_mux$190506 $auto$simplemap.cc:126:simplemap_reduce$190455 $auto$simplemap.cc:75:simplemap_bitop$190342 $auto$simplemap.cc:75:simplemap_bitop$316352 $auto$simplemap.cc:225:simplemap_logbin$315712 $auto$simplemap.cc:75:simplemap_bitop$316512 $auto$simplemap.cc:38:simplemap_not$40195 $auto$simplemap.cc:126:simplemap_reduce$315927 $auto$simplemap.cc:75:simplemap_bitop$316384 $auto$simplemap.cc:225:simplemap_logbin$315744 $auto$simplemap.cc:126:simplemap_reduce$16068 $auto$simplemap.cc:75:simplemap_bitop$191250 $auto$simplemap.cc:126:simplemap_reduce$315925 $auto$simplemap.cc:75:simplemap_bitop$316480 $auto$simplemap.cc:75:simplemap_bitop$315840 $auto$simplemap.cc:267:simplemap_mux$191090 $auto$simplemap.cc:267:simplemap_mux$190928 $auto$simplemap.cc:126:simplemap_reduce$190877 $auto$simplemap.cc:75:simplemap_bitop$190764 $auto$simplemap.cc:267:simplemap_mux$22287 $auto$simplemap.cc:38:simplemap_not$191185 $auto$simplemap.cc:267:simplemap_mux$190667 $auto$simplemap.cc:267:simplemap_mux$190505 $auto$simplemap.cc:126:simplemap_reduce$190451 $auto$simplemap.cc:75:simplemap_bitop$190341 $auto$simplemap.cc:75:simplemap_bitop$316351 $auto$simplemap.cc:75:simplemap_bitop$40098 $auto$simplemap.cc:75:simplemap_bitop$316511 $auto$simplemap.cc:38:simplemap_not$40194 $auto$simplemap.cc:126:simplemap_reduce$315942 $auto$simplemap.cc:75:simplemap_bitop$316383 $auto$simplemap.cc:75:simplemap_bitop$40130 $auto$simplemap.cc:126:simplemap_reduce$315940 $auto$simplemap.cc:75:simplemap_bitop$316479 $auto$simplemap.cc:75:simplemap_bitop$40162 $auto$simplemap.cc:75:simplemap_bitop$191249 $auto$simplemap.cc:267:simplemap_mux$191089 $auto$simplemap.cc:267:simplemap_mux$190927 $auto$simplemap.cc:126:simplemap_reduce$190873 $auto$simplemap.cc:75:simplemap_bitop$190763 $auto$simplemap.cc:267:simplemap_mux$22286 $auto$simplemap.cc:38:simplemap_not$191184 $auto$simplemap.cc:267:simplemap_mux$190666 $auto$simplemap.cc:267:simplemap_mux$190504 $auto$simplemap.cc:126:simplemap_reduce$190447 $auto$simplemap.cc:75:simplemap_bitop$190340 $auto$simplemap.cc:75:simplemap_bitop$316350 $auto$simplemap.cc:225:simplemap_logbin$315710 $auto$simplemap.cc:75:simplemap_bitop$316510 $auto$simplemap.cc:38:simplemap_not$40193 $auto$simplemap.cc:126:simplemap_reduce$315957 $auto$simplemap.cc:75:simplemap_bitop$316382 $auto$simplemap.cc:225:simplemap_logbin$315742 $auto$simplemap.cc:126:simplemap_reduce$16084 $auto$simplemap.cc:126:simplemap_reduce$16078 $auto$simplemap.cc:126:simplemap_reduce$16067 $auto$simplemap.cc:75:simplemap_bitop$191248 $auto$simplemap.cc:126:simplemap_reduce$315955 $auto$simplemap.cc:75:simplemap_bitop$316478 $auto$simplemap.cc:75:simplemap_bitop$315838 $auto$simplemap.cc:267:simplemap_mux$191088 $auto$simplemap.cc:267:simplemap_mux$190926 $auto$simplemap.cc:126:simplemap_reduce$190869 $auto$simplemap.cc:75:simplemap_bitop$190762 $auto$simplemap.cc:267:simplemap_mux$22285 $auto$simplemap.cc:38:simplemap_not$315773 $auto$simplemap.cc:267:simplemap_mux$190665 $auto$simplemap.cc:267:simplemap_mux$190503 $auto$simplemap.cc:126:simplemap_reduce$190443 $auto$simplemap.cc:75:simplemap_bitop$190339 $auto$simplemap.cc:75:simplemap_bitop$316349 $auto$simplemap.cc:75:simplemap_bitop$40096 $auto$simplemap.cc:75:simplemap_bitop$316509 $auto$simplemap.cc:38:simplemap_not$40192 $auto$simplemap.cc:126:simplemap_reduce$315972 $auto$simplemap.cc:75:simplemap_bitop$316381 $auto$simplemap.cc:75:simplemap_bitop$40128 $auto$simplemap.cc:75:simplemap_bitop$191247 $auto$simplemap.cc:126:simplemap_reduce$315970 $auto$simplemap.cc:75:simplemap_bitop$316477 $auto$simplemap.cc:75:simplemap_bitop$315837 $auto$simplemap.cc:267:simplemap_mux$191087 $auto$simplemap.cc:267:simplemap_mux$190925 $auto$simplemap.cc:126:simplemap_reduce$190865 $auto$simplemap.cc:75:simplemap_bitop$190761 $auto$simplemap.cc:267:simplemap_mux$22284 $auto$simplemap.cc:38:simplemap_not$315772 $auto$simplemap.cc:267:simplemap_mux$190664 $auto$simplemap.cc:267:simplemap_mux$190502 $auto$simplemap.cc:126:simplemap_reduce$190439 $auto$simplemap.cc:75:simplemap_bitop$190338 $auto$simplemap.cc:75:simplemap_bitop$316348 $auto$simplemap.cc:225:simplemap_logbin$315708 $auto$simplemap.cc:75:simplemap_bitop$316508 $auto$simplemap.cc:38:simplemap_not$40191 $auto$simplemap.cc:126:simplemap_reduce$315987 $auto$simplemap.cc:75:simplemap_bitop$316380 $auto$simplemap.cc:225:simplemap_logbin$315740 $auto$simplemap.cc:126:simplemap_reduce$16066 $auto$simplemap.cc:75:simplemap_bitop$191246 $auto$simplemap.cc:126:simplemap_reduce$315985 $auto$simplemap.cc:75:simplemap_bitop$316476 $auto$simplemap.cc:75:simplemap_bitop$315836 $auto$simplemap.cc:267:simplemap_mux$191086 $auto$simplemap.cc:267:simplemap_mux$190924 $auto$simplemap.cc:126:simplemap_reduce$190861 $auto$simplemap.cc:75:simplemap_bitop$190760 $auto$simplemap.cc:267:simplemap_mux$22283 $auto$simplemap.cc:38:simplemap_not$191181 $auto$simplemap.cc:267:simplemap_mux$190663 $auto$simplemap.cc:267:simplemap_mux$190501 $auto$simplemap.cc:126:simplemap_reduce$190435 $auto$simplemap.cc:75:simplemap_bitop$190337 $auto$simplemap.cc:75:simplemap_bitop$316347 $auto$simplemap.cc:75:simplemap_bitop$40094 $auto$simplemap.cc:75:simplemap_bitop$316507 $auto$simplemap.cc:38:simplemap_not$40190 $auto$simplemap.cc:126:simplemap_reduce$316002 $auto$simplemap.cc:75:simplemap_bitop$316379 $auto$simplemap.cc:75:simplemap_bitop$40126 $auto$simplemap.cc:75:simplemap_bitop$191245 $auto$simplemap.cc:126:simplemap_reduce$316000 $auto$simplemap.cc:75:simplemap_bitop$316475 $auto$simplemap.cc:75:simplemap_bitop$315835 $auto$simplemap.cc:267:simplemap_mux$191085 $auto$simplemap.cc:267:simplemap_mux$190923 $auto$simplemap.cc:126:simplemap_reduce$190857 $auto$simplemap.cc:75:simplemap_bitop$190759 $auto$simplemap.cc:267:simplemap_mux$22282 $auto$simplemap.cc:38:simplemap_not$191180 $auto$simplemap.cc:267:simplemap_mux$190662 $auto$simplemap.cc:267:simplemap_mux$190500 $auto$simplemap.cc:126:simplemap_reduce$190431 $auto$simplemap.cc:75:simplemap_bitop$190336 $auto$simplemap.cc:75:simplemap_bitop$316346 $auto$simplemap.cc:225:simplemap_logbin$315706 $auto$simplemap.cc:75:simplemap_bitop$316506 $auto$simplemap.cc:38:simplemap_not$40189 $auto$simplemap.cc:126:simplemap_reduce$316017 $auto$simplemap.cc:75:simplemap_bitop$316378 $auto$simplemap.cc:225:simplemap_logbin$315738 $auto$simplemap.cc:126:simplemap_reduce$16077 $auto$simplemap.cc:126:simplemap_reduce$16065 $auto$simplemap.cc:75:simplemap_bitop$191244 $auto$simplemap.cc:126:simplemap_reduce$316015 $auto$simplemap.cc:75:simplemap_bitop$316474 $auto$simplemap.cc:75:simplemap_bitop$315834 $auto$simplemap.cc:267:simplemap_mux$191084 $auto$simplemap.cc:267:simplemap_mux$190922 $auto$simplemap.cc:126:simplemap_reduce$190853 $auto$simplemap.cc:75:simplemap_bitop$190758 $auto$simplemap.cc:267:simplemap_mux$22281 $auto$simplemap.cc:38:simplemap_not$191179 $auto$simplemap.cc:267:simplemap_mux$190661 $auto$simplemap.cc:267:simplemap_mux$190499 $auto$simplemap.cc:126:simplemap_reduce$190427 $auto$simplemap.cc:75:simplemap_bitop$190335 $auto$simplemap.cc:75:simplemap_bitop$316345 $auto$simplemap.cc:75:simplemap_bitop$40092 $auto$simplemap.cc:75:simplemap_bitop$316505 $auto$simplemap.cc:38:simplemap_not$40188 $auto$simplemap.cc:126:simplemap_reduce$316032 $auto$simplemap.cc:75:simplemap_bitop$316377 $auto$simplemap.cc:75:simplemap_bitop$40124 $auto$simplemap.cc:75:simplemap_bitop$191243 $auto$simplemap.cc:126:simplemap_reduce$316030 $auto$simplemap.cc:75:simplemap_bitop$316473 $auto$simplemap.cc:75:simplemap_bitop$315833 $auto$simplemap.cc:267:simplemap_mux$191083 $auto$simplemap.cc:267:simplemap_mux$190921 $auto$simplemap.cc:126:simplemap_reduce$190849 $auto$simplemap.cc:75:simplemap_bitop$190757 $auto$simplemap.cc:267:simplemap_mux$22280 $auto$simplemap.cc:38:simplemap_not$315768 $auto$simplemap.cc:267:simplemap_mux$190660 $auto$simplemap.cc:267:simplemap_mux$190498 $auto$simplemap.cc:126:simplemap_reduce$190423 $auto$simplemap.cc:75:simplemap_bitop$190334 $auto$simplemap.cc:75:simplemap_bitop$316344 $auto$simplemap.cc:225:simplemap_logbin$315704 $auto$simplemap.cc:75:simplemap_bitop$316504 $auto$simplemap.cc:38:simplemap_not$40187 $auto$simplemap.cc:126:simplemap_reduce$316047 $auto$simplemap.cc:75:simplemap_bitop$316376 $auto$simplemap.cc:225:simplemap_logbin$315736 $auto$simplemap.cc:126:simplemap_reduce$16064 $auto$simplemap.cc:75:simplemap_bitop$191242 $auto$simplemap.cc:126:simplemap_reduce$316045 $auto$simplemap.cc:75:simplemap_bitop$316472 $auto$simplemap.cc:75:simplemap_bitop$315832 $auto$simplemap.cc:267:simplemap_mux$191082 $auto$simplemap.cc:267:simplemap_mux$190920 $auto$simplemap.cc:126:simplemap_reduce$190845 $auto$simplemap.cc:75:simplemap_bitop$190756 $auto$simplemap.cc:267:simplemap_mux$22279 $auto$simplemap.cc:38:simplemap_not$191177 $auto$simplemap.cc:267:simplemap_mux$190659 $auto$simplemap.cc:267:simplemap_mux$190497 $auto$simplemap.cc:126:simplemap_reduce$190419 $auto$simplemap.cc:75:simplemap_bitop$190333 $auto$simplemap.cc:75:simplemap_bitop$316343 $auto$simplemap.cc:75:simplemap_bitop$40090 $auto$simplemap.cc:75:simplemap_bitop$316503 $auto$simplemap.cc:38:simplemap_not$40186 $auto$simplemap.cc:126:simplemap_reduce$316062 $auto$simplemap.cc:75:simplemap_bitop$316375 $auto$simplemap.cc:75:simplemap_bitop$40122 $auto$simplemap.cc:75:simplemap_bitop$191241 $auto$simplemap.cc:126:simplemap_reduce$316060 $auto$simplemap.cc:75:simplemap_bitop$316471 $auto$simplemap.cc:75:simplemap_bitop$315831 $auto$simplemap.cc:267:simplemap_mux$191081 $auto$simplemap.cc:267:simplemap_mux$190919 $auto$simplemap.cc:126:simplemap_reduce$190841 $auto$simplemap.cc:75:simplemap_bitop$190755 $auto$simplemap.cc:267:simplemap_mux$22278 $auto$simplemap.cc:38:simplemap_not$315766 $auto$simplemap.cc:267:simplemap_mux$190658 $auto$simplemap.cc:267:simplemap_mux$190496 $auto$simplemap.cc:126:simplemap_reduce$190415 $auto$simplemap.cc:75:simplemap_bitop$190332 $auto$simplemap.cc:75:simplemap_bitop$316342 $auto$simplemap.cc:225:simplemap_logbin$315702 $auto$simplemap.cc:75:simplemap_bitop$316502 $auto$simplemap.cc:38:simplemap_not$40185 $auto$simplemap.cc:126:simplemap_reduce$316077 $auto$simplemap.cc:75:simplemap_bitop$316374 $auto$simplemap.cc:225:simplemap_logbin$315734 $auto$simplemap.cc:126:simplemap_reduce$16087 $auto$simplemap.cc:126:simplemap_reduce$16083 $auto$simplemap.cc:126:simplemap_reduce$16076 $auto$simplemap.cc:126:simplemap_reduce$16063 $auto$simplemap.cc:75:simplemap_bitop$191240 $auto$simplemap.cc:126:simplemap_reduce$316075 $auto$simplemap.cc:75:simplemap_bitop$316470 $auto$simplemap.cc:75:simplemap_bitop$315830 $auto$simplemap.cc:267:simplemap_mux$191080 $auto$simplemap.cc:267:simplemap_mux$190918 $auto$simplemap.cc:126:simplemap_reduce$190837 $auto$simplemap.cc:75:simplemap_bitop$190754 $auto$simplemap.cc:267:simplemap_mux$22277 $auto$simplemap.cc:38:simplemap_not$315765 $auto$simplemap.cc:267:simplemap_mux$190657 $auto$simplemap.cc:267:simplemap_mux$190495 $auto$simplemap.cc:126:simplemap_reduce$190411 $auto$simplemap.cc:75:simplemap_bitop$190331 $auto$simplemap.cc:75:simplemap_bitop$316341 $auto$simplemap.cc:75:simplemap_bitop$40088 $auto$simplemap.cc:75:simplemap_bitop$316501 $auto$simplemap.cc:38:simplemap_not$40184 $auto$simplemap.cc:126:simplemap_reduce$316092 $auto$simplemap.cc:75:simplemap_bitop$316373 $auto$simplemap.cc:75:simplemap_bitop$40120 $auto$simplemap.cc:75:simplemap_bitop$191239 $auto$simplemap.cc:126:simplemap_reduce$316090 $auto$simplemap.cc:75:simplemap_bitop$316469 $auto$simplemap.cc:75:simplemap_bitop$315829 $auto$simplemap.cc:267:simplemap_mux$191079 $auto$simplemap.cc:267:simplemap_mux$190917 $auto$simplemap.cc:126:simplemap_reduce$190833 $auto$simplemap.cc:75:simplemap_bitop$190753 $auto$simplemap.cc:267:simplemap_mux$22276 $auto$simplemap.cc:38:simplemap_not$315764 $auto$simplemap.cc:267:simplemap_mux$190656 $auto$simplemap.cc:267:simplemap_mux$190494 $auto$simplemap.cc:126:simplemap_reduce$190407 $auto$simplemap.cc:75:simplemap_bitop$190330 $auto$simplemap.cc:75:simplemap_bitop$316340 $auto$simplemap.cc:225:simplemap_logbin$315700 $auto$simplemap.cc:75:simplemap_bitop$316500 $auto$simplemap.cc:38:simplemap_not$40183 $auto$simplemap.cc:126:simplemap_reduce$316107 $auto$simplemap.cc:75:simplemap_bitop$316372 $auto$simplemap.cc:225:simplemap_logbin$315732 $auto$simplemap.cc:126:simplemap_reduce$16062 $auto$simplemap.cc:75:simplemap_bitop$191238 $auto$simplemap.cc:126:simplemap_reduce$316105 $auto$simplemap.cc:75:simplemap_bitop$316468 $auto$simplemap.cc:75:simplemap_bitop$315828 $auto$simplemap.cc:267:simplemap_mux$191078 $auto$simplemap.cc:267:simplemap_mux$190916 $auto$simplemap.cc:126:simplemap_reduce$190829 $auto$simplemap.cc:75:simplemap_bitop$190752 $auto$simplemap.cc:267:simplemap_mux$22275 $auto$simplemap.cc:38:simplemap_not$191173 $auto$simplemap.cc:267:simplemap_mux$190655 $auto$simplemap.cc:267:simplemap_mux$190493 $auto$simplemap.cc:126:simplemap_reduce$190403 $auto$simplemap.cc:75:simplemap_bitop$190329 $auto$simplemap.cc:75:simplemap_bitop$316339 $auto$simplemap.cc:75:simplemap_bitop$40086 $auto$simplemap.cc:75:simplemap_bitop$316499 $auto$simplemap.cc:38:simplemap_not$40182 $auto$simplemap.cc:126:simplemap_reduce$316122 $auto$simplemap.cc:75:simplemap_bitop$316371 $auto$simplemap.cc:75:simplemap_bitop$40118 $auto$simplemap.cc:75:simplemap_bitop$191237 $auto$simplemap.cc:126:simplemap_reduce$316120 $auto$simplemap.cc:75:simplemap_bitop$316467 $auto$simplemap.cc:75:simplemap_bitop$315827 $auto$simplemap.cc:267:simplemap_mux$191077 $auto$simplemap.cc:267:simplemap_mux$190915 $auto$simplemap.cc:126:simplemap_reduce$190825 $auto$simplemap.cc:75:simplemap_bitop$190751 $auto$simplemap.cc:267:simplemap_mux$22274 $auto$simplemap.cc:38:simplemap_not$315762 $auto$simplemap.cc:267:simplemap_mux$190654 $auto$simplemap.cc:267:simplemap_mux$190492 $auto$simplemap.cc:126:simplemap_reduce$190399 $auto$simplemap.cc:75:simplemap_bitop$190328 $auto$simplemap.cc:75:simplemap_bitop$316338 $auto$simplemap.cc:225:simplemap_logbin$315698 $auto$simplemap.cc:75:simplemap_bitop$316498 $auto$simplemap.cc:38:simplemap_not$40181 $auto$simplemap.cc:126:simplemap_reduce$316137 $auto$simplemap.cc:75:simplemap_bitop$316370 $auto$simplemap.cc:225:simplemap_logbin$315730 $auto$simplemap.cc:126:simplemap_reduce$16075 $auto$simplemap.cc:126:simplemap_reduce$16061 $auto$simplemap.cc:75:simplemap_bitop$191236 $auto$simplemap.cc:126:simplemap_reduce$316135 $auto$simplemap.cc:75:simplemap_bitop$316466 $auto$simplemap.cc:75:simplemap_bitop$315826 $auto$simplemap.cc:267:simplemap_mux$191076 $auto$simplemap.cc:267:simplemap_mux$190914 $auto$simplemap.cc:126:simplemap_reduce$190821 $auto$simplemap.cc:75:simplemap_bitop$190750 $auto$simplemap.cc:267:simplemap_mux$22273 $auto$simplemap.cc:38:simplemap_not$191171 $auto$simplemap.cc:267:simplemap_mux$190653 $auto$simplemap.cc:267:simplemap_mux$190491 $auto$simplemap.cc:126:simplemap_reduce$190395 $auto$simplemap.cc:75:simplemap_bitop$190327 $auto$simplemap.cc:75:simplemap_bitop$316337 $auto$simplemap.cc:75:simplemap_bitop$40084 $auto$simplemap.cc:75:simplemap_bitop$316497 $auto$simplemap.cc:38:simplemap_not$40180 $auto$simplemap.cc:126:simplemap_reduce$316152 $auto$simplemap.cc:75:simplemap_bitop$316369 $auto$simplemap.cc:75:simplemap_bitop$40116 $auto$simplemap.cc:75:simplemap_bitop$191235 $auto$simplemap.cc:126:simplemap_reduce$316150 $auto$simplemap.cc:75:simplemap_bitop$316465 $auto$simplemap.cc:75:simplemap_bitop$315825 $auto$simplemap.cc:267:simplemap_mux$191075 $auto$simplemap.cc:267:simplemap_mux$190913 $auto$simplemap.cc:126:simplemap_reduce$190817 $auto$simplemap.cc:75:simplemap_bitop$190749 $auto$simplemap.cc:267:simplemap_mux$22272 $auto$simplemap.cc:38:simplemap_not$315760 $auto$simplemap.cc:267:simplemap_mux$190652 $auto$simplemap.cc:267:simplemap_mux$190490 $auto$simplemap.cc:126:simplemap_reduce$190391 $auto$simplemap.cc:75:simplemap_bitop$190326 $auto$simplemap.cc:75:simplemap_bitop$316336 $auto$simplemap.cc:225:simplemap_logbin$315696 $auto$simplemap.cc:75:simplemap_bitop$316496 $auto$simplemap.cc:38:simplemap_not$40179 $auto$simplemap.cc:126:simplemap_reduce$316167 $auto$simplemap.cc:75:simplemap_bitop$316368 $auto$simplemap.cc:225:simplemap_logbin$315728 $auto$simplemap.cc:126:simplemap_reduce$16060 $auto$simplemap.cc:75:simplemap_bitop$191234 $auto$simplemap.cc:126:simplemap_reduce$316165 $auto$simplemap.cc:75:simplemap_bitop$316464 $auto$simplemap.cc:75:simplemap_bitop$315824 $auto$simplemap.cc:267:simplemap_mux$191074 $auto$simplemap.cc:267:simplemap_mux$190912 $auto$simplemap.cc:126:simplemap_reduce$190813 $auto$simplemap.cc:75:simplemap_bitop$190748 $auto$simplemap.cc:267:simplemap_mux$22271 $auto$simplemap.cc:38:simplemap_not$191169 $auto$simplemap.cc:267:simplemap_mux$190651 $auto$simplemap.cc:267:simplemap_mux$190489 $auto$simplemap.cc:126:simplemap_reduce$190387 $auto$simplemap.cc:75:simplemap_bitop$190325 $auto$simplemap.cc:75:simplemap_bitop$316335 $auto$simplemap.cc:75:simplemap_bitop$40082 $auto$simplemap.cc:75:simplemap_bitop$316495 $auto$simplemap.cc:38:simplemap_not$40178 $auto$simplemap.cc:126:simplemap_reduce$316182 $auto$simplemap.cc:75:simplemap_bitop$316367 $auto$simplemap.cc:75:simplemap_bitop$40114 $auto$simplemap.cc:75:simplemap_bitop$191233 $auto$simplemap.cc:126:simplemap_reduce$316180 $auto$simplemap.cc:75:simplemap_bitop$316463 $auto$simplemap.cc:75:simplemap_bitop$315823 $auto$simplemap.cc:267:simplemap_mux$191073 $auto$simplemap.cc:267:simplemap_mux$190911 $auto$simplemap.cc:126:simplemap_reduce$190809 $auto$simplemap.cc:75:simplemap_bitop$190747 $auto$simplemap.cc:267:simplemap_mux$22270 $auto$simplemap.cc:38:simplemap_not$315758 $auto$simplemap.cc:267:simplemap_mux$190650 $auto$simplemap.cc:267:simplemap_mux$190488 $auto$simplemap.cc:126:simplemap_reduce$190383 $auto$simplemap.cc:75:simplemap_bitop$190324 $auto$simplemap.cc:75:simplemap_bitop$316334 $auto$simplemap.cc:225:simplemap_logbin$315694 $auto$simplemap.cc:75:simplemap_bitop$316494 $auto$simplemap.cc:38:simplemap_not$40177 $auto$simplemap.cc:126:simplemap_reduce$316197 $auto$simplemap.cc:75:simplemap_bitop$316366 $auto$simplemap.cc:225:simplemap_logbin$315726 $auto$simplemap.cc:126:simplemap_reduce$16082 $auto$simplemap.cc:126:simplemap_reduce$16074 $auto$simplemap.cc:126:simplemap_reduce$16059 $auto$simplemap.cc:75:simplemap_bitop$191232 $auto$simplemap.cc:126:simplemap_reduce$316195 $auto$simplemap.cc:75:simplemap_bitop$316462 $auto$simplemap.cc:75:simplemap_bitop$315822 $auto$simplemap.cc:267:simplemap_mux$191072 $auto$simplemap.cc:267:simplemap_mux$190910 $auto$simplemap.cc:126:simplemap_reduce$190805 $auto$simplemap.cc:75:simplemap_bitop$190746 $auto$simplemap.cc:267:simplemap_mux$22269 $auto$simplemap.cc:38:simplemap_not$315757 $auto$simplemap.cc:267:simplemap_mux$190649 $auto$simplemap.cc:267:simplemap_mux$190487 $auto$simplemap.cc:126:simplemap_reduce$190379 $auto$simplemap.cc:75:simplemap_bitop$190323 $auto$simplemap.cc:75:simplemap_bitop$316333 $auto$simplemap.cc:75:simplemap_bitop$40080 $auto$simplemap.cc:75:simplemap_bitop$316493 $auto$simplemap.cc:38:simplemap_not$40176 $auto$simplemap.cc:126:simplemap_reduce$316212 $auto$simplemap.cc:75:simplemap_bitop$316365 $auto$simplemap.cc:75:simplemap_bitop$40112 $auto$simplemap.cc:75:simplemap_bitop$191231 $auto$simplemap.cc:126:simplemap_reduce$316210 $auto$simplemap.cc:75:simplemap_bitop$316461 $auto$simplemap.cc:75:simplemap_bitop$315821 $auto$simplemap.cc:267:simplemap_mux$191071 $auto$simplemap.cc:267:simplemap_mux$190909 $auto$simplemap.cc:126:simplemap_reduce$190801 $auto$simplemap.cc:75:simplemap_bitop$190745 $auto$simplemap.cc:267:simplemap_mux$22268 $auto$simplemap.cc:38:simplemap_not$315756 $auto$simplemap.cc:267:simplemap_mux$190648 $auto$simplemap.cc:267:simplemap_mux$190486 $auto$simplemap.cc:126:simplemap_reduce$190375 $auto$simplemap.cc:75:simplemap_bitop$190322 $auto$simplemap.cc:75:simplemap_bitop$316332 $auto$simplemap.cc:225:simplemap_logbin$315692 $auto$simplemap.cc:75:simplemap_bitop$316492 $auto$simplemap.cc:38:simplemap_not$40175 $auto$simplemap.cc:126:simplemap_reduce$316227 $auto$simplemap.cc:75:simplemap_bitop$316364 $auto$simplemap.cc:225:simplemap_logbin$315724 $auto$simplemap.cc:126:simplemap_reduce$16058 $auto$simplemap.cc:75:simplemap_bitop$191230 $auto$simplemap.cc:126:simplemap_reduce$316225 $auto$simplemap.cc:75:simplemap_bitop$316460 $auto$simplemap.cc:75:simplemap_bitop$315820 $auto$simplemap.cc:267:simplemap_mux$191070 $auto$simplemap.cc:267:simplemap_mux$190908 $auto$simplemap.cc:126:simplemap_reduce$190797 $auto$simplemap.cc:75:simplemap_bitop$190744 $auto$simplemap.cc:267:simplemap_mux$22267 $auto$simplemap.cc:38:simplemap_not$315755 $auto$simplemap.cc:267:simplemap_mux$190647 $auto$simplemap.cc:267:simplemap_mux$190485 $auto$simplemap.cc:126:simplemap_reduce$190371 $auto$simplemap.cc:75:simplemap_bitop$190321 $auto$simplemap.cc:75:simplemap_bitop$316331 $auto$simplemap.cc:75:simplemap_bitop$40078 $auto$simplemap.cc:75:simplemap_bitop$316491 $auto$simplemap.cc:38:simplemap_not$40174 $auto$simplemap.cc:126:simplemap_reduce$316242 $auto$simplemap.cc:75:simplemap_bitop$316363 $auto$simplemap.cc:75:simplemap_bitop$40110 $auto$simplemap.cc:126:simplemap_reduce$316240 $auto$simplemap.cc:75:simplemap_bitop$316459 $auto$simplemap.cc:75:simplemap_bitop$40142 $auto$simplemap.cc:75:simplemap_bitop$191229 $auto$simplemap.cc:267:simplemap_mux$191069 $auto$simplemap.cc:267:simplemap_mux$190907 $auto$simplemap.cc:126:simplemap_reduce$190793 $auto$simplemap.cc:75:simplemap_bitop$190743 $auto$simplemap.cc:267:simplemap_mux$22266 $auto$simplemap.cc:38:simplemap_not$191164 $auto$simplemap.cc:267:simplemap_mux$190646 $auto$simplemap.cc:267:simplemap_mux$190484 $auto$simplemap.cc:126:simplemap_reduce$190367 $auto$simplemap.cc:75:simplemap_bitop$190320 $auto$simplemap.cc:75:simplemap_bitop$316458 $auto$simplemap.cc:75:simplemap_bitop$40141 $auto$simplemap.cc:75:simplemap_bitop$316330 $auto$simplemap.cc:225:simplemap_logbin$315690 $auto$simplemap.cc:126:simplemap_reduce$316255 $auto$simplemap.cc:75:simplemap_bitop$316490 $auto$simplemap.cc:38:simplemap_not$40173 $auto$simplemap.cc:126:simplemap_reduce$316257 $auto$simplemap.cc:75:simplemap_bitop$316362 $auto$simplemap.cc:225:simplemap_logbin$315722 $auto$simplemap.cc:126:simplemap_reduce$16073 $auto$simplemap.cc:126:simplemap_reduce$16057 $auto$simplemap.cc:75:simplemap_bitop$191228 $auto$simplemap.cc:267:simplemap_mux$191068 $auto$simplemap.cc:267:simplemap_mux$190906 $auto$simplemap.cc:126:simplemap_reduce$190789 $auto$simplemap.cc:75:simplemap_bitop$190742 $auto$simplemap.cc:267:simplemap_mux$22265 $auto$simplemap.cc:38:simplemap_not$191163 $auto$simplemap.cc:267:simplemap_mux$190645 $auto$simplemap.cc:267:simplemap_mux$190483 $auto$simplemap.cc:126:simplemap_reduce$190363 $auto$simplemap.cc:75:simplemap_bitop$190319 $auto$simplemap.cc:75:simplemap_bitop$316329 $auto$simplemap.cc:75:simplemap_bitop$40076 $auto$simplemap.cc:75:simplemap_bitop$316489 $auto$simplemap.cc:38:simplemap_not$40172 $auto$simplemap.cc:126:simplemap_reduce$316272 $auto$simplemap.cc:75:simplemap_bitop$316361 $auto$simplemap.cc:75:simplemap_bitop$40108 $auto$simplemap.cc:75:simplemap_bitop$191227 $auto$simplemap.cc:126:simplemap_reduce$316270 $auto$simplemap.cc:75:simplemap_bitop$316457 $auto$simplemap.cc:75:simplemap_bitop$315817 $auto$simplemap.cc:267:simplemap_mux$191067 $auto$simplemap.cc:267:simplemap_mux$190905 $auto$simplemap.cc:126:simplemap_reduce$190785 $auto$simplemap.cc:75:simplemap_bitop$190741 $auto$simplemap.cc:267:simplemap_mux$22264 $auto$simplemap.cc:38:simplemap_not$191162 $auto$simplemap.cc:267:simplemap_mux$190644 $auto$simplemap.cc:267:simplemap_mux$190482 $auto$simplemap.cc:126:simplemap_reduce$190359 $auto$simplemap.cc:75:simplemap_bitop$190318 $auto$simplemap.cc:75:simplemap_bitop$316328 $auto$simplemap.cc:225:simplemap_logbin$315688 $auto$simplemap.cc:75:simplemap_bitop$316488 $auto$simplemap.cc:38:simplemap_not$40171 $auto$simplemap.cc:126:simplemap_reduce$316287 $auto$simplemap.cc:75:simplemap_bitop$316360 $auto$simplemap.cc:225:simplemap_logbin$315720 $auto$simplemap.cc:126:simplemap_reduce$16056 $auto$simplemap.cc:75:simplemap_bitop$191226 $auto$simplemap.cc:126:simplemap_reduce$316285 $auto$simplemap.cc:75:simplemap_bitop$316456 $auto$simplemap.cc:75:simplemap_bitop$315816 $auto$simplemap.cc:267:simplemap_mux$191066 $auto$simplemap.cc:267:simplemap_mux$190904 $auto$simplemap.cc:126:simplemap_reduce$190781 $auto$simplemap.cc:75:simplemap_bitop$190740 $auto$simplemap.cc:267:simplemap_mux$22263 $auto$simplemap.cc:38:simplemap_not$315751 $auto$simplemap.cc:267:simplemap_mux$190643 $auto$simplemap.cc:267:simplemap_mux$190481 $auto$simplemap.cc:126:simplemap_reduce$190355 $auto$simplemap.cc:75:simplemap_bitop$190317 $auto$simplemap.cc:75:simplemap_bitop$316327 $auto$simplemap.cc:75:simplemap_bitop$40074 $auto$simplemap.cc:75:simplemap_bitop$316487 $auto$simplemap.cc:38:simplemap_not$40170 $auto$simplemap.cc:126:simplemap_reduce$316302 $auto$simplemap.cc:75:simplemap_bitop$316359 $auto$simplemap.cc:75:simplemap_bitop$40106 $auto$simplemap.cc:75:simplemap_bitop$191225 $auto$simplemap.cc:126:simplemap_reduce$316300 $auto$simplemap.cc:75:simplemap_bitop$316455 $auto$simplemap.cc:75:simplemap_bitop$315815 $auto$simplemap.cc:267:simplemap_mux$191065 $auto$simplemap.cc:267:simplemap_mux$190903 $auto$simplemap.cc:126:simplemap_reduce$190777 $auto$simplemap.cc:75:simplemap_bitop$190739 $auto$simplemap.cc:267:simplemap_mux$22262 $auto$simplemap.cc:38:simplemap_not$315750 $auto$simplemap.cc:267:simplemap_mux$190642 $auto$simplemap.cc:267:simplemap_mux$190480 $auto$simplemap.cc:126:simplemap_reduce$190351 $auto$simplemap.cc:75:simplemap_bitop$190316 $auto$simplemap.cc:75:simplemap_bitop$316518 $auto$simplemap.cc:126:simplemap_reduce$16089 $auto$simplemap.cc:126:simplemap_reduce$16086 $auto$simplemap.cc:126:simplemap_reduce$16081 $auto$simplemap.cc:126:simplemap_reduce$16072 $auto$simplemap.cc:126:simplemap_reduce$16055 $auto$simplemap.cc:75:simplemap_bitop$191224 $auto$simplemap.cc:126:simplemap_reduce$316314 $auto$simplemap.cc:75:simplemap_bitop$316550 $auto$simplemap.cc:267:simplemap_mux$40201 $auto$simplemap.cc:75:simplemap_bitop$316582 $auto$simplemap.cc:126:simplemap_reduce$21307 $auto$simplemap.cc:38:simplemap_not$30976 $auto$alumacc.cc:485:replace_alu$6986.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$6986.slice[0].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316452 $auto$simplemap.cc:75:simplemap_bitop$316453 $auto$alumacc.cc:485:replace_alu$7002.slice[30].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316450 $auto$simplemap.cc:75:simplemap_bitop$316451 $auto$alumacc.cc:485:replace_alu$7002.slice[28].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316448 $auto$simplemap.cc:75:simplemap_bitop$316449 $auto$alumacc.cc:485:replace_alu$7002.slice[26].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316446 $auto$simplemap.cc:75:simplemap_bitop$316447 $auto$alumacc.cc:485:replace_alu$7002.slice[24].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316444 $auto$simplemap.cc:75:simplemap_bitop$316445 $auto$alumacc.cc:485:replace_alu$7002.slice[22].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316442 $auto$simplemap.cc:75:simplemap_bitop$316443 $auto$alumacc.cc:485:replace_alu$7002.slice[20].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316440 $auto$simplemap.cc:75:simplemap_bitop$316441 $auto$alumacc.cc:485:replace_alu$7002.slice[18].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316438 $auto$simplemap.cc:75:simplemap_bitop$316439 $auto$alumacc.cc:485:replace_alu$7002.slice[16].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316436 $auto$simplemap.cc:75:simplemap_bitop$316437 $auto$alumacc.cc:485:replace_alu$7002.slice[14].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316434 $auto$simplemap.cc:75:simplemap_bitop$316435 $auto$alumacc.cc:485:replace_alu$7002.slice[12].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316432 $auto$simplemap.cc:75:simplemap_bitop$316433 $auto$alumacc.cc:485:replace_alu$7002.slice[10].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316430 $auto$simplemap.cc:75:simplemap_bitop$316431 $auto$alumacc.cc:485:replace_alu$7002.slice[8].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316428 $auto$simplemap.cc:75:simplemap_bitop$316429 $auto$alumacc.cc:485:replace_alu$7002.slice[6].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316426 $auto$simplemap.cc:75:simplemap_bitop$316427 $auto$alumacc.cc:485:replace_alu$7002.slice[4].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316424 $auto$simplemap.cc:75:simplemap_bitop$316425 $auto$alumacc.cc:485:replace_alu$7002.slice[2].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316422 $auto$simplemap.cc:75:simplemap_bitop$316423 $auto$alumacc.cc:485:replace_alu$7002.slice[0].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$316326 $auto$simplemap.cc:225:simplemap_logbin$315686 $auto$simplemap.cc:75:simplemap_bitop$316486 $auto$simplemap.cc:38:simplemap_not$40169 $auto$simplemap.cc:126:simplemap_reduce$316317 $auto$simplemap.cc:75:simplemap_bitop$316358 $auto$simplemap.cc:225:simplemap_logbin$315718 $auto$simplemap.cc:126:simplemap_reduce$316320 $auto$simplemap.cc:126:simplemap_reduce$316315 $auto$simplemap.cc:75:simplemap_bitop$316454 $auto$simplemap.cc:75:simplemap_bitop$315814 $auto$simplemap.cc:126:simplemap_reduce$315871 $auto$simplemap.cc:126:simplemap_reduce$315866 $auto$simplemap.cc:75:simplemap_bitop$316420 $auto$simplemap.cc:126:simplemap_reduce$315856 $auto$simplemap.cc:126:simplemap_reduce$315851 $auto$simplemap.cc:75:simplemap_bitop$316421 $auto$alumacc.cc:485:replace_alu$6999.slice[30].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$315901 $auto$simplemap.cc:126:simplemap_reduce$315896 $auto$simplemap.cc:75:simplemap_bitop$316418 $auto$simplemap.cc:126:simplemap_reduce$315886 $auto$simplemap.cc:126:simplemap_reduce$315881 $auto$simplemap.cc:75:simplemap_bitop$316419 $auto$alumacc.cc:485:replace_alu$6999.slice[28].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$315931 $auto$simplemap.cc:126:simplemap_reduce$315926 $auto$simplemap.cc:75:simplemap_bitop$316416 $auto$simplemap.cc:126:simplemap_reduce$315911 $auto$simplemap.cc:75:simplemap_bitop$316417 $auto$alumacc.cc:485:replace_alu$6999.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$315961 $auto$simplemap.cc:126:simplemap_reduce$315956 $auto$simplemap.cc:75:simplemap_bitop$316414 $auto$simplemap.cc:126:simplemap_reduce$315946 $auto$simplemap.cc:126:simplemap_reduce$315941 $auto$simplemap.cc:75:simplemap_bitop$316415 $auto$alumacc.cc:485:replace_alu$6999.slice[24].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$315991 $auto$simplemap.cc:126:simplemap_reduce$315986 $auto$simplemap.cc:75:simplemap_bitop$316412 $auto$simplemap.cc:126:simplemap_reduce$315976 $auto$simplemap.cc:126:simplemap_reduce$315971 $auto$simplemap.cc:75:simplemap_bitop$316413 $auto$alumacc.cc:485:replace_alu$6999.slice[22].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316021 $auto$simplemap.cc:126:simplemap_reduce$316016 $auto$simplemap.cc:75:simplemap_bitop$316410 $auto$simplemap.cc:126:simplemap_reduce$316006 $auto$simplemap.cc:126:simplemap_reduce$316001 $auto$simplemap.cc:75:simplemap_bitop$316411 $auto$alumacc.cc:485:replace_alu$6999.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316051 $auto$simplemap.cc:126:simplemap_reduce$316046 $auto$simplemap.cc:75:simplemap_bitop$316408 $auto$simplemap.cc:126:simplemap_reduce$316036 $auto$simplemap.cc:126:simplemap_reduce$316031 $auto$simplemap.cc:75:simplemap_bitop$316409 $auto$alumacc.cc:485:replace_alu$6999.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316081 $auto$simplemap.cc:126:simplemap_reduce$316076 $auto$simplemap.cc:75:simplemap_bitop$316406 $auto$simplemap.cc:126:simplemap_reduce$316066 $auto$simplemap.cc:126:simplemap_reduce$316061 $auto$simplemap.cc:75:simplemap_bitop$316407 $auto$alumacc.cc:485:replace_alu$6999.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316111 $auto$simplemap.cc:126:simplemap_reduce$316106 $auto$simplemap.cc:75:simplemap_bitop$316404 $auto$simplemap.cc:126:simplemap_reduce$316096 $auto$simplemap.cc:126:simplemap_reduce$316091 $auto$simplemap.cc:75:simplemap_bitop$316405 $auto$alumacc.cc:485:replace_alu$6999.slice[14].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316141 $auto$simplemap.cc:126:simplemap_reduce$316136 $auto$simplemap.cc:75:simplemap_bitop$316402 $auto$simplemap.cc:126:simplemap_reduce$316126 $auto$simplemap.cc:126:simplemap_reduce$316121 $auto$simplemap.cc:75:simplemap_bitop$316403 $auto$alumacc.cc:485:replace_alu$6999.slice[12].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316171 $auto$simplemap.cc:126:simplemap_reduce$316166 $auto$simplemap.cc:75:simplemap_bitop$316400 $auto$simplemap.cc:126:simplemap_reduce$316156 $auto$simplemap.cc:126:simplemap_reduce$316151 $auto$simplemap.cc:75:simplemap_bitop$316401 $auto$alumacc.cc:485:replace_alu$6999.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316201 $auto$simplemap.cc:126:simplemap_reduce$316196 $auto$simplemap.cc:75:simplemap_bitop$316398 $auto$simplemap.cc:126:simplemap_reduce$316186 $auto$simplemap.cc:126:simplemap_reduce$316181 $auto$simplemap.cc:75:simplemap_bitop$316399 $auto$alumacc.cc:485:replace_alu$6999.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316231 $auto$simplemap.cc:126:simplemap_reduce$316226 $auto$simplemap.cc:75:simplemap_bitop$316396 $auto$simplemap.cc:126:simplemap_reduce$316216 $auto$simplemap.cc:126:simplemap_reduce$316211 $auto$simplemap.cc:75:simplemap_bitop$316397 $auto$alumacc.cc:485:replace_alu$6999.slice[6].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316261 $auto$simplemap.cc:126:simplemap_reduce$316256 $auto$simplemap.cc:75:simplemap_bitop$316394 $auto$simplemap.cc:126:simplemap_reduce$316246 $auto$simplemap.cc:126:simplemap_reduce$316241 $auto$simplemap.cc:75:simplemap_bitop$316395 $auto$alumacc.cc:485:replace_alu$6999.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316291 $auto$simplemap.cc:126:simplemap_reduce$316286 $auto$simplemap.cc:75:simplemap_bitop$316392 $auto$simplemap.cc:126:simplemap_reduce$316276 $auto$simplemap.cc:126:simplemap_reduce$316271 $auto$simplemap.cc:75:simplemap_bitop$316393 $auto$alumacc.cc:485:replace_alu$6999.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316321 $auto$simplemap.cc:126:simplemap_reduce$316316 $auto$simplemap.cc:75:simplemap_bitop$316390 $auto$simplemap.cc:126:simplemap_reduce$316306 $auto$simplemap.cc:126:simplemap_reduce$316301 $auto$simplemap.cc:75:simplemap_bitop$316391 $auto$alumacc.cc:485:replace_alu$6999.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$316313 $auto$simplemap.cc:75:simplemap_bitop$316614 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40267 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40331 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40395 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40459 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40523 $auto$simplemap.cc:75:simplemap_bitop$316615 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40268 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40332 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40396 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40460 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40524 $auto$simplemap.cc:75:simplemap_bitop$316616 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40269 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40333 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40397 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40461 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40525 $auto$simplemap.cc:75:simplemap_bitop$316617 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40270 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40334 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40398 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40462 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40526 $auto$simplemap.cc:75:simplemap_bitop$316618 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40271 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40335 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40399 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40463 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40527 $auto$simplemap.cc:75:simplemap_bitop$316619 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40272 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40336 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40400 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40464 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40528 $auto$simplemap.cc:75:simplemap_bitop$316620 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40273 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40337 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40401 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40465 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40529 $auto$simplemap.cc:75:simplemap_bitop$316621 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40274 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40338 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40402 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40466 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40530 $auto$simplemap.cc:75:simplemap_bitop$316622 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40275 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40339 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40403 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40467 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40531 $auto$simplemap.cc:75:simplemap_bitop$316623 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40276 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40340 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40404 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40468 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40532 $auto$simplemap.cc:75:simplemap_bitop$316624 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40277 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40341 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40405 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40469 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40533 $auto$simplemap.cc:75:simplemap_bitop$316625 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40278 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40342 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40406 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40470 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40534 $auto$simplemap.cc:75:simplemap_bitop$316626 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40279 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40343 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40407 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40471 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40535 $auto$simplemap.cc:75:simplemap_bitop$316627 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40280 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40344 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40408 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40472 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40536 $auto$simplemap.cc:75:simplemap_bitop$316628 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40281 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40345 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40409 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40473 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40537 $auto$simplemap.cc:75:simplemap_bitop$316629 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40282 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40346 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40410 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40474 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40538 $auto$simplemap.cc:75:simplemap_bitop$316630 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40283 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40347 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40411 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40475 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40539 $auto$simplemap.cc:75:simplemap_bitop$316631 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40284 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40348 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40412 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40476 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40540 $auto$simplemap.cc:75:simplemap_bitop$316632 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40285 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40349 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40413 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40477 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40541 $auto$simplemap.cc:75:simplemap_bitop$316633 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40286 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40350 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40414 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40478 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40542 $auto$simplemap.cc:75:simplemap_bitop$316634 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40287 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40351 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40415 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40479 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40543 $auto$simplemap.cc:75:simplemap_bitop$316635 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40288 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40352 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40416 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40480 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40544 $auto$simplemap.cc:75:simplemap_bitop$316636 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40289 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40353 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40417 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40481 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40545 $auto$simplemap.cc:75:simplemap_bitop$316637 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40290 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40354 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40418 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40482 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40546 $auto$simplemap.cc:75:simplemap_bitop$316638 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40291 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40355 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40419 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40483 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40547 $auto$simplemap.cc:75:simplemap_bitop$316639 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40292 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40356 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40420 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40484 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40548 $auto$simplemap.cc:75:simplemap_bitop$316640 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40293 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40357 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40421 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40485 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40549 $auto$simplemap.cc:75:simplemap_bitop$316641 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40294 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40358 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40422 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40486 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40550 $auto$simplemap.cc:75:simplemap_bitop$316642 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40295 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40359 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40423 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40487 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40551 $auto$simplemap.cc:75:simplemap_bitop$316643 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40296 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40360 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40424 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40488 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40552 $auto$simplemap.cc:75:simplemap_bitop$316644 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40297 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40361 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40425 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40489 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40553 $auto$simplemap.cc:75:simplemap_bitop$316645 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40298 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40362 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40426 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40490 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$603.$auto$simplemap.cc:267:simplemap_mux$40554 $auto$simplemap.cc:75:simplemap_bitop$316676 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40697 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40793 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40889 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40985 $auto$simplemap.cc:267:simplemap_mux$316740 $auto$simplemap.cc:126:simplemap_reduce$315875 $auto$simplemap.cc:126:simplemap_reduce$315873 $auto$simplemap.cc:126:simplemap_reduce$315869 $auto$simplemap.cc:126:simplemap_reduce$315862 $auto$simplemap.cc:75:simplemap_bitop$316708 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41225 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41321 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41417 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41513 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$41081 $auto$simplemap.cc:126:simplemap_reduce$42749 $auto$simplemap.cc:267:simplemap_mux$316741 $auto$simplemap.cc:126:simplemap_reduce$315860 $auto$simplemap.cc:126:simplemap_reduce$315858 $auto$simplemap.cc:126:simplemap_reduce$315854 $auto$simplemap.cc:126:simplemap_reduce$315847 $auto$simplemap.cc:75:simplemap_bitop$316677 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40698 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40794 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40890 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40986 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$41082 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41579 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41580 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41483 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41581 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41484 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41582 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41485 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41583 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41486 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41584 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41387 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41487 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41585 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41388 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41488 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41586 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41389 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41489 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41587 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41390 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41490 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41588 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41391 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41491 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41589 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41392 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41492 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41590 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41393 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41493 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41591 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41394 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41494 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41592 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41291 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41395 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41495 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41593 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41292 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41396 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41496 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41594 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41293 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41397 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41497 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41595 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41294 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41398 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41498 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41596 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41295 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41399 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41499 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41597 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41296 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41400 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41500 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41598 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41297 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41401 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41501 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41599 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41298 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41402 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41502 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41600 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41299 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41403 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41503 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41601 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41300 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41404 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41504 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41602 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41301 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41405 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41505 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41603 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41302 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41406 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41506 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41604 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41303 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41407 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41507 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41605 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41304 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41408 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41508 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41606 $auto$simplemap.cc:75:simplemap_bitop$316648 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40669 $auto$simplemap.cc:75:simplemap_bitop$316664 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40685 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40781 $auto$simplemap.cc:75:simplemap_bitop$316656 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40677 $auto$simplemap.cc:75:simplemap_bitop$316672 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40693 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40789 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40885 $auto$simplemap.cc:75:simplemap_bitop$316652 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40673 $auto$simplemap.cc:75:simplemap_bitop$316668 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40689 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40785 $auto$simplemap.cc:75:simplemap_bitop$316660 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40681 $auto$simplemap.cc:267:simplemap_mux$316724 $auto$simplemap.cc:126:simplemap_reduce$316115 $auto$simplemap.cc:126:simplemap_reduce$316113 $auto$simplemap.cc:126:simplemap_reduce$316109 $auto$simplemap.cc:126:simplemap_reduce$316102 $auto$simplemap.cc:75:simplemap_bitop$316692 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41209 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41305 $auto$simplemap.cc:267:simplemap_mux$316716 $auto$simplemap.cc:126:simplemap_reduce$316235 $auto$simplemap.cc:126:simplemap_reduce$316233 $auto$simplemap.cc:126:simplemap_reduce$316229 $auto$simplemap.cc:126:simplemap_reduce$316222 $auto$simplemap.cc:75:simplemap_bitop$316684 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41201 $auto$simplemap.cc:267:simplemap_mux$316732 $auto$simplemap.cc:126:simplemap_reduce$315995 $auto$simplemap.cc:126:simplemap_reduce$315993 $auto$simplemap.cc:126:simplemap_reduce$315989 $auto$simplemap.cc:126:simplemap_reduce$315982 $auto$simplemap.cc:75:simplemap_bitop$316700 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41217 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41313 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41409 $auto$simplemap.cc:267:simplemap_mux$316712 $auto$simplemap.cc:126:simplemap_reduce$316295 $auto$simplemap.cc:126:simplemap_reduce$316293 $auto$simplemap.cc:126:simplemap_reduce$316289 $auto$simplemap.cc:126:simplemap_reduce$316282 $auto$simplemap.cc:75:simplemap_bitop$316680 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41197 $auto$simplemap.cc:267:simplemap_mux$316728 $auto$simplemap.cc:126:simplemap_reduce$316055 $auto$simplemap.cc:126:simplemap_reduce$316053 $auto$simplemap.cc:126:simplemap_reduce$316049 $auto$simplemap.cc:126:simplemap_reduce$316042 $auto$simplemap.cc:75:simplemap_bitop$316696 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41213 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41309 $auto$simplemap.cc:267:simplemap_mux$316720 $auto$simplemap.cc:126:simplemap_reduce$316175 $auto$simplemap.cc:126:simplemap_reduce$316173 $auto$simplemap.cc:126:simplemap_reduce$316169 $auto$simplemap.cc:126:simplemap_reduce$316162 $auto$simplemap.cc:75:simplemap_bitop$316688 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41205 $auto$simplemap.cc:267:simplemap_mux$316736 $auto$simplemap.cc:126:simplemap_reduce$315935 $auto$simplemap.cc:126:simplemap_reduce$315933 $auto$simplemap.cc:126:simplemap_reduce$315929 $auto$simplemap.cc:126:simplemap_reduce$315922 $auto$simplemap.cc:75:simplemap_bitop$316704 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41221 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41317 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41413 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41509 $auto$simplemap.cc:75:simplemap_bitop$316650 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40671 $auto$simplemap.cc:75:simplemap_bitop$316666 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40687 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40783 $auto$simplemap.cc:75:simplemap_bitop$316658 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40679 $auto$simplemap.cc:75:simplemap_bitop$316674 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40695 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40791 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40887 $auto$simplemap.cc:75:simplemap_bitop$316654 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40675 $auto$simplemap.cc:75:simplemap_bitop$316670 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40691 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40787 $auto$simplemap.cc:75:simplemap_bitop$316662 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40683 $auto$simplemap.cc:75:simplemap_bitop$316646 $auto$simplemap.cc:267:simplemap_mux$316710 $auto$simplemap.cc:126:simplemap_reduce$316325 $auto$simplemap.cc:126:simplemap_reduce$316323 $auto$simplemap.cc:126:simplemap_reduce$316319 $auto$simplemap.cc:126:simplemap_reduce$316312 $auto$simplemap.cc:75:simplemap_bitop$316678 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41195 $auto$simplemap.cc:267:simplemap_mux$316726 $auto$simplemap.cc:126:simplemap_reduce$316085 $auto$simplemap.cc:126:simplemap_reduce$316083 $auto$simplemap.cc:126:simplemap_reduce$316079 $auto$simplemap.cc:126:simplemap_reduce$316072 $auto$simplemap.cc:75:simplemap_bitop$316694 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41211 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41307 $auto$simplemap.cc:267:simplemap_mux$316718 $auto$simplemap.cc:126:simplemap_reduce$316205 $auto$simplemap.cc:126:simplemap_reduce$316203 $auto$simplemap.cc:126:simplemap_reduce$316199 $auto$simplemap.cc:126:simplemap_reduce$316192 $auto$simplemap.cc:75:simplemap_bitop$316686 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41203 $auto$simplemap.cc:267:simplemap_mux$316734 $auto$simplemap.cc:126:simplemap_reduce$315965 $auto$simplemap.cc:126:simplemap_reduce$315963 $auto$simplemap.cc:126:simplemap_reduce$315959 $auto$simplemap.cc:126:simplemap_reduce$315952 $auto$simplemap.cc:75:simplemap_bitop$316702 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41219 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41315 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41411 $auto$simplemap.cc:267:simplemap_mux$316714 $auto$simplemap.cc:126:simplemap_reduce$316265 $auto$simplemap.cc:126:simplemap_reduce$316263 $auto$simplemap.cc:126:simplemap_reduce$316259 $auto$simplemap.cc:126:simplemap_reduce$316252 $auto$simplemap.cc:75:simplemap_bitop$316682 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41199 $auto$simplemap.cc:267:simplemap_mux$316730 $auto$simplemap.cc:126:simplemap_reduce$316025 $auto$simplemap.cc:126:simplemap_reduce$316023 $auto$simplemap.cc:126:simplemap_reduce$316019 $auto$simplemap.cc:126:simplemap_reduce$316012 $auto$simplemap.cc:75:simplemap_bitop$316698 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41215 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41311 $auto$simplemap.cc:267:simplemap_mux$316722 $auto$simplemap.cc:126:simplemap_reduce$316145 $auto$simplemap.cc:126:simplemap_reduce$316143 $auto$simplemap.cc:126:simplemap_reduce$316139 $auto$simplemap.cc:126:simplemap_reduce$316132 $auto$simplemap.cc:75:simplemap_bitop$316690 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41207 $auto$simplemap.cc:267:simplemap_mux$316738 $auto$simplemap.cc:126:simplemap_reduce$315905 $auto$simplemap.cc:126:simplemap_reduce$315903 $auto$simplemap.cc:126:simplemap_reduce$315899 $auto$simplemap.cc:126:simplemap_reduce$315892 $auto$simplemap.cc:75:simplemap_bitop$316706 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41223 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41319 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41415 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41511 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41607 $auto$simplemap.cc:75:simplemap_bitop$316647 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40668 $auto$simplemap.cc:75:simplemap_bitop$316663 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40684 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40780 $auto$simplemap.cc:75:simplemap_bitop$316655 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40676 $auto$simplemap.cc:75:simplemap_bitop$316671 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40692 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40788 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40884 $auto$simplemap.cc:75:simplemap_bitop$316651 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40672 $auto$simplemap.cc:75:simplemap_bitop$316667 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40688 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40784 $auto$simplemap.cc:75:simplemap_bitop$316659 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40680 $auto$simplemap.cc:75:simplemap_bitop$316675 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40696 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40792 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40888 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40984 $auto$simplemap.cc:75:simplemap_bitop$316649 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40670 $auto$simplemap.cc:75:simplemap_bitop$316665 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40686 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40782 $auto$simplemap.cc:75:simplemap_bitop$316657 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40678 $auto$simplemap.cc:75:simplemap_bitop$316673 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40694 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40790 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40886 $auto$simplemap.cc:75:simplemap_bitop$316653 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40674 $auto$simplemap.cc:75:simplemap_bitop$316669 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40690 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40786 $auto$simplemap.cc:75:simplemap_bitop$316661 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$604.$auto$simplemap.cc:267:simplemap_mux$40682 $auto$simplemap.cc:126:simplemap_reduce$42741 $auto$simplemap.cc:267:simplemap_mux$316725 $auto$simplemap.cc:126:simplemap_reduce$316100 $auto$simplemap.cc:126:simplemap_reduce$316098 $auto$simplemap.cc:126:simplemap_reduce$316094 $auto$simplemap.cc:126:simplemap_reduce$316087 $auto$simplemap.cc:75:simplemap_bitop$316693 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41210 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41306 $auto$simplemap.cc:126:simplemap_reduce$42737 $auto$simplemap.cc:267:simplemap_mux$316717 $auto$simplemap.cc:126:simplemap_reduce$316220 $auto$simplemap.cc:126:simplemap_reduce$316218 $auto$simplemap.cc:126:simplemap_reduce$316214 $auto$simplemap.cc:126:simplemap_reduce$316207 $auto$simplemap.cc:75:simplemap_bitop$316685 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41202 $auto$simplemap.cc:126:simplemap_reduce$42745 $auto$simplemap.cc:267:simplemap_mux$316733 $auto$simplemap.cc:126:simplemap_reduce$315980 $auto$simplemap.cc:126:simplemap_reduce$315978 $auto$simplemap.cc:126:simplemap_reduce$315974 $auto$simplemap.cc:126:simplemap_reduce$315967 $auto$simplemap.cc:75:simplemap_bitop$316701 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41218 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41314 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41410 $auto$simplemap.cc:126:simplemap_reduce$42735 $auto$simplemap.cc:267:simplemap_mux$316713 $auto$simplemap.cc:126:simplemap_reduce$316280 $auto$simplemap.cc:126:simplemap_reduce$316278 $auto$simplemap.cc:126:simplemap_reduce$316274 $auto$simplemap.cc:126:simplemap_reduce$316267 $auto$simplemap.cc:75:simplemap_bitop$316681 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41198 $auto$simplemap.cc:126:simplemap_reduce$42743 $auto$simplemap.cc:267:simplemap_mux$316729 $auto$simplemap.cc:126:simplemap_reduce$316040 $auto$simplemap.cc:126:simplemap_reduce$316038 $auto$simplemap.cc:126:simplemap_reduce$316034 $auto$simplemap.cc:126:simplemap_reduce$316027 $auto$simplemap.cc:75:simplemap_bitop$316697 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41214 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41310 $auto$simplemap.cc:126:simplemap_reduce$42739 $auto$simplemap.cc:267:simplemap_mux$316721 $auto$simplemap.cc:126:simplemap_reduce$316160 $auto$simplemap.cc:126:simplemap_reduce$316158 $auto$simplemap.cc:126:simplemap_reduce$316154 $auto$simplemap.cc:126:simplemap_reduce$316147 $auto$simplemap.cc:75:simplemap_bitop$316689 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41206 $auto$simplemap.cc:126:simplemap_reduce$315918 $auto$simplemap.cc:126:simplemap_reduce$315914 $auto$simplemap.cc:126:simplemap_reduce$315907 $auto$simplemap.cc:75:simplemap_bitop$316705 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41222 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41318 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41414 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41510 $auto$simplemap.cc:126:simplemap_reduce$42751 $auto$simplemap.cc:126:simplemap_reduce$42734 $auto$simplemap.cc:267:simplemap_mux$316711 $auto$simplemap.cc:126:simplemap_reduce$316310 $auto$simplemap.cc:126:simplemap_reduce$316308 $auto$simplemap.cc:126:simplemap_reduce$316304 $auto$simplemap.cc:126:simplemap_reduce$316297 $auto$simplemap.cc:75:simplemap_bitop$316679 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41196 $auto$simplemap.cc:126:simplemap_reduce$42755 $auto$simplemap.cc:126:simplemap_reduce$42742 $auto$simplemap.cc:267:simplemap_mux$316727 $auto$simplemap.cc:126:simplemap_reduce$316070 $auto$simplemap.cc:126:simplemap_reduce$316068 $auto$simplemap.cc:126:simplemap_reduce$316064 $auto$simplemap.cc:126:simplemap_reduce$316057 $auto$simplemap.cc:75:simplemap_bitop$316695 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41212 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41308 $auto$simplemap.cc:126:simplemap_reduce$42753 $auto$simplemap.cc:126:simplemap_reduce$42738 $auto$simplemap.cc:267:simplemap_mux$316719 $auto$simplemap.cc:126:simplemap_reduce$316190 $auto$simplemap.cc:126:simplemap_reduce$316188 $auto$simplemap.cc:126:simplemap_reduce$316184 $auto$simplemap.cc:126:simplemap_reduce$316177 $auto$simplemap.cc:75:simplemap_bitop$316687 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41204 $auto$simplemap.cc:126:simplemap_reduce$42746 $auto$simplemap.cc:267:simplemap_mux$316735 $auto$simplemap.cc:126:simplemap_reduce$315950 $auto$simplemap.cc:126:simplemap_reduce$315948 $auto$simplemap.cc:126:simplemap_reduce$315944 $auto$simplemap.cc:126:simplemap_reduce$315937 $auto$simplemap.cc:75:simplemap_bitop$316703 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41220 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41316 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41412 $auto$simplemap.cc:126:simplemap_reduce$42760 $auto$simplemap.cc:126:simplemap_reduce$42752 $auto$simplemap.cc:126:simplemap_reduce$42736 $auto$simplemap.cc:267:simplemap_mux$316715 $auto$simplemap.cc:126:simplemap_reduce$316250 $auto$simplemap.cc:126:simplemap_reduce$316248 $auto$simplemap.cc:126:simplemap_reduce$316244 $auto$simplemap.cc:126:simplemap_reduce$316237 $auto$simplemap.cc:75:simplemap_bitop$316683 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41200 $auto$simplemap.cc:126:simplemap_reduce$42762 $auto$simplemap.cc:126:simplemap_reduce$42756 $auto$simplemap.cc:126:simplemap_reduce$42744 $auto$simplemap.cc:267:simplemap_mux$316731 $auto$simplemap.cc:126:simplemap_reduce$316010 $auto$simplemap.cc:126:simplemap_reduce$316008 $auto$simplemap.cc:126:simplemap_reduce$316004 $auto$simplemap.cc:126:simplemap_reduce$315997 $auto$simplemap.cc:75:simplemap_bitop$316699 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41216 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41312 $auto$simplemap.cc:126:simplemap_reduce$42765 $auto$simplemap.cc:126:simplemap_reduce$42761 $auto$simplemap.cc:126:simplemap_reduce$42754 $auto$simplemap.cc:126:simplemap_reduce$42740 $auto$simplemap.cc:267:simplemap_mux$316723 $auto$simplemap.cc:126:simplemap_reduce$316130 $auto$simplemap.cc:126:simplemap_reduce$316128 $auto$simplemap.cc:126:simplemap_reduce$316124 $auto$simplemap.cc:126:simplemap_reduce$316117 $auto$simplemap.cc:75:simplemap_bitop$316691 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41208 $auto$simplemap.cc:126:simplemap_reduce$42758 $auto$simplemap.cc:126:simplemap_reduce$42748 $auto$simplemap.cc:267:simplemap_mux$316739 $auto$simplemap.cc:126:simplemap_reduce$315890 $auto$simplemap.cc:126:simplemap_reduce$315888 $auto$simplemap.cc:126:simplemap_reduce$315884 $auto$simplemap.cc:126:simplemap_reduce$315877 $auto$simplemap.cc:75:simplemap_bitop$316707 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41224 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41320 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41416 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41512 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$605.$auto$simplemap.cc:267:simplemap_mux$41608 $auto$simplemap.cc:267:simplemap_mux$191064 $auto$simplemap.cc:267:simplemap_mux$190902 $auto$simplemap.cc:126:simplemap_reduce$190773 $auto$simplemap.cc:75:simplemap_bitop$190738 $auto$simplemap.cc:267:simplemap_mux$22261 $auto$ff.cc:266:slice$43912 $auto$simplemap.cc:225:simplemap_logbin$44271 $auto$simplemap.cc:75:simplemap_bitop$43845 $auto$simplemap.cc:75:simplemap_bitop$43846 $auto$simplemap.cc:75:simplemap_bitop$43847 $auto$ff.cc:266:slice$42908 $auto$ff.cc:479:convert_ce_over_srst$326471 $auto$simplemap.cc:126:simplemap_reduce$13287 $auto$simplemap.cc:126:simplemap_reduce$13285 $auto$simplemap.cc:126:simplemap_reduce$13052 $auto$opt_expr.cc:617:replace_const_cells$325327 $auto$simplemap.cc:75:simplemap_bitop$43785 $auto$simplemap.cc:225:simplemap_logbin$42771 $auto$simplemap.cc:225:simplemap_logbin$42774 $auto$simplemap.cc:126:simplemap_reduce$42779 $auto$simplemap.cc:267:simplemap_mux$40060 $auto$ff.cc:266:slice$42040 $auto$simplemap.cc:225:simplemap_logbin$42572 $auto$simplemap.cc:225:simplemap_logbin$42574 $auto$simplemap.cc:225:simplemap_logbin$42576 $auto$simplemap.cc:225:simplemap_logbin$38920 $auto$simplemap.cc:75:simplemap_bitop$38922 $auto$simplemap.cc:75:simplemap_bitop$38923 $auto$simplemap.cc:196:simplemap_lognot$46021 $auto$simplemap.cc:225:simplemap_logbin$42770 $auto$simplemap.cc:225:simplemap_logbin$40072 $auto$simplemap.cc:38:simplemap_not$40064 $auto$simplemap.cc:126:simplemap_reduce$42768 $auto$simplemap.cc:126:simplemap_reduce$42766 $auto$simplemap.cc:126:simplemap_reduce$42763 $auto$simplemap.cc:126:simplemap_reduce$42757 $auto$simplemap.cc:126:simplemap_reduce$42747 $auto$simplemap.cc:267:simplemap_mux$316737 $auto$simplemap.cc:126:simplemap_reduce$315920 $auto$simplemap.cc:126:simplemap_reduce$315916 $auto$simplemap.cc:126:simplemap_reduce$315912 $auto$simplemap.cc:75:simplemap_bitop$316353
Found an SCC: $auto$ff.cc:266:slice$22247 $auto$simplemap.cc:126:simplemap_reduce$21317 $auto$simplemap.cc:225:simplemap_logbin$22045
Found an SCC: $auto$ff.cc:266:slice$21963 $auto$simplemap.cc:126:simplemap_reduce$21311 $auto$simplemap.cc:225:simplemap_logbin$21901
Found an SCC: $auto$ff.cc:266:slice$17340 $auto$ff.cc:266:slice$17341 $auto$simplemap.cc:126:simplemap_reduce$17530 $auto$opt_expr.cc:617:replace_const_cells$324931 $auto$simplemap.cc:126:simplemap_reduce$17515 $auto$ff.cc:266:slice$17342 $auto$simplemap.cc:75:simplemap_bitop$124568 $auto$simplemap.cc:196:simplemap_lognot$17534 $auto$simplemap.cc:126:simplemap_reduce$17532 $auto$simplemap.cc:126:simplemap_reduce$17529 $auto$opt_expr.cc:617:replace_const_cells$324943 $auto$simplemap.cc:267:simplemap_mux$124563 $auto$simplemap.cc:126:simplemap_reduce$124582 $auto$simplemap.cc:126:simplemap_reduce$124579 $auto$simplemap.cc:126:simplemap_reduce$124587 $auto$simplemap.cc:126:simplemap_reduce$124584 $auto$simplemap.cc:75:simplemap_bitop$124566 $auto$simplemap.cc:267:simplemap_mux$17501 $auto$simplemap.cc:225:simplemap_logbin$17504 $auto$simplemap.cc:196:simplemap_lognot$17519 $auto$simplemap.cc:126:simplemap_reduce$17517 $auto$simplemap.cc:126:simplemap_reduce$17514 $auto$opt_expr.cc:617:replace_const_cells$325281 $auto$ff.cc:266:slice$17339 $auto$simplemap.cc:126:simplemap_reduce$21292 $auto$simplemap.cc:126:simplemap_reduce$21290 $auto$simplemap.cc:225:simplemap_logbin$17460 $auto$simplemap.cc:196:simplemap_lognot$17470 $auto$simplemap.cc:126:simplemap_reduce$17468 $auto$opt_expr.cc:617:replace_const_cells$324941 $auto$simplemap.cc:267:simplemap_mux$124564
Found an SCC: $auto$ff.cc:266:slice$17344 $auto$ff.cc:266:slice$17345 $auto$ff.cc:266:slice$17350 $auto$ff.cc:266:slice$17351 $auto$simplemap.cc:126:simplemap_reduce$17549 $auto$opt_expr.cc:617:replace_const_cells$324945 $auto$ff.cc:266:slice$17343 $auto$simplemap.cc:126:simplemap_reduce$17554 $auto$simplemap.cc:126:simplemap_reduce$17550 $auto$simplemap.cc:38:simplemap_not$124354 $auto$ff.cc:266:slice$17346 $auto$simplemap.cc:38:simplemap_not$124355 $auto$ff.cc:266:slice$17347 $auto$simplemap.cc:126:simplemap_reduce$17551 $auto$ff.cc:266:slice$17348 $auto$simplemap.cc:38:simplemap_not$124357 $auto$ff.cc:266:slice$17349 $auto$simplemap.cc:126:simplemap_reduce$21286 $auto$simplemap.cc:196:simplemap_lognot$17561 $auto$simplemap.cc:126:simplemap_reduce$17559 $auto$simplemap.cc:126:simplemap_reduce$17557 $auto$simplemap.cc:126:simplemap_reduce$17555 $auto$simplemap.cc:126:simplemap_reduce$17552 $auto$simplemap.cc:38:simplemap_not$124358
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$20988 $auto$simplemap.cc:126:simplemap_reduce$21189 $auto$simplemap.cc:38:simplemap_not$319908 $auto$ff.cc:266:slice$18343 $auto$ff.cc:479:convert_ce_over_srst$326155 $auto$simplemap.cc:126:simplemap_reduce$18531 $auto$ff.cc:266:slice$18342 $auto$ff.cc:479:convert_ce_over_srst$326153 $auto$simplemap.cc:38:simplemap_not$319906 $auto$ff.cc:266:slice$18341 $auto$ff.cc:479:convert_ce_over_srst$326151 $auto$simplemap.cc:126:simplemap_reduce$18530 $auto$ff.cc:266:slice$18340 $auto$ff.cc:479:convert_ce_over_srst$326149 $auto$ff.cc:266:slice$18339 $auto$ff.cc:479:convert_ce_over_srst$326147 $auto$simplemap.cc:38:simplemap_not$21192 $auto$alumacc.cc:485:replace_alu$6833.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$6833.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$6833.slice[0].ccu2c_i $auto$simplemap.cc:38:simplemap_not$319903 $auto$ff.cc:266:slice$18338 $auto$ff.cc:479:convert_ce_over_srst$326145 $auto$simplemap.cc:126:simplemap_reduce$20975 $auto$simplemap.cc:126:simplemap_reduce$20991 $auto$simplemap.cc:126:simplemap_reduce$20989 $auto$simplemap.cc:38:simplemap_not$21028 $auto$simplemap.cc:75:simplemap_bitop$18268 $auto$simplemap.cc:126:simplemap_reduce$18535 $auto$simplemap.cc:126:simplemap_reduce$18533 $auto$simplemap.cc:126:simplemap_reduce$18529 $auto$simplemap.cc:38:simplemap_not$319904
Found an SCC: $auto$simplemap.cc:38:simplemap_not$124600 $auto$ff.cc:266:slice$17193 $auto$simplemap.cc:126:simplemap_reduce$17321 $auto$simplemap.cc:126:simplemap_reduce$17294 $auto$ff.cc:266:slice$17194 $auto$simplemap.cc:38:simplemap_not$124602 $auto$ff.cc:266:slice$17195 $auto$simplemap.cc:126:simplemap_reduce$17326 $auto$simplemap.cc:126:simplemap_reduce$17322 $auto$simplemap.cc:126:simplemap_reduce$17299 $auto$simplemap.cc:126:simplemap_reduce$17295 $auto$simplemap.cc:38:simplemap_not$124603 $auto$ff.cc:266:slice$17196 $auto$simplemap.cc:38:simplemap_not$124604 $auto$ff.cc:266:slice$17197 $auto$simplemap.cc:126:simplemap_reduce$17323 $auto$simplemap.cc:126:simplemap_reduce$17296 $auto$simplemap.cc:38:simplemap_not$124605 $auto$ff.cc:266:slice$17198 $auto$simplemap.cc:38:simplemap_not$124606 $auto$ff.cc:266:slice$17199 $auto$simplemap.cc:126:simplemap_reduce$17302 $auto$simplemap.cc:126:simplemap_reduce$17300 $auto$simplemap.cc:126:simplemap_reduce$17297 $auto$simplemap.cc:126:simplemap_reduce$17329 $auto$simplemap.cc:126:simplemap_reduce$17327 $auto$simplemap.cc:126:simplemap_reduce$17324 $auto$simplemap.cc:38:simplemap_not$124607 $auto$ff.cc:266:slice$17200 $auto$simplemap.cc:196:simplemap_lognot$17306 $auto$simplemap.cc:126:simplemap_reduce$17304 $auto$simplemap.cc:196:simplemap_lognot$17333 $auto$simplemap.cc:126:simplemap_reduce$17331 $auto$ff.cc:266:slice$17201 $auto$simplemap.cc:167:logic_reduce$13033 $auto$simplemap.cc:225:simplemap_logbin$17278 $auto$simplemap.cc:225:simplemap_logbin$17279
Found 8 SCCs in module processorci_top.
Found 8 SCCs.

34.42.5. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.6. Executing PROC pass (convert processes to netlists).

34.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

34.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

34.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

34.42.6.4. Executing PROC_INIT pass (extract init attributes).

34.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

34.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

34.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

34.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

34.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).

34.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

34.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

34.42.6.12. Executing OPT_EXPR pass (perform const folding).

34.42.7. Executing TECHMAP pass (map to technology primitives).

34.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

34.42.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~162 debug messages>

34.42.8. Executing OPT pass (performing simple optimizations).

34.42.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

34.42.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

34.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

34.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.

34.42.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

34.42.8.6. Executing OPT_DFF pass (perform DFF optimizations).

34.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..

34.42.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

34.42.8.9. Finished OPT passes. (There is nothing left to do.)

34.42.9. Executing TECHMAP pass (map to technology primitives).

34.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

34.42.9.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1061 debug messages>

34.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

34.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

34.42.12. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.13. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

34.42.14. Executing TECHMAP pass (map to technology primitives).

34.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v
Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

34.42.14.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~201 debug messages>

34.42.15. Executing OPT pass (performing simple optimizations).

34.42.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

34.42.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

34.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

34.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.42.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.42.15.6. Executing OPT_DFF pass (perform DFF optimizations).

34.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

34.42.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.42.15.9. Rerunning OPT passes. (Maybe there is more to do..)

34.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

34.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

34.42.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

34.42.15.13. Executing OPT_DFF pass (perform DFF optimizations).

34.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

34.42.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

34.42.15.16. Finished OPT passes. (There is nothing left to do.)

34.42.16. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

34.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 38496 cells with 250207 new cells, skipped 14727 cells.
  replaced 4 cell types:
    6339 $_OR_
     475 $_XOR_
      62 $_ORNOT_
   31620 $_MUX_
  not replaced 10 cell types:
      32 $scopeinfo
    2815 $_NOT_
    4860 $_AND_
    4287 TRELLIS_FF
       1 DP16KD
       4 MULT18X18D
     611 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
    1058 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
    1058 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER

34.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9).

34.42.17.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 107546 AND gates and 275596 wires from module `processorci_top' to a netlist network with 8694 inputs and 3742 outputs.

34.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9).

34.42.17.5. Executing ABC9.
Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   8694/   3742  and =   74144  lev =   59 (4.96)  mem = 1.34 MB  box = 1669  bb = 1058
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   8694/   3742  and =   91110  lev =   63 (4.16)  mem = 1.53 MB  ch =11616  box = 1601  bb = 1058
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   91110.  Ch =  9697.  Total mem =   19.20 MB. Peak cut mem =    0.35 MB.
ABC: P:  Del = 8682.00.  Ar =   84550.0.  Edge =    93278.  Cut =  1117215.  T =     0.50 sec
ABC: P:  Del = 8534.00.  Ar =   79943.0.  Edge =    87485.  Cut =  1076717.  T =     0.51 sec
ABC: P:  Del = 8534.00.  Ar =   23683.0.  Edge =    71917.  Cut =  2151557.  T =     0.91 sec
ABC: F:  Del = 8533.00.  Ar =   21463.0.  Edge =    68877.  Cut =  1926168.  T =     0.82 sec
ABC: A:  Del = 8533.00.  Ar =   19737.0.  Edge =    63167.  Cut =  1964457.  T =     1.36 sec
ABC: A:  Del = 8533.00.  Ar =   19563.0.  Edge =    62931.  Cut =  2013604.  T =     1.35 sec
ABC: Total time =     5.48 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   8694/   3742  and =   55170  lev =   52 (4.67)  mem = 1.11 MB  box = 1599  bb = 1058
ABC: Mapping (K=7)  :  lut =  16046  edge =   61143  lev =   17 (1.90)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   52  mem = 0.69 MB
ABC: LUT = 16046 : 2=1030 6.4 %  3=3786 23.6 %  4=8772 54.7 %  5=2227 13.9 %  6=115 0.7 %  7=116 0.7 %  Ave = 3.81
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 102.59 seconds, total: 102.59 seconds

34.42.17.6. Executing AIGER frontend.
<suppressed ~24954 debug messages>
Removed 82634 unused cells and 120810 unused wires.

34.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:    16064
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      541
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1058
ABC RESULTS:           input signals:     1256
ABC RESULTS:          output signals:      489
Removing temp directory.

34.42.18. Executing TECHMAP pass (map to technology primitives).

34.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v
Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

34.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001010 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2677 debug messages>
Removed 1659 unused cells and 289331 unused wires.

34.43. Executing TECHMAP pass (map to technology primitives).

34.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

34.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod$af0aef944d67a9554c024ff6bd1455131ab9766d\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$330dd9c7d92f1df9719e00be5c8873252663a1de\$lut for cells of type $lut.
Using template $paramod$c4a4cf1f67c598049dd5cb5cdb183838e000e772\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$0c0ecd52ddc4062e855792f313b58212abf7867f\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$c685a6e5e211287be351ac5f1078c1501564ce89\$lut for cells of type $lut.
Using template $paramod$28c616faf5f033f157ae11b466e19ab28d454f1e\$lut for cells of type $lut.
Using template $paramod$51f16771a212f7d7927f95aa192faa6dc8222898\$lut for cells of type $lut.
Using template $paramod$d345781bc5d014060901f9e4c645b8d136f2a9c6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut.
Using template $paramod$8d58c55d26490b5a99a369b5eb692d6122da9b60\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$752c9bd575908fd3e677df62693237233e307757\$lut for cells of type $lut.
Using template $paramod$2e37a29808ea9d028852cbc67bbcbc7bc127b77a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$8d08395e9a4e4cded27c9198dd6b7fb30a5dc6be\$lut for cells of type $lut.
Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$369624b024132c6d54ca5ca0dec0683515f4f203\$lut for cells of type $lut.
Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut.
Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut.
Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$098e58216a69950f0886b9f52f31a2a03d30183d\$lut for cells of type $lut.
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut.
Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut.
Using template $paramod$38446ff493f776d29ea4f3122b249720a55b03df\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$fc6feb7ca0813ec6f9a6e104d2344b22630ad56a\$lut for cells of type $lut.
Using template $paramod$5b5755730b9a53f6c50cca29ba2f99d7e0bc0fe6\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut.
Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut.
Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$bac9d46c0d1e778167fa8869abb1a0d9da802241\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$df23d368a6ae8908771963811f5ab56f622887ca\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod$e84e4a245515000cd6930e0f4535753ed485f71e\$lut for cells of type $lut.
Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut.
Using template $paramod$9c10e17a0a1ecd0e2664d222f0eb0cb2cf52c224\$lut for cells of type $lut.
Using template $paramod$a9f1133a3906e1a228933cdcaf464c776493a7e0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$6230360d3448cb863f2f259c28a1234ced7c698b\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut.
Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut.
Using template $paramod$2ca5a8bf2a853a223fe0e0148e443d1b7e1e37b1\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$122a4c0b007fa7ed75dbda7c4d71a52e22ce1276\$lut for cells of type $lut.
Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut.
Using template $paramod$9a582b26ac72558b4b8d34b9fac10efff27334ce\$lut for cells of type $lut.
Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut.
Using template $paramod$05dd5d01546eff9da45f32c923ffbe0f9afdb118\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$4a79e420bd8f8531fae065eb0f1448636a88dd22\$lut for cells of type $lut.
Using template $paramod$ae08c76a6a700543e8cbf77158f5cdb4e9c14400\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$a0219a10af5eeac70b87184a9a0bdd503910b00e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110110 for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$2102ed4cb87db815bd09dfb94e3ad0dc634acb70\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$581d7e5f451b6b3ddd4ad06c99f094a0a6e88e05\$lut for cells of type $lut.
Using template $paramod$893407dabd938ffd31ac8ddbe04cd1bb7b4d8909\$lut for cells of type $lut.
Using template $paramod$f7dbfcc55e1e06abee68b5aa3b6d8da06b763680\$lut for cells of type $lut.
Using template $paramod$29fb0dcbea7e19908c494ce4a8a756b15e2a78b6\$lut for cells of type $lut.
Using template $paramod$c9de912174387ef4b962cc6531eba6d7223348cd\$lut for cells of type $lut.
Using template $paramod$4fe5cdb13da5e1298983f8531c96681a078669af\$lut for cells of type $lut.
Using template $paramod$089f979e3ab2db3494780ce4eaba44acbbede03c\$lut for cells of type $lut.
Using template $paramod$652a95a3df5bdea5c71823d14909e72afa195345\$lut for cells of type $lut.
Using template $paramod$5f892cbccc8e0b846db30004f6a576906c92120c\$lut for cells of type $lut.
Using template $paramod$3b35bafdc9ca1ba7b58af3a2c3754255c8d3e8ea\$lut for cells of type $lut.
Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3\$lut for cells of type $lut.
Using template $paramod$dd9bc70275ecbea3b768554c6cbcd2e59eee4b79\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$6e4742bd4751476544881cca69fb5f022ade86b4\$lut for cells of type $lut.
Using template $paramod$044fed7600db3b2163ef68752b2e3f461bdc101e\$lut for cells of type $lut.
Using template $paramod$ebcbbdbec81431c529d818d79260668712396912\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$74c86188be82ef6de23ceaa53763cdce7c4b3ae3\$lut for cells of type $lut.
Using template $paramod$e053a22d78e6bd5ea33183ea69976f0db741be0e\$lut for cells of type $lut.
Using template $paramod$db738be77b96326a46ff06b19713ffc9bc25345a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$7d43acc88b2d3af3bac64100bfe6b3c077318ca5\$lut for cells of type $lut.
Using template $paramod$02313b2bb70d4d75eb570d6a718a7e71c886406a\$lut for cells of type $lut.
Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$71f530e8a7f4f89f2e3e5502a552426c66ceedaa\$lut for cells of type $lut.
Using template $paramod$0111dbc434199eb6d3f89c35652f1a8ca1df6734\$lut for cells of type $lut.
Using template $paramod$741ad739db97fb463e1be510a8ffdd2aad407ee0\$lut for cells of type $lut.
Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut.
Using template $paramod$8c2e098a78289c69a367bf606e2b1e99c9632637\$lut for cells of type $lut.
Using template $paramod$8c768e4a7e55bf0f8f506bb1b977e7f2dabb8711\$lut for cells of type $lut.
Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$6410b45ea4d1e53d7fd209ee0400ef5c9579c44a\$lut for cells of type $lut.
Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut.
Using template $paramod$0167b96a3321f225cf98b602e01abe2c8c6b04db\$lut for cells of type $lut.
Using template $paramod$3b7f7f3d85a1c341eb9bb72b457d31acefe503a5\$lut for cells of type $lut.
Using template $paramod$d26ed00b2888b377817a70e6ee01acb2811dbe36\$lut for cells of type $lut.
Using template $paramod$446222f3dee8c3b7af8178fba7628b2ee4b2e06d\$lut for cells of type $lut.
Using template $paramod$2053b0e582848dc98d20957945f6f5c1a329eb94\$lut for cells of type $lut.
Using template $paramod$05335e4b81c06aae487cba659b8360e70d797ebd\$lut for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut.
Using template $paramod$44f6f0c0bfe5b6d2a869195ab8d9a5463325cd31\$lut for cells of type $lut.
Using template $paramod$173802ab957d7f811e3c628a17c2d9ac77692ecd\$lut for cells of type $lut.
Using template $paramod$300b4156df89d6d360300165092a53a286e44fe3\$lut for cells of type $lut.
Using template $paramod$96f140829851467619d89188afb45950040f759f\$lut for cells of type $lut.
Using template $paramod$92054f5a87b8b0114ce1e9dfe4f8e9981cb594ac\$lut for cells of type $lut.
Using template $paramod$38da530960c8d0872f5145bbed29e6bd1de68578\$lut for cells of type $lut.
Using template $paramod$f917a8682f0563203cb37487ea970fda1e894b57\$lut for cells of type $lut.
Using template $paramod$77a79c63321da6f25f9b54063a156fd8ed6af952\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$68e3d3f27e6a41c3bf8782ac6aac602773fca3a6\$lut for cells of type $lut.
Using template $paramod$ccde76a25d45898fe76c71e1ef39711e4da740d9\$lut for cells of type $lut.
Using template $paramod$13308b33e30958a96c5bd985d89aca002a667b23\$lut for cells of type $lut.
Using template $paramod$ee553c574ab2f916d3d8d85eaa3629c01709dc3a\$lut for cells of type $lut.
Using template $paramod$9bb69212f68eb2322f7034adb2fd5b49105d0731\$lut for cells of type $lut.
Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut.
Using template $paramod$c3ca34967d7c6ceae947cfaf7c86f28b195924ef\$lut for cells of type $lut.
Using template $paramod$87fe10ddefa00c8b9613e531da70ebc094660b4f\$lut for cells of type $lut.
Using template $paramod$0078c17b096f74a77cf0310952a25e63cbe784ab\$lut for cells of type $lut.
Using template $paramod$257473e5980137599292bae6ba74115aa46b4110\$lut for cells of type $lut.
Using template $paramod$3bb8e51772cd4d22a92a009951c65bf250f88205\$lut for cells of type $lut.
Using template $paramod$c039f15592dbb863a55cd28cd138649990f0aecd\$lut for cells of type $lut.
Using template $paramod$4b29e093b16c368d23b70f9bc7b1816a2013d17c\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$ffbe6e0b4b34baf782107e93a76b08232b8000aa\$lut for cells of type $lut.
Using template $paramod$7a7f5fec48b30e55a9cd689c3b5678806eecd2d8\$lut for cells of type $lut.
Using template $paramod$23627d32cba37e137237b06f0d69d84dab1144d4\$lut for cells of type $lut.
Using template $paramod$23076c663d864c28a788d30528ce53eedf05c00b\$lut for cells of type $lut.
Using template $paramod$01c4c6d1e72abd0e1539d338129ac5a71456d511\$lut for cells of type $lut.
Using template $paramod$b10a0454c1882cb425bbae3ce8cbf2c1102bac86\$lut for cells of type $lut.
Using template $paramod$4957e9c58c5105ad4f54ddfa259af5cd00cdfbae\$lut for cells of type $lut.
Using template $paramod$b7fc6a704325d84d0daa9dc8053cd48cc006f33b\$lut for cells of type $lut.
Using template $paramod$c554b816101be4e9401218de04230036e0b14c79\$lut for cells of type $lut.
Using template $paramod$2646f79d883fe55c6115f3a5c1d9911a69497523\$lut for cells of type $lut.
Using template $paramod$a7853c26ee21262b981ae0d0b74778bb403c5822\$lut for cells of type $lut.
Using template $paramod$4a9e1df3d2a1e9079d9dc827db9adf434288295b\$lut for cells of type $lut.
Using template $paramod$ad84e3bf55beb81929dddc0ffa380a3da019a547\$lut for cells of type $lut.
Using template $paramod$62780deb435554f4f8c3853e6f5f208d511b13b6\$lut for cells of type $lut.
Using template $paramod$8c9ed9fba3f07703e29935d8f4ba7b338dca5a38\$lut for cells of type $lut.
Using template $paramod$a1c41e46db5390caa8977688625aa5961e09128a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$e67f7401ddeed7957ea40cf37767a32ba5d5b941\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$c820aa2e2b10212aad9cb4abecfacc6013111bf8\$lut for cells of type $lut.
Using template $paramod$129f5b55fa9a45614df91b4a79acd963ccf442b9\$lut for cells of type $lut.
Using template $paramod$02a39d6f75416c06fff45fc81145d64144c93f5a\$lut for cells of type $lut.
Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut.
Using template $paramod$7f937f9b61bf542e3f85320ab27ebb3043b4337a\$lut for cells of type $lut.
Using template $paramod$5013e270f714f338bf0fdc4d451356213fab99c0\$lut for cells of type $lut.
Using template $paramod$41d6a8c714869a8ddb8bb83b5428ad46b4d2fcaa\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$de3406006c16cf7256a0a2fdcbb1597ad8f6cb54\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$ef3c091323a84a78d729201d2e6359e2b30ccdb8\$lut for cells of type $lut.
Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$393bbb957de1d0a6ac3c2a3b907b576687a877d0\$lut for cells of type $lut.
Using template $paramod$84e807d4502b6c6d3d6bf2798990113ee5b6befd\$lut for cells of type $lut.
Using template $paramod$2bcdd3da3eac10ee801d52b1dd05f904e5b14ade\$lut for cells of type $lut.
Using template $paramod$b7dbf2fba227f160b8e48e786b5c59ef3fbd5aae\$lut for cells of type $lut.
Using template $paramod$6bf2caa40fb1acb49d1a3518d072e0f81faf3832\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$24e83bd24b403ddd5d396288e207d4e90f80fe39\$lut for cells of type $lut.
Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut.
Using template $paramod$2962f979358b8c59f7d908c222c6d1fad7aeea7e\$lut for cells of type $lut.
Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut.
Using template $paramod$903b13a78e0201d81ee2cb5e579e213337de2eac\$lut for cells of type $lut.
Using template $paramod$16dffbf1bc428a4f5ab58c9b78f55317f92370a5\$lut for cells of type $lut.
Using template $paramod$7a7c5a90414cad5cf0940d4ec13ac6166bf454b1\$lut for cells of type $lut.
Using template $paramod$4608da9fd023edc9f354f403fba66f5b785d6c89\$lut for cells of type $lut.
Using template $paramod$20348009456f6262c437b95109d10c006bbc3f3a\$lut for cells of type $lut.
Using template $paramod$ef2ddc9df01a1477faf1b226059e38ddbe6f3128\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut.
Using template $paramod$97f2cbbe0ad85c6a16593a8c6400e74d6f24e13d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$ebcf3c34b3486471560dfa367ec9f1b53ac14e98\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$4b7c18f90e1cab5b546dd47c402b06c129eed7f0\$lut for cells of type $lut.
Using template $paramod$a6ef2a845efd4ff0d96bc4fd2f06cc3516fa63ff\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$6cded6c61ce853ef2739b0e8efd438c7483cfea8\$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut.
Using template $paramod$537a837d28776a52b26098cc00fc838432c2049e\$lut for cells of type $lut.
Using template $paramod$98b9252561d29ef0a4ae9aea7551cce630cb979c\$lut for cells of type $lut.
Using template $paramod$cf5e582f715e5fb2d4513be72acb1692e82fca7a\$lut for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$1bf8d554d4a0166389d05355c46b5d67de798aa0\$lut for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$57d47653e6c4c78960c950de584d722d27d5de32\$lut for cells of type $lut.
Using template $paramod$115f7914ea7f275f68a38ef9bb547f387fcc044c\$lut for cells of type $lut.
Using template $paramod$0e0591ac27b6559d44b4716b35daaa57c6cc835e\$lut for cells of type $lut.
Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut.
Using template $paramod$53aa4ed694a318d1c953f64ce655f506530d6819\$lut for cells of type $lut.
Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$6608a65352d2f37ee214f81832cafa7a0d73ae55\$lut for cells of type $lut.
Using template $paramod$8207a4b4445604513c8d809c61f5081fdab92b58\$lut for cells of type $lut.
Using template $paramod$d4294245ac8ca459236d150b7f63b89fc0b734d5\$lut for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$37a2d863c34304020b657b2b0f14ddd4970cc24b\$lut for cells of type $lut.
Using template $paramod$ef2b41d13ee27e6181d7c1b04a9d128947b5a51c\$lut for cells of type $lut.
Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut.
Using template $paramod$187b265af118a45b7880d2dcc0524ee2abd6b591\$lut for cells of type $lut.
Using template $paramod$8915f24fcc45a3744fe14e4ac7411030ea0a9166\$lut for cells of type $lut.
Using template $paramod$f541431bf9bbcc71613860d1c85b05be39d75713\$lut for cells of type $lut.
Using template $paramod$f55d059d9e1d4d8fd6a5fb9c5424b52601b9b180\$lut for cells of type $lut.
Using template $paramod$b99f725187fd5b9fa8dfc1981d71d75927693e63\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut.
Using template $paramod$0189d933eed523b159b35d60915e80e53d803bc2\$lut for cells of type $lut.
Using template $paramod$bda5da73d01b4db0d2bc78be1e1b907c2cbe57e9\$lut for cells of type $lut.
Using template $paramod$8384c297ba29b8fe3856727600bfc1032bea85e7\$lut for cells of type $lut.
Using template $paramod$99ddbb4ae9fdbb3bcca2b92cc87638c0452b9d23\$lut for cells of type $lut.
Using template $paramod$637ac5c2c69ffd8a64a79cbecb7e87ac59219f4a\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$9c082446b4bd60df488d54bc39e652bcf1737c4d\$lut for cells of type $lut.
Using template $paramod$1863ef99a7b42c1f89232d279c01998dce9847a6\$lut for cells of type $lut.
Using template $paramod$338e4671a66ebe496ca98da8cd02639ec4954438\$lut for cells of type $lut.
Using template $paramod$46a64e40864a1f47f66c52ab5959b931c09ae0c4\$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$b7f2af3b894343554c22993fa7e7d9f6371a085d\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$1df48f0121e497a123a899ea4a1c38118002c0b9\$lut for cells of type $lut.
Using template $paramod$ce6da8dfe4fa17b5e2f351d83465ac2f02211d78\$lut for cells of type $lut.
Using template $paramod$234997bee759301806c8ada31f0c044884c8f8c5\$lut for cells of type $lut.
Using template $paramod$9841ff00c05ef2b91f1dc1e16a5a17a672c76a9c\$lut for cells of type $lut.
Using template $paramod$d5d73cc1e6e41882e5bf159d1175c2b58667f907\$lut for cells of type $lut.
Using template $paramod$1e021503cfc34904848d17b6108e08af981b1d38\$lut for cells of type $lut.
Using template $paramod$ea23d774dd8e0dbff9bfd3858dc21c63b79d5ee4\$lut for cells of type $lut.
Using template $paramod$16ffe7b575e8a1012cd37846538ebde136a9a658\$lut for cells of type $lut.
Using template $paramod$de75d8ed1435cf2804ac8d6108bb0f23af706d83\$lut for cells of type $lut.
Using template $paramod$daaef74e20efd051e05033f395447181e087130f\$lut for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut.
Using template $paramod$093c8c8d3647d81039c4d7bf96f95107d574803e\$lut for cells of type $lut.
Using template $paramod$e95b62b20e79839d7e3e0602943589b12cde6927\$lut for cells of type $lut.
Using template $paramod$cf7f3a0cbef28573cfdd7218ef90ef5391ec0286\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$d61ab9a5a1d723fc5de4be7b38a6f1747f5b34ac\$lut for cells of type $lut.
Using template $paramod$8c0397d1e1abb1d2c8901012d8a8856df58839a8\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$1f9991b7d220a1444c81118371531284fe6401b3\$lut for cells of type $lut.
Using template $paramod$ff31ee3bd1d6cb4165e454f957c1472ec9abff7f\$lut for cells of type $lut.
Using template $paramod$ed49ac630ee8b054c4deb19667be9e8a11947f4d\$lut for cells of type $lut.
Using template $paramod$817a98ab8490f29d36e133ba921aed43b5e13159\$lut for cells of type $lut.
Using template $paramod$0ad65018a9b921b3b2ff4aff999a4c0fe8d258b3\$lut for cells of type $lut.
Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099\$lut for cells of type $lut.
Using template $paramod$adf4c2fabfa4eccdd812c3b43f59b813b1c6dd04\$lut for cells of type $lut.
Using template $paramod$d59b794362302cacda9a6e63c8aaca360cb232b6\$lut for cells of type $lut.
Using template $paramod$a118e8e194e33b05fe662e3d52c7a58937ef28fb\$lut for cells of type $lut.
Using template $paramod$21dec4a24e911a45480eba2c0d9ab23d777a7412\$lut for cells of type $lut.
Using template $paramod$63208c79a704f7b48158ac5ca25f0cc7404cc096\$lut for cells of type $lut.
Using template $paramod$2e473764f25e8a69de1395443a083eff1424afeb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$74cfa2de6455b42621640696be65d1d379a71ace\$lut for cells of type $lut.
Using template $paramod$4bd4d1a8a9e346a94507f65b9c1ebde03fcad485\$lut for cells of type $lut.
Using template $paramod$50893e0cd69869d18d41a6546e39535356efda03\$lut for cells of type $lut.
Using template $paramod$72a2d84d8470cf23e95759e82ce3fd5464b62d58\$lut for cells of type $lut.
Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut.
Using template $paramod$bbf8c65f00b09f2cf68e6ca5410fa9a0c7a5e2b9\$lut for cells of type $lut.
Using template $paramod$828096678386a4453f064d41cbed89443fa1b5d0\$lut for cells of type $lut.
Using template $paramod$1046bb5e1eafd4bf6fbd80cc25d0e121a2c9b305\$lut for cells of type $lut.
Using template $paramod$6f7b605ac89b2ef500058a0f5d207a3c3f2a658f\$lut for cells of type $lut.
Using template $paramod$9b7de4abb86ac782adfda2986e0734ca5f3df82c\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$078db3dcdab00c5525715fc651615331bbb90453\$lut for cells of type $lut.
Using template $paramod$fba2e4f6f8ab1bc181fa350d2e7f12d4e9c80f0b\$lut for cells of type $lut.
Using template $paramod$8fec025799f9cb7afca8156c4b47621e5d893096\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$8adcaf95747d2763e8a475141a0035cf7f7001e3\$lut for cells of type $lut.
Using template $paramod$eaddf175cbf0f357c5cc21e4dcb779376e653604\$lut for cells of type $lut.
Using template $paramod$047b364b84986f7d93317724da6587455a4e32a0\$lut for cells of type $lut.
Using template $paramod$ca91fcc5cbe768e2d7255c839b7e358fd54801a6\$lut for cells of type $lut.
Using template $paramod$880afb6ea6b01db2467b31e5b8b3c0a9fc8686cf\$lut for cells of type $lut.
Using template $paramod$e2b8f307f1ffa901c3750272cd6a9874d41797ba\$lut for cells of type $lut.
Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut.
Using template $paramod$6b41b673dd4ac8b57e9a6f6475a3ea1fbb78cf57\$lut for cells of type $lut.
Using template $paramod$a459b16dcd826488597b4205162069de1339cf59\$lut for cells of type $lut.
Using template $paramod$3e5166dee1c1f724dd65d0dea3d36a709d245c2c\$lut for cells of type $lut.
Using template $paramod$97892369518ba7fede925f60d22d778182ae2c81\$lut for cells of type $lut.
Using template $paramod$e14c6fb4ef898346777977169cf1b7b0d32573fe\$lut for cells of type $lut.
Using template $paramod$a466678992feb44cf6749703c13a9fa3f3b5c308\$lut for cells of type $lut.
Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd\$lut for cells of type $lut.
Using template $paramod$7a290f589267b1934181d1524aa904d900fe5b82\$lut for cells of type $lut.
Using template $paramod$80d3931447d1225a7aaed055bf09f9b46864761f\$lut for cells of type $lut.
Using template $paramod$1d93d254734faf72793095bf626729d2bcb71864\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$5ecaf6479f57a9e87686643f7fc2c39ce674fa67\$lut for cells of type $lut.
Using template $paramod$aca5e0f9d547a0d0afa69307c25a36d29ff93905\$lut for cells of type $lut.
Using template $paramod$68503246eec490da7833ea943f43dc893d866f3c\$lut for cells of type $lut.
Using template $paramod$bfff1ab93e379807aa95f1a46e310365341de420\$lut for cells of type $lut.
Using template $paramod$35e41d587148a85b6f12b548bc5f21792836ed54\$lut for cells of type $lut.
Using template $paramod$161db7d99c6a25759d6bd139ac266d3ebfeac53f\$lut for cells of type $lut.
Using template $paramod$b2e0825f64bd811a61934a72f5cb6d10453c43c9\$lut for cells of type $lut.
Using template $paramod$db7b02fddf4cc0b2c6b5c015ae0c3732b51555f7\$lut for cells of type $lut.
Using template $paramod$2caa93f46c19de99b945084ea50c97ca1398f154\$lut for cells of type $lut.
Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut.
Using template $paramod$c153fdf016e44aed0c29389a7a6afff27dca56b6\$lut for cells of type $lut.
Using template $paramod$507a2a372a6e003d4d949a6f61d5e2bf633425ee\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut.
Using template $paramod$04aadee43c61819341dbe5dac3b039fe0b77a47a\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$e21ab7140f5d70efd4439745db2467fa93905bb6\$lut for cells of type $lut.
Using template $paramod$80a3ad83b0cc21585fc9f61ce42c3a6c3efdaed2\$lut for cells of type $lut.
Using template $paramod$5d0e000c0a65cfa117102d87fcbd8f83684d30fd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut.
Using template $paramod$115b33a94acd0d35393b7ffd17f6f80c031f9c76\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$907f2d2c02ff149f00785eb99b3e2aa8a6a3fccd\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$b053538fb4536514881298fa3d5e86574e44ce4e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut.
Using template $paramod$3d15019bc3c3947166ac5e931ccd6987f738b3ad\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$bf63ab7ae4814dd738f4846eb5db47ed1afec133\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$8c0aa4283e004d7e549a2fa42300002224408629\$lut for cells of type $lut.
Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut.
Using template $paramod$33f2f726aae9e51eca08731f9b4f3a6eef20561c\$lut for cells of type $lut.
Using template $paramod$9accec461bdf9de30d8ae592852e822e78be8a49\$lut for cells of type $lut.
Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$9049397e8df8108adcf55f7aeecd1b2fb9b498f6\$lut for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$acd2aac62f6cac8eccb6441cdd9fcd1a9733ebff\$lut for cells of type $lut.
Using template $paramod$a2f201d984e8bd96c8e0db17337de5e27f0661cc\$lut for cells of type $lut.
Using template $paramod$f6dc5effae5c2b2fa74fb9734eb02ac8c26dc87d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$0d6e5085e7f484e8afccaf843a26899272d0f476\$lut for cells of type $lut.
Using template $paramod$6dc05f9f044ab30f5362b0c302f3cf6295cf2d76\$lut for cells of type $lut.
Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut.
Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$f3a867ad1463836a851adbf533d541186295e26c\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$a73e5affe093cbfcf0d2b43eb8fbeac4ea474b24\$lut for cells of type $lut.
Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut.
Using template $paramod$edfe6773e2ae95f1f17ad5bea62c0e1b079fa667\$lut for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$5f62258baf8e9e81bbe6ab71cd1b06a1c2737273\$lut for cells of type $lut.
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut.
Using template $paramod$b3082da6730e6e1ffbfd0ceff231671d1527fc50\$lut for cells of type $lut.
Using template $paramod$acbd127fa51bf3b670888e0e6dbc97acbf4541bb\$lut for cells of type $lut.
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut.
Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut.
Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut.
Using template $paramod$9e45b1a8f5d89c07bcbb75a2bb1c598231b04feb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$2d8ecce5c907513cebcd38ab5efe0fc26fc03464\$lut for cells of type $lut.
Using template $paramod$422612419457332f7f31a22e29b30432ffb427bf\$lut for cells of type $lut.
Using template $paramod$bf80ab5b82bc1c590371914612ed4ab80a2743a3\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod$2694fda3f2b652c6e191caaf34470870453c3027\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$22a17f102d8eb29f9e3f67afc5da9acc7c1e8867\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$8d8a6111e2a82db0bfbd78666fa69c753d8df004\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$91e303dedaa4dcc5053a2b80ff2dab844bbf2f3d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut.
Using template $paramod$03a9885a61e46980831d2c64059eb66aa27bbfee\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut.
Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578\$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$3b383aa74b05b60cb9cabc0ba0eca4dea92c2b33\$lut for cells of type $lut.
Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188\$lut for cells of type $lut.
Using template $paramod$af0c0e3aea5daa768aac0697b02a2a49301800b1\$lut for cells of type $lut.
Using template $paramod$eaacf9809ed87d6f801a5466f6f5f3d660730e88\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d\$lut for cells of type $lut.
Using template $paramod$d0f8e9e00b83cb69742e69fe894a4d457c015e6a\$lut for cells of type $lut.
Using template $paramod$549a24c0b77071744eefd28bf11342e15d6bc181\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$c35492cebda5b908d10e5976bd14d50fda8ce5fd\$lut for cells of type $lut.
Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut.
Using template $paramod$b04f0510561c4bbb703d2e39c6eca682b920366b\$lut for cells of type $lut.
Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut.
Using template $paramod$b59ffb63b9b7df8891d116cef9a15779c52f9b13\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut.
Using template $paramod$7c8b40752437e9e76109be15d5be0b4e21964ab2\$lut for cells of type $lut.
Using template $paramod$07d604fa63557df73201af3ab3c9bef4e6969c47\$lut for cells of type $lut.
Using template $paramod$4045162732ff1ef3063f7c74bcf446c45645f6c6\$lut for cells of type $lut.
Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$822322c7e12c4d18249679c55eeb859fc9b9edc0\$lut for cells of type $lut.
Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut.
Using template $paramod$a5d5c745abad930299600272e8260a256cf53240\$lut for cells of type $lut.
Using template $paramod$20aecb9a781743d0e93608b1c1e7d62ffc3a69a9\$lut for cells of type $lut.
Using template $paramod$24c1f285a7007833594bc4fc8c3ab552b1afa454\$lut for cells of type $lut.
Using template $paramod$1fa8c4b1c3dd435bf16a82b5a7b9def186b8a7b3\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$3eb61a9b4835399f9e41942bc9767d04b8dcbe31\$lut for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod$be39c13f160673fb03a90fe22c20fa04224ea98f\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$71b9c40f96279e3a116252ec42d3ff82239d4987\$lut for cells of type $lut.
Using template $paramod$0392318cefd9d15f572622bd5a88290120220d9c\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut.
Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut.
Using template $paramod$a47ab8a9401965088c690edab226b5e61dd268e6\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$0c0f0cd424efc67e0089008c016ea0898b7d1e0b\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$c11ee6bbb8d9fd9cf391261624c378fb45e86b84\$lut for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$9931195a70e7ddc2c5c6492070dc0179c0aedf40\$lut for cells of type $lut.
Using template $paramod$592cec9bca2c3cc6c9687a1a8cdd6cc2f3621ab1\$lut for cells of type $lut.
Using template $paramod$cc88270836ca29009a83d7e3eaf54afc4b29bf0a\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$fa874836ac64420bb7d9c67e99a0912e16a50ef2\$lut for cells of type $lut.
Using template $paramod$eeea089431e54644147af2c573dc3d2eca0e3b09\$lut for cells of type $lut.
Using template $paramod$a467e3aee4b54a60cdec89714694957109e0405d\$lut for cells of type $lut.
Using template $paramod$a7dd70936723fbbb030dc58d6d27b34fca6928ee\$lut for cells of type $lut.
Using template $paramod$cd9c6569d01df8505e03a274d799be758732d8c1\$lut for cells of type $lut.
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut.
Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut.
Using template $paramod$96b3fba966a5e5f87276372f1b4baba918f20c71\$lut for cells of type $lut.
Using template $paramod$0b2a8d00c264985361ea46953ae43c6ff5fdf81a\$lut for cells of type $lut.
Using template $paramod$7e0ce8cb9c99c4151243b3c915874937f2dbcb46\$lut for cells of type $lut.
Using template $paramod$286ed3273cbe066b6afe10d043ec3b66405aa78e\$lut for cells of type $lut.
Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$8b81775fb73b10ccf3a57c39fc26126ef8a47ddb\$lut for cells of type $lut.
Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027\$lut for cells of type $lut.
Using template $paramod$ac183dd2522ef84ecc4f0b888214bf15bff13200\$lut for cells of type $lut.
Using template $paramod$6440cc58e136932fbe77de91e89368779ff7efec\$lut for cells of type $lut.
Using template $paramod$6ba68ce1bbaa7f9811ae95eeee8480e7f91276be\$lut for cells of type $lut.
Using template $paramod$67ed851dcd4a972c20f6ecfb6a1f8766cd1ed285\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut.
Using template $paramod$1780bd352ec1af971e2f8a4e64b861091a94595b\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36\$lut for cells of type $lut.
Using template $paramod$19e5b38cca183d8b6b3a15d20dc995c09cd71893\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$493190373199e5a39be045ba23abb29ecef89037\$lut for cells of type $lut.
Using template $paramod$46a832bac987dab0247c275f3cf9ef7599bdf9cc\$lut for cells of type $lut.
Using template $paramod$4bd488bb9e7b92f6843c86d97a879ddbc9bac2f8\$lut for cells of type $lut.
Using template $paramod$b2d730f0e0e6f4705e2c703185c15ea64db0f32f\$lut for cells of type $lut.
Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0\$lut for cells of type $lut.
Using template $paramod$03da3dcc7c75ea9c9148a6fc634f76a9d0cbefef\$lut for cells of type $lut.
Using template $paramod$e124096bf99861d60006bf856be698efb41be3c3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut.
Using template $paramod$d0a46f8637b2b026d480bf9e8554ef5d086fd1d1\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod$1c7d8014a4d7918ee35a20538945662d20569ae6\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod$1ebb6b019fe9509d51860d40d0a48b52671ad12b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut.
Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut.
Using template $paramod$a7be344af0979c41b8930051bf1455c2976339f4\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut.
Using template $paramod$964dd3bb74caaeb47247bf4769459daf8ef427dd\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$a88d6a8ce8fd5d33cd3a669ac5bea735659071b9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut.
Using template $paramod$74a12c4d30e035eeda2d34c53b77373f2b2df37a\$lut for cells of type $lut.
Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e\$lut for cells of type $lut.
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut.
Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2\$lut for cells of type $lut.
Using template $paramod$6deead41a97e885fdfb7651ed7486bc07c319d2a\$lut for cells of type $lut.
Using template $paramod$e2c4569c82266091e46f75e0949ed929858f6bd1\$lut for cells of type $lut.
Using template $paramod$703e4c49c33d516152d6067070070c0f3df8148b\$lut for cells of type $lut.
Using template $paramod$5e7f29004533a83f5f084f62af5d9c64e3eff358\$lut for cells of type $lut.
Using template $paramod$968bbcc64da0b510b4577f17a4a470793a3617e9\$lut for cells of type $lut.
Using template $paramod$d8021370f0670d331038a0473505efae4dff2706\$lut for cells of type $lut.
Using template $paramod$1928c37415183f54e16ed3f8e433e2db5e63c48d\$lut for cells of type $lut.
Using template $paramod$2ad0d88c7f03b97b4d8246284ceaeaea834426d6\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
Using template $paramod$f0773b2e1ec54f4b5730a332b99958a07b433091\$lut for cells of type $lut.
Using template $paramod$9fcf2314b06bf8475a41a06506d87acad1afbbaf\$lut for cells of type $lut.
Using template $paramod$810e0f22d547104f8208898922f6ac2444aeece7\$lut for cells of type $lut.
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$dbbe0ea5aadf61e5da6ebbf1f47442d5facdca4e\$lut for cells of type $lut.
Using template $paramod$d50aaf7bc91b84437dde85e30486261cdbeeccac\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut.
Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111100 for cells of type $lut.
Using template $paramod$aa79b66d99645f2c6597509fe375a3cb97da6e36\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod$fd6824f8854c4a2d37f966378af417ea1c277d6a\$lut for cells of type $lut.
Using template $paramod$ba07846b1e706d3eb2010a528b0f0417e3645924\$lut for cells of type $lut.
Using template $paramod$4d6e761a7a62dc9cc597aef6e1d49cac6bdc495b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$432e4e01d71b10f1550b48be5a824f4f5138a82c\$lut for cells of type $lut.
Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut.
Using template $paramod$60096d1cdb5f7f55fdf4ed3aab322b5c7375f61e\$lut for cells of type $lut.
Using template $paramod$46e0c58da989560e0dc35528a00016369495a2aa\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$73d07df06bdcebf8bcc513075902f140fba061ec\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$4c8de682f2508054a5f7f13444038e3331866a9d\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut.
Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut.
Using template $paramod$a87662230f14ba9dfff5245dcac6285924ced66e\$lut for cells of type $lut.
Using template $paramod$ba38eeec612c623fb7e710aa4d96a3562d261f4e\$lut for cells of type $lut.
Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$93f74d366819d1f86e5e8b91d159aa6b1cd7e9fb\$lut for cells of type $lut.
Using template $paramod$ee454ad2383885733a4273245816698f8443c10b\$lut for cells of type $lut.
Using template $paramod$c471af5667a682bd131a5b479e58e470d1b2b7cd\$lut for cells of type $lut.
Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut.
Using template $paramod$f65af1b660a013aeaba9a5dc41e6bdede642e3c3\$lut for cells of type $lut.
Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821\$lut for cells of type $lut.
Using template $paramod$5ad7f7d3b561b5c79281ba8ebc061eab6e208d21\$lut for cells of type $lut.
Using template $paramod$d497222f59d990d3f689ed9c6ac453ecc8a2f4b4\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$bcc5b9fc09d0cdc8bad6b96e9e7cf91abb8e99bf\$lut for cells of type $lut.
Using template $paramod$2bf796e0fd6e6f7f76aac424a34e617ed5d61822\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$39b5c9bbcf3c411b53cac6bd441743d88790cb9c\$lut for cells of type $lut.
Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut.
Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut.
Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut.
Using template $paramod$7667ee60653b518109ce38341e4a8566a12b1d87\$lut for cells of type $lut.
Using template $paramod$b9305c669fd883d24574655b402c7ff9f28efb1a\$lut for cells of type $lut.
Using template $paramod$e953ca6166af75b2444378071091ce589a6edd9e\$lut for cells of type $lut.
Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut.
Using template $paramod$e343406e5e7142fc2d1b3b4b19848be7fa882f02\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod$9a383ca297ef012b6f33ce559547f89432250d88\$lut for cells of type $lut.
Using template $paramod$84f4f1db72921f11c5ff5a4dc511dfd4d3da404b\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b\$lut for cells of type $lut.
Using template $paramod$27331a24b2c1dcbe1b3eefac456a3f892f3b23d2\$lut for cells of type $lut.
Using template $paramod$ccd615fd05c207b3720d6a57918c9420a160f9de\$lut for cells of type $lut.
Using template $paramod$168aeef333136ff4f1f2ce3a62c8b6d1ffc7dc28\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$37cbd66b1bb96fdf033ea86280ae98f0988c69d1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod$b772929e028aced8081b5fc62b4a4f9cace04851\$lut for cells of type $lut.
Using template $paramod$ad2f7ea4e482304c44e7a6f6dae5db1a4029e245\$lut for cells of type $lut.
Using template $paramod$89968a75cd461967ed73db8ea07d0b7442f889e1\$lut for cells of type $lut.
Using template $paramod$ee3aee51512c440156b3fdfdf887fb8c17d950f3\$lut for cells of type $lut.
Using template $paramod$9c9c977d4ef412c658600f27af104e72c77928d0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$3538781ccdac1cfa3ad11d05d3d609f1cfa2d6b0\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$bb30b1a7babe3b9233abcb75d43d2653a9294bb7\$lut for cells of type $lut.
Using template $paramod$89b4b7e50bbae4eeba8c06f35180c6d1b6d9c2a9\$lut for cells of type $lut.
Using template $paramod$077caa0fe67e147edfc4c4dc820ac55adfc6d436\$lut for cells of type $lut.
Using template $paramod$756861dd4dfe0a5b9de37af2241117b1958e2ffe\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod$5b72438ff391ef6fcf2c5d407744382a084031d9\$lut for cells of type $lut.
Using template $paramod$555b6355e2cc751ac120ccebbd6efcfbc305670e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$64f43dc318f4c77b4186c3ebcba0aa7863e84359\$lut for cells of type $lut.
Using template $paramod$d96af730adf02974ec3298258a511f8b9b1fc45c\$lut for cells of type $lut.
Using template $paramod$24c5ea0aec41ae6ba7a430097101b6d6733bd632\$lut for cells of type $lut.
Using template $paramod$9ea238b3c4036add2bd96e5aaac8768e1ad77c5a\$lut for cells of type $lut.
Using template $paramod$27b3f0fa42364736b3118fe629ea0ac17a15414d\$lut for cells of type $lut.
Using template $paramod$c39bbcce81dae514aefd17dbc9fef8e011d41497\$lut for cells of type $lut.
Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut.
Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f\$lut for cells of type $lut.
Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut.
Using template $paramod$fcbd89979f935443011d8b6aa10df325912180d3\$lut for cells of type $lut.
Using template $paramod$df929792afd0bebf101a124ee890c12e0fed6a8d\$lut for cells of type $lut.
Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut.
Using template $paramod$c6bc287a973b75ebfda4bf6098ce9cb319148a64\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$09aa8a3143d50cc59564172c2564d6271fb3a300\$lut for cells of type $lut.
Using template $paramod$bc0c58c467d714257661a1d7ac1bb5f9ac39b898\$lut for cells of type $lut.
Using template $paramod$7a84df6e12e70b4c9a7b8fb79ef77f264f9bc27f\$lut for cells of type $lut.
Using template $paramod$db6b7476922213a65b6e3c3c166d39eadf7a7fdc\$lut for cells of type $lut.
Using template $paramod$ce5e9dd5e131f009611c40898ea0b12549bc2d79\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$7cef2c8af49f0e0719fb9a5ed02b1ac5d9028931\$lut for cells of type $lut.
Using template $paramod$f8e1bdecd38a1f2a88371fc52b96bff86506a2c7\$lut for cells of type $lut.
Using template $paramod$0d1a522f4785fa313f32f60468421ae26419ee3a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100110 for cells of type $lut.
Using template $paramod$e4839330e20dd875e13ea3ae857bc7ea9a9a5629\$lut for cells of type $lut.
Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut.
Using template $paramod$6423d726e9a2aeb860255b5262559102a32c1449\$lut for cells of type $lut.
Using template $paramod$684678481d261f1b3e68acd0931b217bad3edc9a\$lut for cells of type $lut.
Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut.
Using template $paramod$202ef33ed7c16f8af46b2c0a3a76b0741a206df4\$lut for cells of type $lut.
Using template $paramod$4f8edd664328039cee7936fba43b73a91069e069\$lut for cells of type $lut.
Using template $paramod$f054a7d7ab239e8c6ce022005b59678182897bfe\$lut for cells of type $lut.
Using template $paramod$06e1b49bb860dd46d7e5fdcbc52d5c30182f8b56\$lut for cells of type $lut.
Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut.
Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut.
Using template $paramod$a41f1fef22a0928d27fdf5da763576d46c440d8e\$lut for cells of type $lut.
Using template $paramod$f8e6f0da29c215071ce876a6530a409d298dc72f\$lut for cells of type $lut.
Using template $paramod$cfe658add7b49bc6805d629e0a88423d427de396\$lut for cells of type $lut.
Using template $paramod$e5c44f4d02c85ea0c5c37557461ed95a359dd42a\$lut for cells of type $lut.
Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut.
Using template $paramod$aad85cef508028e01cd98937a5134cd918b6ff79\$lut for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$d6d09106291e3062dc5392fbd4d67277151bdef8\$lut for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$c77bc7eeea014047171710483e12fa5d6d781f52\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$afdefd64f115cbb578c1cd4bf8426ecfef85ae91\$lut for cells of type $lut.
Using template $paramod$6e313f1dc296c479730132519b47325c14166ca6\$lut for cells of type $lut.
Using template $paramod$600a12a5825c233aa9b79c7688b53f96648d31cd\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$ff58554493773336c4e06dc62f25c37448f98c7b\$lut for cells of type $lut.
Using template $paramod$66130a021508460da8794592a805d466d1832f66\$lut for cells of type $lut.
Using template $paramod$d05301ce5e93dff706a71902518a509707fdd560\$lut for cells of type $lut.
Using template $paramod$f0974fda2881110b416333dc44279e032ed765a3\$lut for cells of type $lut.
Using template $paramod$5c38c17ad64dc89466bbbd6b31663f5f0f0671fa\$lut for cells of type $lut.
Using template $paramod$ab5c02e04aac2a755a7077d4a47f25280e3bc179\$lut for cells of type $lut.
Using template $paramod$99b80ad7a32a4cab9968c96b4968cd367d50ba80\$lut for cells of type $lut.
Using template $paramod$06713566e75acee437acc9156d50641188a3bd98\$lut for cells of type $lut.
Using template $paramod$4346d03553d2efc99f22a8f3e6d74c32adfb133e\$lut for cells of type $lut.
Using template $paramod$73e27aafa9e42be181ed0683a42a6aa1db650e3d\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$766f851776a2d25e13728c9147ddfe7ff70917a3\$lut for cells of type $lut.
Using template $paramod$28e2a479987a035f608a836ed0e0d93dcabf5445\$lut for cells of type $lut.
Using template $paramod$a062d72afab9fb247973992aa72e13128fcbbeeb\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$2a2d4c86167109f1e1c123aeaa7489a318c9881b\$lut for cells of type $lut.
Using template $paramod$a511f425a16be7369933baa8c17a62ec61a7d7bf\$lut for cells of type $lut.
Using template $paramod$40e5a5bffee68d424d8b966d83c16c547cdeb8ab\$lut for cells of type $lut.
Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut.
Using template $paramod$6f3f060a82077d7722793a80a7f81ffcda8e7f4d\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod$3ed38497da539fb1966ff98618ed0995aecce72a\$lut for cells of type $lut.
Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod$c2842ed6ac328d347b6d1c2cecf2b583dc6a8707\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$01e96e53d77f79e0721c00741bd5ab06a9e25a93\$lut for cells of type $lut.
Using template $paramod$9b041a9580d113123e73bb50e05a5c2cde18e031\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut.
Using template $paramod$d8325753180ccd86c828757d9dbb16c299287a89\$lut for cells of type $lut.
Using template $paramod$096f8f0a00831e8fcf9de4968c0c1d657d68ca97\$lut for cells of type $lut.
Using template $paramod$f66701c2a576cac72f53fd2cecc38934e65f0e16\$lut for cells of type $lut.
Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut.
Using template $paramod$5cbf57656b696240954235fae9426d7f1493fda9\$lut for cells of type $lut.
Using template $paramod$693a12eaf143c7ed2a80a183d2e9375572af15f6\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$6ec77e5904e6054edcc5c95cc394e9dfebf2889e\$lut for cells of type $lut.
Using template $paramod$e5761adfcc530461835be17350166b9d43dfadee\$lut for cells of type $lut.
Using template $paramod$2558c329bb5b4a00f8ccab4e2e8b51b456f1d8b1\$lut for cells of type $lut.
Using template $paramod$8f986caed758d4e6ddf0982fe58e5dab967f469f\$lut for cells of type $lut.
Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut.
Using template $paramod$c75656bc8af73b1fd37fc2f9580b970bd545f476\$lut for cells of type $lut.
Using template $paramod$02904265621ae79a27c13b089e66a2817bd924bf\$lut for cells of type $lut.
Using template $paramod$4e5c78db886e260fae81580d9aff04819947b95f\$lut for cells of type $lut.
Using template $paramod$be6ac5828ef34873154e44fd05a2dbaadc4bbfbd\$lut for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut.
Using template $paramod$960ac2b5144f5b7bfcff596b057efff7228d3117\$lut for cells of type $lut.
Using template $paramod$8ca9224585981e8fbfac9b98f6e2848113a34467\$lut for cells of type $lut.
Using template $paramod$cc0454b50e7a4bac6495b6e30a58ceb8dfd032c5\$lut for cells of type $lut.
Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut.
Using template $paramod$821c2723d6171961a34ac5358ff9ec58dbfb33a8\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$021904a6d3cd28c5646f5dad6a4a7f12484f0a2e\$lut for cells of type $lut.
Using template $paramod$3357e04690749b6c89de0fcd28f53cd216bd2047\$lut for cells of type $lut.
Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut.
Using template $paramod$718179c4766b4ea66e8ece9b944be5b997b67ba5\$lut for cells of type $lut.
Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod$849eede967b3c8935808391f1a9ce50503aa897a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut.
Using template $paramod$e942ff15257dd44eb70ae034d1b665e0116c7a3e\$lut for cells of type $lut.
Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut.
Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut.
Using template $paramod$95437c548840ae5673e70f982edd362a76476eb8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$85b36cc3c65c84e4f6c8451518ca3211c7c1cba0\$lut for cells of type $lut.
Using template $paramod$6b666729e8acbed684231f468059c6ab64de1fba\$lut for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$e239c80ed79b5a8451681fe5c06c49632ba73ede\$lut for cells of type $lut.
Using template $paramod$5e96c51e862795fcf5123ad90ed33b3bddf109cb\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut.
Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut.
Using template $paramod$47fa2f84639cacb9dd6b3d20220476702f4e2512\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$bd8eb8a93a84395fc86ec14d94f01a1a060e9d20\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$2f1f206e63267115fcaedc93034f025334319032\$lut for cells of type $lut.
Using template $paramod$74190755306950a81a07803293f7549508f6f157\$lut for cells of type $lut.
Using template $paramod$fa9eb26fcf7e57b4dc534d2b1f531381b1fc4e16\$lut for cells of type $lut.
Using template $paramod$3ec83cc0e0ec241030d7c40596e80d62c44c0f57\$lut for cells of type $lut.
Using template $paramod$47050b95172a3d97945f1d3565e0c2cf796d5a4a\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$accf50a247cd8bba7db1ad1f71c658b6b8d28bae\$lut for cells of type $lut.
Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut.
Using template $paramod$2ba51c7bf234f9ce3d769281ed286d6830810ff5\$lut for cells of type $lut.
Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut.
Using template $paramod$7c3833e617307006af30409ed68b65a011a1121e\$lut for cells of type $lut.
Using template $paramod$6aa123f49eb0ae3739d6708812cedabc589076b1\$lut for cells of type $lut.
Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe\$lut for cells of type $lut.
Using template $paramod$529baf23c57d5ed871d62e547aaaa8bb53e364ce\$lut for cells of type $lut.
Using template $paramod$f65cf6380214e831938c4f25f730307ae86218f7\$lut for cells of type $lut.
Using template $paramod$5b522c549bf568db4969be109aabdbdd1b5ea20b\$lut for cells of type $lut.
Using template $paramod$72ec34f0d3574fd4a61ad277dc680da7ce75f22e\$lut for cells of type $lut.
Using template $paramod$14f110dd93cb39e050b0d142022c473ff15c7394\$lut for cells of type $lut.
Using template $paramod$b90d0bd825ef9aa143f3f391212f99bcd2d228dc\$lut for cells of type $lut.
Using template $paramod$b50d1dafa6b98a085ed9bc5bbcfdb0b166f8cfb2\$lut for cells of type $lut.
Using template $paramod$2225cef461de622c2634604592601e1bcc55dfcc\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$dc80e74b9623b8a802ef4b5162559616e5ac1cef\$lut for cells of type $lut.
Using template $paramod$4a0b7d2a2849f16773696ba19d68aee3da2f49f1\$lut for cells of type $lut.
Using template $paramod$3d8fa18e9c34a1aa6c69e2f2e158bbfff1733c5e\$lut for cells of type $lut.
Using template $paramod$55ac124d6496496a64c6f2c29f5ac412a62ef57d\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$b01cf9ad43c57de5e967ca9c8e14912aa370b88c\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$a2852b15f763e943f165ca09df85ea37f94d7533\$lut for cells of type $lut.
Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9\$lut for cells of type $lut.
Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut.
Using template $paramod$1ca23e17bf41dc1e9eab64b373f9322defa25a58\$lut for cells of type $lut.
Using template $paramod$b009a26b33c3ca109c016cf968a774c0d66687bb\$lut for cells of type $lut.
Using template $paramod$f821be747782e31d503fe9b09e9af982befba4b8\$lut for cells of type $lut.
Using template $paramod$eec5f7b0cabd69dce13ed9564259f8a7153bcc2b\$lut for cells of type $lut.
Using template $paramod$1c841451dcbff3fc89c34b98394654d15d2a6c07\$lut for cells of type $lut.
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut.
Using template $paramod$a10421186f5d825e033d40d060e41227b3d8cca1\$lut for cells of type $lut.
Using template $paramod$b5640990f5ca1875cce1a6c7d2b3eb17963ae49e\$lut for cells of type $lut.
Using template $paramod$ca009e911508f27903ef81bdd82bfd594b87e190\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$686040a6946217fb8cbe14a1f78309cb287b4969\$lut for cells of type $lut.
Using template $paramod$7ed31fc00b1e5ea4e6f7d572afcd9937b67f68a0\$lut for cells of type $lut.
Using template $paramod$f329471abfc3d33a0c54fa800ada6b7f22f95f8e\$lut for cells of type $lut.
Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$a2bdfa5e998d98fd71d35f847d9d764874dcd9e4\$lut for cells of type $lut.
Using template $paramod$0bfc535937424f0464495d54aead951ee8afbe60\$lut for cells of type $lut.
Using template $paramod$504d627b7f107c5f6e5c95ac43c2135d313086e7\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$f919a4b1991f60672ac129533fc4e98150f7d551\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut.
Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut.
Using template $paramod$d6e6d411b16e057eae3ca70523bb1b2722704525\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$76bda82466d3389b35a6c0d236517b2521618924\$lut for cells of type $lut.
Using template $paramod$b40080b643baa8bb528ec249e10d82b2d80dfed9\$lut for cells of type $lut.
Using template $paramod$13fa9273f1d4ad6050109d02dc87cffc90450a95\$lut for cells of type $lut.
Using template $paramod$13162dab747ee1e52bfdba3be872c6d5a3be6de5\$lut for cells of type $lut.
Using template $paramod$1194b3a751797ffd33921d63424430e7f1ad2a46\$lut for cells of type $lut.
Using template $paramod$de273d25f15c0e35d4108e94f7e3bd92c2e83118\$lut for cells of type $lut.
Using template $paramod$be3467da0aa76c53b62720d6629fc1936fb1c80b\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$0a7817d70895c67313a5df1d76db8357ea7a02a0\$lut for cells of type $lut.
Using template $paramod$4b53666b54a16ca39a6a9869fccf7559f4171200\$lut for cells of type $lut.
Using template $paramod$3fb4a429a639413454e34f7173da8b9aaf03d0ea\$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut.
Using template $paramod$f08ee5ba8cbad0de744a29087d087b708de24c40\$lut for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
Using template $paramod$0e0a07cdccb283f6c4d859d0738d3a6854a935f9\$lut for cells of type $lut.
Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut.
Using template $paramod$89e65390572caf861d31d3a1660dfb6237dfbcc4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$bfeabb867bd04e7effc04f34074b9c8e66901d92\$lut for cells of type $lut.
Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut.
Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~27994 debug messages>

34.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833243.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2771:And$8304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7075[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21449.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$28885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$28092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16063.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$24453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$14663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$14869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$15982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16885.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$16973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$17879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$17961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$17998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18215.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18271.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$18437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$18418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$18553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$19213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$19600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$19625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$19694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$19719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$19857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$19903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$19911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$20234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$20691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$20880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4664_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$20495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$21873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$22125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$22162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$22829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$22875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$22900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$22921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$22998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$23064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$23236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23257.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$23931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$24838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$25127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$25921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$26874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$27721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$28835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$29530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$29801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$29953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$30221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$30397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$30626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$30692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$30960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$31212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$31586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$31993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$32586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$32812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$32850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$32900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$32968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$33659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$33885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$33998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$34567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$34970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834148.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$35358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$35439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$35479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$35525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$35546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$35956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$36716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$36871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$36928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$37237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37263.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$37295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$37468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$37477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$37534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$37543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$37778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$37778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$37957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$38476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$38483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$38576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$38948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$38996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$39482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$39517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$39556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$39566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$39578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$39982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$40222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$18413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$40516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$34413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$40631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$40650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$40659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$40950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834031.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$41489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$41773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$41951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$42501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$42790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$42996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$43196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$43217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$43655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$43993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$44466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$44631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$44650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$44660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$44979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$45689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$45872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$45974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$45990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$46580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$46703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$46758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$46960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$46967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$47892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$47920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$47984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$47984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$48156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48763.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$48866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$48985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$49004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$49014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$49308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$49315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$49450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$49550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$49812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$49998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$49998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$50019.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$50040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$50062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$50430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$50532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4597_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$50984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$51026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$51112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$51941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$51941.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$52172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$52878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$52925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$52925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$53590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$53977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$53977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$54212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$54758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$54914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$54914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$55884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$55925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$55925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$56933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$56933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$57932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$57932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$58435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$58935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$58935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$59082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$59800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59833.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$59874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$59945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$59945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$60945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$60945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61445.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$61946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$61946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$62947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$62947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$63954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$63954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64097.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$64956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$64956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$65955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$65955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$66955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$66955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$67957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$67957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68100.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$68962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$68962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$69677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$69677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$49777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\M1.$procmux$3191_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\M1.$procmux$3243_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$opt_dff.cc:219:make_patterns_logic$6539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$opt_dff.cc:219:make_patterns_logic$6699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2724:Not$6582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2771:And$8304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7063[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$21570.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7075[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7075[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$fsm_map.cc:170:map_fsm$5645[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$50604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7063[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2859:Mux$7075[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$21829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$rtlil.cc:2771:And$8304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$48345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$auto$opt_dff.cc:219:make_patterns_logic$5963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$49812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4989_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4260_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4260_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4260_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4260_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4260_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\First_Stage.$procmux$4290_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:48$559_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$0\take_jalr_o[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4551_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4551_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$28904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$31011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$14917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$832907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833791.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$46703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$45963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$45308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$44166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$43338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$833995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$42431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$41169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$40622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$39116.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$38000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$37450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$36463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$35623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$34422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834257.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$17412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$832866$lut$aiger832865$15890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$16070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$832866$lut$aiger832865$15594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$832866$lut$aiger832865$15642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834441.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$832866$lut$aiger832865$16130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$832866$lut\Controller.Memory.write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$834517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 41219 unused wires.

34.45. Executing AUTONAME pass.
Renamed 3354051 objects in module processorci_top (442 iterations).
<suppressed ~44560 debug messages>

34.46. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `processorci_top'. Setting top module to processorci_top.

34.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

34.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

34.47. Printing statistics.

=== processorci_top ===

   Number of wires:              17470
   Number of wire bits:          56489
   Number of public wires:       17470
   Number of public wire bits:   56489
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              28757
     $scopeinfo                     32
     CCU2C                         541
     DP16KD                          1
     L6MUX21                       463
     LUT4                        19450
     MULT18X18D                      4
     PFUMX                        2921
     TRELLIS_DPR16X4              1058
     TRELLIS_FF                   4287

34.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

34.49. Executing JSON backend.

Warnings: 69 unique messages, 69 total
End of script. Logfile hash: ec24d35a79, CPU: user 258.76s system 1.33s, MEM: 1065.59 MB peak
Time spent: 39% 1x abc9_exe (102 sec), 10% 1x autoname (26 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [===                                               ] 4.41%
Loading: [=====                                             ] 9.19%
Loading: [=======                                           ] 13.97%
Loading: [==========                                        ] 18.75%
Loading: [============                                      ] 23.16%
Loading: [==============                                    ] 27.20%
Loading: [=================                                 ] 32.16%
Loading: [===================                               ] 37.13%
Loading: [=====================                             ] 41.54%
Loading: [========================                          ] 46.50%
Loading: [==========================                        ] 51.28%
Loading: [============================                      ] 55.87%
Loading: [===============================                   ] 60.65%
Loading: [=================================                 ] 65.61%
Loading: [====================================              ] 70.21%
Loading: [=====================================             ] 73.88%
Loading: [========================================          ] 78.48%
Loading: [==========================================        ] 82.70%
Loading: [============================================      ] 87.30%
Loading: [===============================================   ] 92.08%
Loading: [================================================= ] 96.67%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1278.309 ; gain = 24.836 ; free physical = 1811 ; free virtual = 24221
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv
WARNING: [filemgmt 56-12] File '/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv' cannot be added to the project because it already exists in the project, skipping this file
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv
# read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv
# read_verilog /eda/processor_ci/rtl/Grande-Risco-5.v
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# set HIGH_CLK 1
# read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \
#     -verilog_define $HIGH_CLK
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3809364
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2033.031 ; gain = 403.746 ; free physical = 739 ; free virtual = 23149
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/Grande-Risco-5.v:149]
INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/Grande-Risco-5.v:29]
CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/Grande-Risco-5.v:149]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Grande-Risco-5.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
	Parameter COUNTER_BITS bound to: 32 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
WARNING: [Synth 8-7071] port 'core_read_data_memory_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50]
WARNING: [Synth 8-7071] port 'core_memory_read_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50]
WARNING: [Synth 8-7071] port 'core_memory_write_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50]
WARNING: [Synth 8-7023] instance 'Controller' of module 'Controller' has 27 connections declared, but only 24 given [/eda/processor_ci/rtl/Grande-Risco-5.v:50]
INFO: [Synth 8-6157] synthesizing module 'Grande_Risco5' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
	Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'IFID' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
	Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'IR_Decompression' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:31]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:34]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:76]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:114]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:132]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:198]
INFO: [Synth 8-6155] done synthesizing module 'IR_Decompression' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:216]
INFO: [Synth 8-6157] synthesizing module 'Branch_Prediction' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1]
	Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Branch_Prediction' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Invalid_IR_Check' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:16]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:18]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:24]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:33]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:45]
INFO: [Synth 8-6155] done synthesizing module 'Invalid_IR_Check' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'IFID' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3]
INFO: [Synth 8-6157] synthesizing module 'IDEX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:26]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:30]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:41]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:41]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:29]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Forwarding_Unit' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Forwarding_Unit' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:11]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1]
INFO: [Synth 8-6157] synthesizing module 'MDU' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4]
INFO: [Synth 8-6155] done synthesizing module 'MDU' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4]
INFO: [Synth 8-6155] done synthesizing module 'IDEX' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3]
INFO: [Synth 8-6157] synthesizing module 'EXMEM' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:99]
INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:237]
INFO: [Synth 8-6155] done synthesizing module 'EXMEM' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3]
INFO: [Synth 8-6157] synthesizing module 'MEMWB' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:74]
INFO: [Synth 8-6155] done synthesizing module 'MEMWB' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:88]
INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:100]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3]
INFO: [Synth 8-6157] synthesizing module 'ICache' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1]
	Parameter CACHE_SIZE bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ICache' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1]
INFO: [Synth 8-6157] synthesizing module 'DCache' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1]
	Parameter CACHE_SIZE bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'DCache' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1]
INFO: [Synth 8-6157] synthesizing module 'Cache_request_Multiplexer' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1]
	Parameter DATA_WIDTH bound to: 32 - type: integer 
	Parameter ADDR_WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Cache_request_Multiplexer' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1]
INFO: [Synth 8-6155] done synthesizing module 'Grande_Risco5' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Grande-Risco-5.v:153]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Grande-Risco-5.v:153]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/Grande-Risco-5.v:153]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Grande-Risco-5.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-6014] Unused sequential element jump_is_predicted_reg was removed.  [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:87]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Grande-Risco-5.v:21]
WARNING: [Synth 8-7129] Port invalid_fetch_instruction in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port invalid_decode_instruction in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[31] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[30] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[29] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[28] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[27] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[26] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[25] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[24] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[23] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[22] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[21] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[20] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[19] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[18] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[17] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[16] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[15] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[14] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[13] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[12] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[11] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[10] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[9] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[8] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[7] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[6] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[5] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port fetch_pc[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[31] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[30] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[29] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[28] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[27] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[26] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[25] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[24] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[23] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[22] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[21] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[20] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[19] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[18] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[17] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[16] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[15] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[14] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[13] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[12] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[11] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[10] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[9] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[8] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[7] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[6] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[5] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port decode_pc[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[31] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[30] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[29] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[28] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[27] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[26] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[25] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[24] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[23] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[22] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[21] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[20] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[19] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[18] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[17] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[16] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[15] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[14] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[13] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[12] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[11] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[10] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[9] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[8] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[7] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[6] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[5] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[4] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[3] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[2] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[1] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port execute_pc[0] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_pc[31] in module CSR_Unit is either unconnected or has no load
WARNING: [Synth 8-7129] Port memory_pc[30] in module CSR_Unit is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2305.109 ; gain = 675.824 ; free physical = 451 ; free virtual = 22865
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2319.953 ; gain = 690.668 ; free physical = 445 ; free virtual = 22859
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2319.953 ; gain = 690.668 ; free physical = 455 ; free virtual = 22869
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2319.953 ; gain = 0.000 ; free physical = 451 ; free virtual = 22865
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2459.703 ; gain = 0.000 ; free physical = 393 ; free virtual = 22808
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2459.738 ; gain = 0.000 ; free physical = 393 ; free virtual = 22808
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 880 ; free virtual = 23345
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 879 ; free virtual = 23344
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:07 ; elapsed = 00:01:09 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 882 ; free virtual = 23347
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_mul_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'state_div_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'unaligned_access_state_reg' in module 'EXMEM'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
                    READ |                              001 |                             0001
        COPY_READ_BUFFER |                              010 |                             0100
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
       COPY_WRITE_BUFFER |                              001 |                             0100
                   WRITE |                              010 |                             0001
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                             0001 |                               00
                 iSTATE0 |                             0010 |                               01
                 iSTATE1 |                             0100 |                               10
                 iSTATE2 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                MUL_IDLE |                              001 |                               00
             MUL_OPERATE |                              010 |                               01
              MUL_FINISH |                              100 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_mul_reg' using encoding 'one-hot' in module 'MDU'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                             0000 |                             0000
      READ_WORD_TO_SUBSW |                             0001 |                             1011
    MODIFY_WORD_TO_SUBSW |                             0010 |                             1100
         READ_FIRST_WORD |                             0011 |                             0001
        READ_SECOND_WORD |                             0100 |                             0010
             MERGE_WORDS |                             0101 |                             0011
               CUT_WORDS |                             0110 |                             1010
READ_FIRST_WORD_TO_WRITE |                             0111 |                             0100
   MODIFY_FIRST_WORD_SUB |                             1000 |                             1110
             WRITE_SUBSW |                             1001 |                             1101
       MODIFY_FIRST_WORD |                             1010 |                             0101
        WRITE_FIRST_WORD |                             1011 |                             0110
READ_SECOND_WORD_TO_WRITE |                             1100 |                             0111
  MODIFY_SECOND_WORD_SUB |                             1101 |                             1111
      MODIFY_SECOND_WORD |                             1110 |                             1000
       WRITE_SECOND_WORD |                             1111 |                             1001
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'unaligned_access_state_reg' using encoding 'sequential' in module 'EXMEM'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:45 ; elapsed = 00:01:47 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 790 ; free virtual = 23274
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   64 Bit       Adders := 2     
	   2 Input   32 Bit       Adders := 19    
	   3 Input   32 Bit       Adders := 2     
	   2 Input   24 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 2     
	   2 Input    8 Bit       Adders := 1     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
	   2 Input    2 Bit       Adders := 3     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---Registers : 
	               64 Bit    Registers := 3     
	               63 Bit    Registers := 1     
	               32 Bit    Registers := 88    
	               24 Bit    Registers := 5     
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 2     
	                8 Bit    Registers := 11    
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 3     
	                3 Bit    Registers := 2     
	                2 Bit    Registers := 512   
	                1 Bit    Registers := 88    
+---Multipliers : 
	              32x32  Multipliers := 1     
+---RAMs : 
	              32K Bit	(1024 X 32 bit)          RAMs := 2     
	              256 Bit	(8 X 32 bit)          RAMs := 2     
	              216 Bit	(8 X 27 bit)          RAMs := 2     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   4 Input   64 Bit        Muxes := 1     
	   2 Input   64 Bit        Muxes := 1     
	  48 Input   64 Bit        Muxes := 2     
	   4 Input   63 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 58    
	   3 Input   32 Bit        Muxes := 7     
	   4 Input   32 Bit        Muxes := 13    
	   8 Input   32 Bit        Muxes := 4     
	   5 Input   32 Bit        Muxes := 4     
	  16 Input   32 Bit        Muxes := 5     
	  14 Input   32 Bit        Muxes := 1     
	  48 Input   24 Bit        Muxes := 1     
	   2 Input    9 Bit        Muxes := 2     
	  48 Input    8 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 4     
	  24 Input    7 Bit        Muxes := 1     
	   2 Input    7 Bit        Muxes := 2     
	   2 Input    6 Bit        Muxes := 4     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 2     
	   9 Input    4 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	  16 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 9     
	  25 Input    4 Bit        Muxes := 1     
	  10 Input    3 Bit        Muxes := 1     
	   3 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 5     
	   5 Input    3 Bit        Muxes := 4     
	   2 Input    2 Bit        Muxes := 22    
	   4 Input    2 Bit        Muxes := 5     
	   3 Input    2 Bit        Muxes := 4     
	  48 Input    2 Bit        Muxes := 1     
	   7 Input    1 Bit        Muxes := 2     
	   2 Input    1 Bit        Muxes := 3231  
	   5 Input    1 Bit        Muxes := 14    
	   8 Input    1 Bit        Muxes := 1     
	  13 Input    1 Bit        Muxes := 1     
	   4 Input    1 Bit        Muxes := 10    
	   6 Input    1 Bit        Muxes := 3     
	   3 Input    1 Bit        Muxes := 9     
	  16 Input    1 Bit        Muxes := 9     
	   9 Input    1 Bit        Muxes := 7     
	  48 Input    1 Bit        Muxes := 22    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP acumulador0, operation Mode is: A2*B.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: Generating DSP acumulador0, operation Mode is: A2*B2.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: register acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A2*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[47]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[46]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[45]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[44]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[43]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[42]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[41]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[40]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[39]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[38]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[37]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[36]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[35]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[34]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[33]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[32]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[31]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[30]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[29]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[28]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[27]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[26]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[25]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[24]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[23]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[22]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[21]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[20]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[19]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[18]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[17]) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[47]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[46]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[45]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[44]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[43]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[42]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[41]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[40]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[39]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[38]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[37]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[36]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[35]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[34]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[33]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[32]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[31]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[30]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[29]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[28]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[27]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[26]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[25]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[24]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[23]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[22]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[21]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[20]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[19]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[18]__0) is unused and will be removed from module IDEX.
WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[17]__0) is unused and will be removed from module IDEX.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:04:43 ; elapsed = 00:04:47 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 218 ; free virtual = 22730
---------------------------------------------------------------------------------
 Sort Area is Core__GB1 acumulador0_3 : 0 0 : 2737 4966 : Used 1 time 0
 Sort Area is Core__GB1 acumulador0_3 : 0 1 : 2229 4966 : Used 1 time 0
 Sort Area is Core__GB1 acumulador0_0 : 0 0 : 2176 4080 : Used 1 time 0
 Sort Area is Core__GB1 acumulador0_0 : 0 1 : 1904 4080 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object          | Depth x Width | Implemented As | 
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
+------------+---------------------+---------------+----------------+


Distributed RAM: Preliminary Mapping Report (see note below)
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+
|Module Name                                  | RTL Object                         | Inference | Size (Depth x Width) | Primitives       | 
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+
|\Processor/N1/First_Stage /Branch_Prediction | address_to_jump_reg                | Implied   | 512 x 32             | RAM64M x 264     | 
|processorci_top                              | ICache/cache_tag_reg               | Implied   | 8 x 27               | RAM16X1S x 27    | 
|processorci_top                              | ICache/cache_data_reg              | Implied   | 8 x 32               | RAM16X1S x 32    | 
|processorci_top                              | DCache/cache_tag_reg               | Implied   | 8 x 27               | RAM16X1S x 27    | 
|processorci_top                              | DCache/cache_data_reg              | Implied   | 8 x 32               | RAM16X1S x 32    | 
|processorci_top                              | Controller/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top                              | Controller/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top                              | Controller/Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|processorci_top                              | Controller/Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping     | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU         | A2*B            | 18     | 15     | -      | -      | 48     | 1    | 0    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17)+A*B  | 15     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 1    | 
|MDU         | A2*B2           | 18     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17)+A2*B | 18     | 15     | -      | -      | 48     | 1    | 0    | -    | -    | -     | 0    | 1    | 
+------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:05:00 ; elapsed = 00:05:04 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 220 ; free virtual = 22732
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:05:33 ; elapsed = 00:05:38 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 164 ; free virtual = 22627
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+
|Module Name                                  | RTL Object                         | Inference | Size (Depth x Width) | Primitives       | 
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+
|\Processor/N1/First_Stage /Branch_Prediction | address_to_jump_reg                | Implied   | 512 x 32             | RAM64M x 264     | 
|processorci_top                              | ICache/cache_tag_reg               | Implied   | 8 x 27               | RAM16X1S x 27    | 
|processorci_top                              | ICache/cache_data_reg              | Implied   | 8 x 32               | RAM16X1S x 32    | 
|processorci_top                              | DCache/cache_tag_reg               | Implied   | 8 x 27               | RAM16X1S x 27    | 
|processorci_top                              | DCache/cache_data_reg              | Implied   | 8 x 32               | RAM16X1S x 32    | 
|processorci_top                              | Controller/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top                              | Controller/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|processorci_top                              | Controller/Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|processorci_top                              | Controller/Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+---------------------------------------------+------------------------------------+-----------+----------------------+------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:05:47 ; elapsed = 00:05:52 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 150 ; free virtual = 22411
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:06:00 ; elapsed = 00:06:05 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 670 ; free virtual = 22843
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:06:00 ; elapsed = 00:06:05 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 670 ; free virtual = 22843
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:07 ; elapsed = 00:06:12 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 650 ; free virtual = 22824
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:06:07 ; elapsed = 00:06:13 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 651 ; free virtual = 22824
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:06:08 ; elapsed = 00:06:14 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 658 ; free virtual = 22831
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:06:09 ; elapsed = 00:06:14 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 658 ; free virtual = 22831
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

DSP Final Report (the ' indicates corresponding REG is set)
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping       | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU         | A'*B'             | 17     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17+A'*B')' | 30     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    | 
|MDU         | A'*B'             | 17     | 17     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17+A'*B')' | 17     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    | 
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+


Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |   279|
|3     |DSP48E1   |     4|
|5     |LUT1      |   136|
|6     |LUT2      |   680|
|7     |LUT3      |  1540|
|8     |LUT4      |   686|
|9     |LUT5      |   852|
|10    |LUT6      |  4234|
|11    |MUXF7     |   663|
|12    |MUXF8     |    35|
|13    |RAM16X1S  |   118|
|14    |RAM256X1S |   256|
|15    |RAM32M    |     2|
|16    |RAM32X1D  |     4|
|17    |RAM64M    |   264|
|18    |FDRE      |  4288|
|19    |FDSE      |    18|
|20    |IBUF      |     2|
|21    |OBUF      |     2|
|22    |OBUFT     |     1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:06:09 ; elapsed = 00:06:14 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 658 ; free virtual = 22831
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 64 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:05:59 ; elapsed = 00:06:05 . Memory (MB): peak = 2459.738 ; gain = 690.668 ; free physical = 666 ; free virtual = 22840
Synthesis Optimization Complete : Time (s): cpu = 00:06:09 ; elapsed = 00:06:15 . Memory (MB): peak = 2459.738 ; gain = 830.453 ; free physical = 666 ; free virtual = 22840
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2459.738 ; gain = 0.000 ; free physical = 973 ; free virtual = 23146
INFO: [Netlist 29-17] Analyzing 1625 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2523.734 ; gain = 0.000 ; free physical = 967 ; free virtual = 23140
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 644 instances were transformed.
  RAM16X1S => RAM32X1S (RAMS32): 118 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
  RAM64M => RAM64M (RAMD64E(x4)): 264 instances

Synth Design complete | Checksum: 7b8a8a0b
INFO: [Common 17-83] Releasing license: Synthesis
118 Infos, 186 Warnings, 4 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:34 ; elapsed = 00:06:35 . Memory (MB): peak = 2523.770 ; gain = 1239.523 ; free physical = 975 ; free virtual = 23148
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2269.964; main = 1937.556; forked = 473.976
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3435.246; main = 2523.738; forked = 1007.555
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2587.766 ; gain = 63.996 ; free physical = 974 ; free virtual = 23147

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1ed99352d

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2587.766 ; gain = 0.000 ; free physical = 953 ; free virtual = 23126

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1ed99352d

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 746 ; free virtual = 22920

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1ed99352d

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 745 ; free virtual = 22918
Phase 1 Initialization | Checksum: 1ed99352d

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 744 ; free virtual = 22918

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1ed99352d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 737 ; free virtual = 22910

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1ed99352d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 737 ; free virtual = 22910
Phase 2 Timer Update And Timing Data Collection | Checksum: 1ed99352d

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 737 ; free virtual = 22910

Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1ed99352d

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 737 ; free virtual = 22911
Retarget | Checksum: 1ed99352d
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 2096b83eb

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 738 ; free virtual = 22911
Constant propagation | Checksum: 2096b83eb
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 19475d566

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2782.766 ; gain = 0.000 ; free physical = 748 ; free virtual = 22922
Sweep | Checksum: 19475d566
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 19475d566

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 743 ; free virtual = 22917
BUFG optimization | Checksum: 19475d566
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 19475d566

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 746 ; free virtual = 22919
Shift Register Optimization | Checksum: 19475d566
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 19475d566

Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 740 ; free virtual = 22914
Post Processing Netlist | Checksum: 19475d566
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e01138f4

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 744 ; free virtual = 22917

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 744 ; free virtual = 22917
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e01138f4

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 744 ; free virtual = 22917
Phase 9 Finalization | Checksum: 1e01138f4

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 744 ; free virtual = 22917
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 1e01138f4

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2814.781 ; gain = 32.016 ; free physical = 744 ; free virtual = 22917
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 740 ; free virtual = 22913

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1e01138f4

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 750 ; free virtual = 22923

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1e01138f4

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 750 ; free virtual = 22923

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 750 ; free virtual = 22923
Ending Netlist Obfuscation Task | Checksum: 1e01138f4

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2814.781 ; gain = 0.000 ; free physical = 750 ; free virtual = 22923
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 2814.781 ; gain = 291.012 ; free physical = 750 ; free virtual = 22923
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2846.797 ; gain = 0.000 ; free physical = 751 ; free virtual = 22925
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1b13ba933

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2846.797 ; gain = 0.000 ; free physical = 751 ; free virtual = 22925
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2846.797 ; gain = 0.000 ; free physical = 751 ; free virtual = 22925

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19d507748

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.797 ; gain = 0.000 ; free physical = 759 ; free virtual = 22932

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 28dc3b7d2

Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 738 ; free virtual = 22912

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 28dc3b7d2

Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 741 ; free virtual = 22914
Phase 1 Placer Initialization | Checksum: 28dc3b7d2

Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 737 ; free virtual = 22911

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 21ad1d6b5

Time (s): cpu = 00:00:32 ; elapsed = 00:00:21 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 731 ; free virtual = 22905

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1e1101836

Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 738 ; free virtual = 22912

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1e1101836

Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 741 ; free virtual = 22914

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 17afe32e1

Time (s): cpu = 00:01:50 ; elapsed = 00:01:12 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 742 ; free virtual = 22916

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 113 LUTNM shape to break, 192 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 26, two critical 87, total 113, new lutff created 3
INFO: [Physopt 32-1138] End 1 Pass. Optimized 195 nets or LUTs. Breaked 113 LUTs, combined 82 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 731 ; free virtual = 22905

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |          113  |             82  |                   195  |           0  |           1  |  00:00:02  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |          113  |             82  |                   195  |           0  |           9  |  00:00:02  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 3dfb3233

Time (s): cpu = 00:01:59 ; elapsed = 00:01:18 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 630 ; free virtual = 22804
Phase 2.4 Global Placement Core | Checksum: fb1fa8a1

Time (s): cpu = 00:03:27 ; elapsed = 00:02:03 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 565 ; free virtual = 22739
Phase 2 Global Placement | Checksum: fb1fa8a1

Time (s): cpu = 00:03:27 ; elapsed = 00:02:03 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 563 ; free virtual = 22738

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 23c93ec0

Time (s): cpu = 00:03:33 ; elapsed = 00:02:06 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 578 ; free virtual = 22753

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12a23f630

Time (s): cpu = 00:03:47 ; elapsed = 00:02:15 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 578 ; free virtual = 22752

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 17534eb17

Time (s): cpu = 00:03:47 ; elapsed = 00:02:16 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 571 ; free virtual = 22745

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 105fa6bb4

Time (s): cpu = 00:03:47 ; elapsed = 00:02:16 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 574 ; free virtual = 22749

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 18f01add3

Time (s): cpu = 00:04:14 ; elapsed = 00:02:35 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 564 ; free virtual = 22738

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 169712033

Time (s): cpu = 00:04:28 ; elapsed = 00:02:49 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 572 ; free virtual = 22746

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 118dfed92

Time (s): cpu = 00:04:30 ; elapsed = 00:02:51 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 578 ; free virtual = 22753

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 6d1f8bd4

Time (s): cpu = 00:04:30 ; elapsed = 00:02:52 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 578 ; free virtual = 22753

Phase 3.9 Fast Optimization
Phase 3.9 Fast Optimization | Checksum: 13cad3426

Time (s): cpu = 00:05:15 ; elapsed = 00:03:26 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 576 ; free virtual = 22751
Phase 3 Detail Placement | Checksum: 13cad3426

Time (s): cpu = 00:05:15 ; elapsed = 00:03:26 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 576 ; free virtual = 22751

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1efeb8a3f

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-4.379 | TNS=-7404.420 |
Phase 1 Physical Synthesis Initialization | Checksum: 139135a40

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 568 ; free virtual = 22742
INFO: [Place 46-33] Processed net Controller/Interpreter/core_reset_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 139135a40

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 576 ; free virtual = 22750
Phase 4.1.1.1 BUFG Insertion | Checksum: 1efeb8a3f

Time (s): cpu = 00:05:39 ; elapsed = 00:03:41 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 576 ; free virtual = 22750

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=-2.928. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b12bf5b1

Time (s): cpu = 00:07:03 ; elapsed = 00:04:52 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 565 ; free virtual = 22740

Time (s): cpu = 00:07:03 ; elapsed = 00:04:52 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 565 ; free virtual = 22740
Phase 4.1 Post Commit Optimization | Checksum: 1b12bf5b1

Time (s): cpu = 00:07:03 ; elapsed = 00:04:52 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 572 ; free virtual = 22747

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1b12bf5b1

Time (s): cpu = 00:07:03 ; elapsed = 00:04:53 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 574 ; free virtual = 22749

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                4x4|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                2x2|                4x4|
|___________|___________________|___________________|
|       West|                1x1|                2x2|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1b12bf5b1

Time (s): cpu = 00:07:04 ; elapsed = 00:04:53 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 569 ; free virtual = 22743
Phase 4.3 Placer Reporting | Checksum: 1b12bf5b1

Time (s): cpu = 00:07:04 ; elapsed = 00:04:53 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 575 ; free virtual = 22750

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 573 ; free virtual = 22748

Time (s): cpu = 00:07:04 ; elapsed = 00:04:53 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 573 ; free virtual = 22748
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ca8c7e79

Time (s): cpu = 00:07:04 ; elapsed = 00:04:53 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 570 ; free virtual = 22745
Ending Placer Task | Checksum: 18d4c95c8

Time (s): cpu = 00:07:04 ; elapsed = 00:04:54 . Memory (MB): peak = 2853.824 ; gain = 7.027 ; free physical = 569 ; free virtual = 22744
38 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:07:08 ; elapsed = 00:04:55 . Memory (MB): peak = 2853.824 ; gain = 39.043 ; free physical = 579 ; free virtual = 22754
# report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
# report_utilization -file digilent_arty_a7_utilization_place.rpt
# report_io -file digilent_arty_a7_io.rpt
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 579 ; free virtual = 22754
# report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 579 ; free virtual = 22754
# report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: b2f2a2ed ConstDB: 0 ShapeSum: da59f2db RouteDB: 0
Post Restoration Checksum: NetGraph: 158bc2c7 | NumContArr: 9fe6bd2 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 1a4dc23d3

Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 531 ; free virtual = 22706

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1a4dc23d3

Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 542 ; free virtual = 22718

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1a4dc23d3

Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 536 ; free virtual = 22712
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 277fbff18

Time (s): cpu = 00:02:05 ; elapsed = 00:01:37 . Memory (MB): peak = 2853.824 ; gain = 0.000 ; free physical = 515 ; free virtual = 22691
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.419 | TNS=-4167.277| WHS=-0.880 | THS=-1368.687|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0237194 %
  Global Horizontal Routing Utilization  = 0.0127167 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 11077
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 11041
  Number of Partially Routed Nets     = 36
  Number of Node Overlaps             = 33

Phase 2 Router Initialization | Checksum: 1e0dda5a6

Time (s): cpu = 00:02:15 ; elapsed = 00:01:43 . Memory (MB): peak = 2858.996 ; gain = 5.172 ; free physical = 509 ; free virtual = 22685

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1e0dda5a6

Time (s): cpu = 00:02:15 ; elapsed = 00:01:43 . Memory (MB): peak = 2858.996 ; gain = 5.172 ; free physical = 509 ; free virtual = 22685

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 15871cfd7

Time (s): cpu = 00:02:44 ; elapsed = 00:01:58 . Memory (MB): peak = 2911.996 ; gain = 58.172 ; free physical = 455 ; free virtual = 22631
Phase 3 Initial Routing | Checksum: 15871cfd7

Time (s): cpu = 00:02:44 ; elapsed = 00:01:58 . Memory (MB): peak = 2911.996 ; gain = 58.172 ; free physical = 455 ; free virtual = 22631
INFO: [Route 35-580] Design has 1288 pins with tight setup and hold constraints.

The top 5 pins with tight setup and hold constraints:

+====================+===================+==================================================+
| Launch Setup Clock | Launch Hold Clock | Pin                                              |
+====================+===================+==================================================+
| sys_clk_pin        | sys_clk_pin       | Processor/N1/First_Stage/IFID_IR_o_reg[6]/R      |
| sys_clk_pin        | sys_clk_pin       | Processor/N1/First_Stage/IFID_IR_o_reg[15]_rep/R |
| sys_clk_pin        | sys_clk_pin       | Processor/N1/First_Stage/IFID_IR_o_reg[26]/R     |
| sys_clk_pin        | sys_clk_pin       | Processor/N1/First_Stage/IFID_IR_o_reg[17]/R     |
| sys_clk_pin        | sys_clk_pin       | Processor/N1/First_Stage/IFID_IR_o_reg[3]/R      |
+--------------------+-------------------+--------------------------------------------------+

File with complete list of pins: tight_setup_hold_pins.txt


Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 3952
 Number of Nodes with overlaps = 837
 Number of Nodes with overlaps = 246
 Number of Nodes with overlaps = 168
 Number of Nodes with overlaps = 79
 Number of Nodes with overlaps = 34
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.832 | TNS=-9299.293| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 16ce2946a

Time (s): cpu = 00:04:54 ; elapsed = 00:03:48 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 420 ; free virtual = 22596

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1799
 Number of Nodes with overlaps = 278
 Number of Nodes with overlaps = 139
 Number of Nodes with overlaps = 50
 Number of Nodes with overlaps = 23
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.574 | TNS=-8669.255| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 220fefae4

Time (s): cpu = 00:05:51 ; elapsed = 00:04:31 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 418 ; free virtual = 22598

Phase 4.3 Global Iteration 2
 Number of Nodes with overlaps = 1639
 Number of Nodes with overlaps = 379
 Number of Nodes with overlaps = 219
 Number of Nodes with overlaps = 75
 Number of Nodes with overlaps = 42
 Number of Nodes with overlaps = 29
 Number of Nodes with overlaps = 21
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 11
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.116 | TNS=-9196.803| WHS=N/A    | THS=N/A    |

Phase 4.3 Global Iteration 2 | Checksum: 30fb07f53

Time (s): cpu = 00:07:17 ; elapsed = 00:05:39 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1026 ; free virtual = 23287
Phase 4 Rip-up And Reroute | Checksum: 30fb07f53

Time (s): cpu = 00:07:17 ; elapsed = 00:05:39 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1023 ; free virtual = 23284

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 3712e03fa

Time (s): cpu = 00:07:23 ; elapsed = 00:05:42 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1022 ; free virtual = 23283
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.557 | TNS=-8584.074| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 171cb2ece

Time (s): cpu = 00:07:24 ; elapsed = 00:05:43 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1012 ; free virtual = 23273

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 171cb2ece

Time (s): cpu = 00:07:24 ; elapsed = 00:05:43 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1010 ; free virtual = 23271
Phase 5 Delay and Skew Optimization | Checksum: 171cb2ece

Time (s): cpu = 00:07:24 ; elapsed = 00:05:43 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1008 ; free virtual = 23269

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1b2115daa

Time (s): cpu = 00:07:32 ; elapsed = 00:05:47 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1018 ; free virtual = 23280
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.398 | TNS=-8253.154| WHS=0.036  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 19155ec99

Time (s): cpu = 00:07:32 ; elapsed = 00:05:47 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1016 ; free virtual = 23278
Phase 6 Post Hold Fix | Checksum: 19155ec99

Time (s): cpu = 00:07:32 ; elapsed = 00:05:47 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1019 ; free virtual = 23280

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 4.25634 %
  Global Horizontal Routing Utilization  = 5.65033 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 72.0721%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 88.2353%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_R_X23Y188 -> INT_R_X23Y188
   INT_L_X24Y188 -> INT_L_X24Y188
   INT_L_X30Y188 -> INT_L_X30Y188
West Dir 1x1 Area, Max Cong = 91.1765%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
   INT_L_X30Y192 -> INT_L_X30Y192
   INT_R_X23Y187 -> INT_R_X23Y187
   INT_L_X28Y186 -> INT_L_X28Y186
   INT_R_X29Y185 -> INT_R_X29Y185
   INT_R_X27Y184 -> INT_R_X27Y184

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 1 Aspect Ratio: 0.666667 Sparse Ratio: 1

Phase 7 Route finalize | Checksum: 19155ec99

Time (s): cpu = 00:07:32 ; elapsed = 00:05:47 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1022 ; free virtual = 23283

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 19155ec99

Time (s): cpu = 00:07:32 ; elapsed = 00:05:47 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1019 ; free virtual = 23280

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1d214ae25

Time (s): cpu = 00:07:37 ; elapsed = 00:05:51 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1018 ; free virtual = 23280

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-4.398 | TNS=-8253.154| WHS=0.036  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 1d214ae25

Time (s): cpu = 00:07:42 ; elapsed = 00:05:53 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1018 ; free virtual = 23279
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 222b1c455

Time (s): cpu = 00:07:43 ; elapsed = 00:05:54 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1024 ; free virtual = 23285
Ending Routing Task | Checksum: 222b1c455

Time (s): cpu = 00:07:44 ; elapsed = 00:05:55 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1014 ; free virtual = 23276

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:07:50 ; elapsed = 00:06:00 . Memory (MB): peak = 2945.996 ; gain = 92.172 ; free physical = 1005 ; free virtual = 23266
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -4.399    -8238.584                   2471                28937        0.035        0.000                      0                28937        3.750        0.000                       0                  6532  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)         Period(ns)      Frequency(MHz)
-----        ------------         ----------      --------------
sck          {0.000 50.000}       100.000         10.000          
sys_clk_pin  {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin        -4.399    -8238.584                   2471                28937        0.035        0.000                      0                28937        3.750        0.000                       0                  6532  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


report_timing_summary: Time (s): cpu = 00:00:22 ; elapsed = 00:00:09 . Memory (MB): peak = 2945.996 ; gain = 0.000 ; free physical = 1032 ; free virtual = 23293
# report_route_status -file digilent_arty_a7_route_status.rpt
# report_drc -file digilent_arty_a7_drc.rpt
Command: report_drc -file digilent_arty_a7_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/digilent_arty_a7_drc.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2978.012 ; gain = 8.004 ; free physical = 1037 ; free virtual = 23299
# report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
report_timing_summary: Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 2978.012 ; gain = 0.000 ; free physical = 879 ; free virtual = 23141
# report_power -file digilent_arty_a7_power.rpt
Command: report_power -file digilent_arty_a7_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 3010.035 ; gain = 32.023 ; free physical = 870 ; free virtual = 23132
# write_bitstream -force "digilent_arty_a7_100t.bit"
Command: write_bitstream -force digilent_arty_a7_100t.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0 output Processor/N1/Second_Stage/Mdu/acumulador0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0__0 output Processor/N1/Second_Stage/Mdu/acumulador0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0__0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador_reg multiplier stage Processor/N1/Second_Stage/Mdu/acumulador_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador_reg__0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_arty_a7_100t.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:48 ; elapsed = 00:00:42 . Memory (MB): peak = 3238.504 ; gain = 228.469 ; free physical = 430 ; free virtual = 22703
# exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr  6 21:44:17 2025...

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] echo
Flashing FPGA digilent_arty_a7_100t.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b digilent_arty_a7_100t -l
Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl
Makefile executed successfully.
Makefile output:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit
empty
Jtag frequency : requested 10.00MHz   -> real 10.00MHz  
Open file DONE
Parse file DONE
load program

Load SRAM: [===============                                   ] 30.00%
Load SRAM: [===============================                   ] 61.00%
Load SRAM: [===============================================   ] 93.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
[Pipeline] echo
Testing FPGA digilent_arty_a7_100t.
[Pipeline] dir
Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyUSB1
Test for FPGA in /dev/ttyUSB1
[Pipeline] sh
+ python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'}
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_arty_a7_100t]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 716515a3-d1e5-4eb2-8db9-2b81503917c4
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: No test report files were found. Configuration error?
Finished: FAILURE