Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/Grande-Risco-5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf Grande-Risco-5 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5 Cloning into 'Grande-Risco-5'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo simulation not supported for System Verilog files [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv Possible cache file: i_cache_test.sv Possible cache file: d_cache_test.sv Cache-related signals in fifo.sv Cache-related signals in uart.sv Possible cache file: cache_request_multiplexer.sv Possible cache file: d_cache.sv Cache-related signals in d_cache.sv Possible cache file: i_cache.sv Results saved to /jenkins/processor_ci_utils/labels/Grande-Risco-5.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] The resource [colorlight_i9] is locked by build Risco-5 #559 #559 since Mar 15, 2025, 1:11 AM. [Resource: colorlight_i9] is not free, waiting for execution ... [Required resources: [colorlight_i9]] added into queue at position 0 [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build Risco-5 #559 #559 since Mar 15, 2025, 1:11 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 1 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b digilent_arty_a7_100t Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096" ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1318.023 ; gain = 0.023 ; free physical = 9413 ; free virtual = 29328 # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv WARNING: [filemgmt 56-12] File '/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv' cannot be added to the project because it already exists in the project, skipping this file # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv # read_verilog -sv /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv # read_verilog /eda/processor_ci/rtl/Grande-Risco-5.v # read_verilog /eda/processor-ci-controller/modules/uart.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog /eda/processor-ci-controller/src/fifo.v # read_verilog /eda/processor-ci-controller/src/reset.v # read_verilog /eda/processor-ci-controller/src/clk_divider.v # read_verilog /eda/processor-ci-controller/src/memory.v # read_verilog /eda/processor-ci-controller/src/interpreter.v # read_verilog /eda/processor-ci-controller/src/controller.v # set ID [lindex $argv 0] # set CLOCK_FREQ [lindex $argv 1] # set MEMORY_SIZE [lindex $argv 2] # set HIGH_CLK 1 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE \ # -verilog_define $HIGH_CLK Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096 -verilog_define 1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 30880 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.777 ; gain = 403.715 ; free physical = 8458 ; free virtual = 28373 --------------------------------------------------------------------------------- CRITICAL WARNING: [Synth 8-9339] data object 'reset_o' is already declared [/eda/processor_ci/rtl/Grande-Risco-5.v:149] INFO: [Synth 8-6826] previous declaration of 'reset_o' is from here [/eda/processor_ci/rtl/Grande-Risco-5.v:29] CRITICAL WARNING: [Synth 8-11152] second declaration of 'reset_o' is ignored [/eda/processor_ci/rtl/Grande-Risco-5.v:149] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15] WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16] WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17] WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84] WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Grande-Risco-5.v:1] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 0 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1] WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268] WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1] WARNING: [Synth 8-7071] port 'core_read_data_memory_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50] WARNING: [Synth 8-7071] port 'core_memory_read_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50] WARNING: [Synth 8-7071] port 'core_memory_write_response_sync' of module 'Controller' is unconnected for instance 'Controller' [/eda/processor_ci/rtl/Grande-Risco-5.v:50] WARNING: [Synth 8-7023] instance 'Controller' of module 'Controller' has 27 connections declared, but only 24 given [/eda/processor_ci/rtl/Grande-Risco-5.v:50] INFO: [Synth 8-6157] synthesizing module 'Grande_Risco5' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1] INFO: [Synth 8-6157] synthesizing module 'Core' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3] Parameter BOOT_ADDRESS bound to: 0 - type: integer Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer INFO: [Synth 8-6157] synthesizing module 'IFID' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3] Parameter BOOT_ADDRESS bound to: 0 - type: integer Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer INFO: [Synth 8-6157] synthesizing module 'IR_Decompression' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:31] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:34] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:76] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:114] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:132] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:198] INFO: [Synth 8-6155] done synthesizing module 'IR_Decompression' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:216] INFO: [Synth 8-6157] synthesizing module 'Branch_Prediction' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1] Parameter BRANCH_PREDICTION_SIZE bound to: 512 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Branch_Prediction' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1] INFO: [Synth 8-6157] synthesizing module 'Invalid_IR_Check' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:16] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:18] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:24] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:33] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:45] INFO: [Synth 8-6155] done synthesizing module 'Invalid_IR_Check' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1] INFO: [Synth 8-6155] done synthesizing module 'IFID' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3] INFO: [Synth 8-6157] synthesizing module 'IDEX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:26] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:30] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:41] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:41] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:29] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1] INFO: [Synth 8-6157] synthesizing module 'Forwarding_Unit' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Forwarding_Unit' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:11] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1] INFO: [Synth 8-6157] synthesizing module 'MDU' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4] INFO: [Synth 8-6155] done synthesizing module 'MDU' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4] INFO: [Synth 8-6155] done synthesizing module 'IDEX' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3] INFO: [Synth 8-6157] synthesizing module 'EXMEM' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:97] INFO: [Synth 8-6155] done synthesizing module 'EXMEM' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3] INFO: [Synth 8-6157] synthesizing module 'MEMWB' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:73] INFO: [Synth 8-6155] done synthesizing module 'MEMWB' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1] INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:88] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:100] INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3] INFO: [Synth 8-6157] synthesizing module 'ICache' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1] Parameter CACHE_SIZE bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ICache' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1] INFO: [Synth 8-6157] synthesizing module 'DCache' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1] Parameter CACHE_SIZE bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'DCache' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1] INFO: [Synth 8-6157] synthesizing module 'Cache_request_Multiplexer' [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1] Parameter DATA_WIDTH bound to: 32 - type: integer Parameter ADDR_WIDTH bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Cache_request_Multiplexer' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Grande_Risco5' (0#1) [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Grande-Risco-5.v:153] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Grande-Risco-5.v:153] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/Grande-Risco-5.v:153] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Grande-Risco-5.v:1] WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25] WARNING: [Synth 8-6014] Unused sequential element jump_is_predicted_reg was removed. [/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:87] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Grande-Risco-5.v:21] WARNING: [Synth 8-7129] Port invalid_fetch_instruction in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port invalid_decode_instruction in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[31] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[30] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[29] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[28] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[27] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[26] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[25] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[24] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[23] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[22] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[21] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[20] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[19] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[18] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[17] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[16] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[15] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[14] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[13] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[12] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[11] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[10] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[9] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[8] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[7] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[6] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[5] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[4] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[3] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[2] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[1] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port fetch_pc[0] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[31] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[30] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[29] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[28] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[27] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[26] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[25] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[24] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[23] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[22] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[21] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[20] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[19] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[18] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[17] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[16] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[15] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[14] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[13] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[12] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[11] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[10] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[9] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[8] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[7] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[6] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[5] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[4] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[3] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[2] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[1] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port decode_pc[0] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[31] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[30] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[29] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[28] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[27] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[26] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[25] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[24] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[23] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[22] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[21] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[20] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[19] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[18] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[17] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[16] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[15] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[14] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[13] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[12] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[11] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[10] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[9] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[8] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[7] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[6] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[5] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[4] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[3] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[2] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[1] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port execute_pc[0] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_pc[31] in module CSR_Unit is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_pc[30] in module CSR_Unit is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2304.887 ; gain = 675.824 ; free physical = 8639 ; free virtual = 28608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2319.730 ; gain = 690.668 ; free physical = 8638 ; free virtual = 28607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2319.730 ; gain = 690.668 ; free physical = 8638 ; free virtual = 28607 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2319.730 ; gain = 0.000 ; free physical = 8649 ; free virtual = 28619 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2453.480 ; gain = 0.000 ; free physical = 8609 ; free virtual = 28579 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2453.516 ; gain = 0.000 ; free physical = 8603 ; free virtual = 28573 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 8588 ; free virtual = 28558 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 8588 ; free virtual = 28558 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 8588 ; free virtual = 28558 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_mul_reg' in module 'MDU' INFO: [Synth 8-802] inferred FSM for state register 'state_div_reg' in module 'MDU' INFO: [Synth 8-802] inferred FSM for state register 'unaligned_access_state_reg' in module 'EXMEM' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0001 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- MUL_IDLE | 001 | 00 MUL_OPERATE | 010 | 01 MUL_FINISH | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_mul_reg' using encoding 'one-hot' in module 'MDU' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 READ_WORD_TO_SUBSW | 0001 | 1011 MODIFY_WORD_TO_SUBSW | 0010 | 1100 READ_FIRST_WORD | 0011 | 0001 READ_SECOND_WORD | 0100 | 0010 MERGE_WORDS | 0101 | 0011 CUT_WORDS | 0110 | 1010 READ_FIRST_WORD_TO_WRITE | 0111 | 0100 MODIFY_FIRST_WORD_SUB | 1000 | 1110 WRITE_SUBSW | 1001 | 1101 MODIFY_FIRST_WORD | 1010 | 0101 WRITE_FIRST_WORD | 1011 | 0110 READ_SECOND_WORD_TO_WRITE | 1100 | 0111 MODIFY_SECOND_WORD_SUB | 1101 | 1111 MODIFY_SECOND_WORD | 1110 | 1000 WRITE_SECOND_WORD | 1111 | 1001 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'unaligned_access_state_reg' using encoding 'sequential' in module 'EXMEM' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 8593 ; free virtual = 28568 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 19 3 Input 32 Bit Adders := 2 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 3 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 64 Bit Registers := 3 63 Bit Registers := 1 32 Bit Registers := 88 24 Bit Registers := 5 16 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 4 Bit Registers := 3 3 Bit Registers := 2 2 Bit Registers := 512 1 Bit Registers := 85 +---Multipliers : 32x32 Multipliers := 1 +---RAMs : 32K Bit (1024 X 32 bit) RAMs := 2 256 Bit (8 X 32 bit) RAMs := 2 216 Bit (8 X 27 bit) RAMs := 2 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 4 Input 63 Bit Muxes := 1 2 Input 32 Bit Muxes := 59 3 Input 32 Bit Muxes := 6 4 Input 32 Bit Muxes := 13 8 Input 32 Bit Muxes := 2 7 Input 32 Bit Muxes := 1 5 Input 32 Bit Muxes := 4 16 Input 32 Bit Muxes := 5 14 Input 32 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 2 Input 9 Bit Muxes := 2 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 4 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 16 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 9 25 Input 4 Bit Muxes := 1 10 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 5 5 Input 3 Bit Muxes := 4 2 Input 2 Bit Muxes := 22 4 Input 2 Bit Muxes := 5 3 Input 2 Bit Muxes := 4 48 Input 2 Bit Muxes := 1 7 Input 1 Bit Muxes := 2 2 Input 1 Bit Muxes := 3232 5 Input 1 Bit Muxes := 14 8 Input 1 Bit Muxes := 1 13 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 9 6 Input 1 Bit Muxes := 3 3 Input 1 Bit Muxes := 9 16 Input 1 Bit Muxes := 9 9 Input 1 Bit Muxes := 7 48 Input 1 Bit Muxes := 22 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met DSP Report: Generating DSP acumulador0, operation Mode is: A2*B. DSP Report: register acumulador0 is absorbed into DSP acumulador0. DSP Report: operator acumulador0 is absorbed into DSP acumulador0. DSP Report: operator acumulador0 is absorbed into DSP acumulador0. DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B. DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg. DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg. DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg. DSP Report: Generating DSP acumulador0, operation Mode is: A2*B2. DSP Report: register acumulador0 is absorbed into DSP acumulador0. DSP Report: register acumulador0 is absorbed into DSP acumulador0. DSP Report: operator acumulador0 is absorbed into DSP acumulador0. DSP Report: operator acumulador0 is absorbed into DSP acumulador0. DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A2*B. DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg. DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg. DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg. DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[47]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[46]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[45]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[44]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[43]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[42]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[41]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[40]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[39]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[38]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[37]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[36]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[35]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[34]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[33]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[32]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[31]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[30]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[29]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[28]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[27]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[26]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[25]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[24]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[23]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[22]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[21]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[20]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[19]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[18]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[17]) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[47]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[46]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[45]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[44]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[43]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[42]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[41]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[40]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[39]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[38]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[37]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[36]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[35]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[34]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[33]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[32]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[31]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[30]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[29]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[28]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[27]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[26]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[25]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[24]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[23]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[22]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[21]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[20]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[19]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[18]__0) is unused and will be removed from module IDEX. WARNING: [Synth 8-3332] Sequential element (Mdu/acumulador_reg[17]__0) is unused and will be removed from module IDEX. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7894 ; free virtual = 27913 --------------------------------------------------------------------------------- Sort Area is Core__GB1 acumulador0_3 : 0 0 : 2737 4966 : Used 1 time 0 Sort Area is Core__GB1 acumulador0_3 : 0 1 : 2229 4966 : Used 1 time 0 Sort Area is Core__GB1 acumulador0_0 : 0 0 : 2176 4080 : Used 1 time 0 Sort Area is Core__GB1 acumulador0_0 : 0 1 : 1904 4080 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ |\Processor/N1/First_Stage /Branch_Prediction | address_to_jump_reg | Implied | 512 x 32 | RAM64M x 264 | |processorci_top | ICache/cache_tag_reg | Implied | 8 x 27 | RAM16X1S x 27 | |processorci_top | ICache/cache_data_reg | Implied | 8 x 32 | RAM16X1S x 32 | |processorci_top | DCache/cache_tag_reg | Implied | 8 x 27 | RAM16X1S x 27 | |processorci_top | DCache/cache_data_reg | Implied | 8 x 32 | RAM16X1S x 32 | |processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |MDU | A2*B | 18 | 15 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | |MDU | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 | |MDU | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | |MDU | (PCIN>>17)+A2*B | 18 | 15 | - | - | 48 | 1 | 0 | - | - | - | 0 | 1 | +------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:43 ; elapsed = 00:01:44 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7903 ; free virtual = 27924 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:56 ; elapsed = 00:01:58 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7872 ; free virtual = 27891 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ |\Processor/N1/First_Stage /Branch_Prediction | address_to_jump_reg | Implied | 512 x 32 | RAM64M x 264 | |processorci_top | ICache/cache_tag_reg | Implied | 8 x 27 | RAM16X1S x 27 | |processorci_top | ICache/cache_data_reg | Implied | 8 x 32 | RAM16X1S x 32 | |processorci_top | DCache/cache_tag_reg | Implied | 8 x 27 | RAM16X1S x 27 | |processorci_top | DCache/cache_data_reg | Implied | 8 x 32 | RAM16X1S x 32 | |processorci_top | Controller/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |processorci_top | Controller/Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | |processorci_top | Controller/Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +---------------------------------------------+------------------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:02:03 ; elapsed = 00:02:04 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7779 ; free virtual = 27798 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7517 ; free virtual = 27536 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7514 ; free virtual = 27533 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:10 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7459 ; free virtual = 27478 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:10 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7461 ; free virtual = 27480 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7439 ; free virtual = 27479 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7436 ; free virtual = 27479 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- DSP Final Report (the ' indicates corresponding REG is set) +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |MDU | A'*B' | 17 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | |MDU | (PCIN>>17+A'*B')' | 30 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | |MDU | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | |MDU | (PCIN>>17+A'*B')' | 17 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 279| |3 |DSP48E1 | 4| |5 |LUT1 | 171| |6 |LUT2 | 651| |7 |LUT3 | 1496| |8 |LUT4 | 763| |9 |LUT5 | 922| |10 |LUT6 | 4139| |11 |MUXF7 | 660| |12 |MUXF8 | 35| |13 |RAM16X1S | 118| |14 |RAM256X1S | 256| |15 |RAM32M | 2| |16 |RAM32X1D | 4| |17 |RAM64M | 264| |18 |FDRE | 4229| |19 |FDSE | 67| |20 |IBUF | 2| |21 |OBUF | 2| |22 |OBUFT | 1| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7435 ; free virtual = 27479 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 64 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:02:06 ; elapsed = 00:02:08 . Memory (MB): peak = 2453.516 ; gain = 690.668 ; free physical = 7432 ; free virtual = 27479 Synthesis Optimization Complete : Time (s): cpu = 00:02:11 ; elapsed = 00:02:12 . Memory (MB): peak = 2453.516 ; gain = 824.453 ; free physical = 7432 ; free virtual = 27479 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2453.516 ; gain = 0.000 ; free physical = 8360 ; free virtual = 28407 INFO: [Netlist 29-17] Analyzing 1622 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2517.512 ; gain = 0.000 ; free physical = 8266 ; free virtual = 28313 INFO: [Project 1-111] Unisim Transformation Summary: A total of 644 instances were transformed. RAM16X1S => RAM32X1S (RAMS32): 118 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances RAM64M => RAM64M (RAMD64E(x4)): 264 instances Synth Design complete | Checksum: 73ab8f31 INFO: [Common 17-83] Releasing license: Synthesis 117 Infos, 186 Warnings, 4 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:22 ; elapsed = 00:02:21 . Memory (MB): peak = 2517.547 ; gain = 1199.523 ; free physical = 8266 ; free virtual = 28313 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2225.327; main = 1936.407; forked = 429.565 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3403.801; main = 2517.516; forked = 982.332 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.77 . Memory (MB): peak = 2581.543 ; gain = 63.996 ; free physical = 8264 ; free virtual = 28311 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1a1712bbd Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2581.543 ; gain = 0.000 ; free physical = 8245 ; free virtual = 28292 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1a1712bbd Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8034 ; free virtual = 28081 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a1712bbd Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8033 ; free virtual = 28080 Phase 1 Initialization | Checksum: 1a1712bbd Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8033 ; free virtual = 28080 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1a1712bbd Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8034 ; free virtual = 28081 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1a1712bbd Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Phase 2 Timer Update And Timing Data Collection | Checksum: 1a1712bbd Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1a1712bbd Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8036 ; free virtual = 28083 Retarget | Checksum: 1a1712bbd INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 2064f16cc Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Constant propagation | Checksum: 2064f16cc INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 188138c92 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2784.543 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Sweep | Checksum: 188138c92 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 188138c92 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 BUFG optimization | Checksum: 188138c92 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 188138c92 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 Shift Register Optimization | Checksum: 188138c92 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 188138c92 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 Post Processing Netlist | Checksum: 188138c92 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2455ce1ac Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2455ce1ac Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 Phase 9 Finalization | Checksum: 2455ce1ac Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 2455ce1ac Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2816.559 ; gain = 32.016 ; free physical = 8037 ; free virtual = 28084 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 2455ce1ac Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 2455ce1ac Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Ending Netlist Obfuscation Task | Checksum: 2455ce1ac Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2816.559 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2816.559 ; gain = 299.012 ; free physical = 8037 ; free virtual = 28084 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2848.574 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e7f28bbb Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2848.574 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2848.574 ; gain = 0.000 ; free physical = 8037 ; free virtual = 28084 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19764a2c3 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2848.574 ; gain = 0.000 ; free physical = 8026 ; free virtual = 28073 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 27de78e1d Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8016 ; free virtual = 28063 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 27de78e1d Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8016 ; free virtual = 28063 Phase 1 Placer Initialization | Checksum: 27de78e1d Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8016 ; free virtual = 28063 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 232edb4df Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8021 ; free virtual = 28068 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 22f5c0e4f Time (s): cpu = 00:00:23 ; elapsed = 00:00:08 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8032 ; free virtual = 28079 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 22f5c0e4f Time (s): cpu = 00:00:23 ; elapsed = 00:00:08 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8032 ; free virtual = 28079 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1b621fcf1 Time (s): cpu = 00:01:05 ; elapsed = 00:00:20 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8029 ; free virtual = 28076 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 121 LUTNM shape to break, 230 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 33, two critical 88, total 121, new lutff created 3 INFO: [Physopt 32-1138] End 1 Pass. Optimized 215 nets or LUTs. Breaked 121 LUTs, combined 94 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 8021 ; free virtual = 28068 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 121 | 94 | 215 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 121 | 94 | 215 | 0 | 9 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4165597 Time (s): cpu = 00:01:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8033 ; free virtual = 28080 Phase 2.4 Global Placement Core | Checksum: 13a414704 Time (s): cpu = 00:01:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8033 ; free virtual = 28080 Phase 2 Global Placement | Checksum: 13a414704 Time (s): cpu = 00:01:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8033 ; free virtual = 28080 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: b8cefff2 Time (s): cpu = 00:01:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8032 ; free virtual = 28079 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 197020e54 Time (s): cpu = 00:01:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8042 ; free virtual = 28089 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 160046903 Time (s): cpu = 00:01:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8044 ; free virtual = 28091 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 11199a8f8 Time (s): cpu = 00:01:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8044 ; free virtual = 28091 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 10ba2e0a2 Time (s): cpu = 00:01:47 ; elapsed = 00:00:35 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8022 ; free virtual = 28069 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 104c74f76 Time (s): cpu = 00:01:52 ; elapsed = 00:00:40 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 8028 ; free virtual = 28075 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 1399357ae Time (s): cpu = 00:01:53 ; elapsed = 00:00:41 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7907 ; free virtual = 27954 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: d4f27de8 Time (s): cpu = 00:01:53 ; elapsed = 00:00:41 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7907 ; free virtual = 27954 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 1a73880ec Time (s): cpu = 00:02:15 ; elapsed = 00:00:52 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7857 ; free virtual = 27904 Phase 3 Detail Placement | Checksum: 1a73880ec Time (s): cpu = 00:02:15 ; elapsed = 00:00:52 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7857 ; free virtual = 27904 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1691fae53 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-5.341 | TNS=-8613.585 | Phase 1 Physical Synthesis Initialization | Checksum: 19070d386 Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7887 ; free virtual = 27934 INFO: [Place 46-33] Processed net Controller/Interpreter/core_reset_reg_0, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 19070d386 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7887 ; free virtual = 27934 Phase 4.1.1.1 BUFG Insertion | Checksum: 1691fae53 Time (s): cpu = 00:02:31 ; elapsed = 00:00:57 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7887 ; free virtual = 27934 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=-3.373. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d853df05 Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7852 ; free virtual = 27900 Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7852 ; free virtual = 27900 Phase 4.1 Post Commit Optimization | Checksum: 1d853df05 Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7856 ; free virtual = 27903 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1d853df05 Time (s): cpu = 00:03:16 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7855 ; free virtual = 27902 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 2x2| 1x1| |___________|___________________|___________________| | West| 2x2| 2x2| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1d853df05 Time (s): cpu = 00:03:17 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7855 ; free virtual = 27902 Phase 4.3 Placer Reporting | Checksum: 1d853df05 Time (s): cpu = 00:03:17 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7854 ; free virtual = 27901 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7852 ; free virtual = 27900 Time (s): cpu = 00:03:17 ; elapsed = 00:01:31 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7852 ; free virtual = 27900 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 236c4f488 Time (s): cpu = 00:03:17 ; elapsed = 00:01:32 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7858 ; free virtual = 27905 Ending Placer Task | Checksum: 1df40cae2 Time (s): cpu = 00:03:17 ; elapsed = 00:01:32 . Memory (MB): peak = 2855.602 ; gain = 7.027 ; free physical = 7857 ; free virtual = 27904 38 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:03:19 ; elapsed = 00:01:32 . Memory (MB): peak = 2855.602 ; gain = 39.043 ; free physical = 7857 ; free virtual = 27904 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7858 ; free virtual = 27905 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7858 ; free virtual = 27905 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: f20fab0e ConstDB: 0 ShapeSum: ed311fd4 RouteDB: 0 Post Restoration Checksum: NetGraph: 278f3f53 | NumContArr: b9016d23 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 265e2a1b0 Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7870 ; free virtual = 27917 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 265e2a1b0 Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7870 ; free virtual = 27917 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 265e2a1b0 Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7870 ; free virtual = 27917 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2825dba74 Time (s): cpu = 00:00:59 ; elapsed = 00:00:33 . Memory (MB): peak = 2855.602 ; gain = 0.000 ; free physical = 7852 ; free virtual = 27900 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.956 | TNS=-4791.185| WHS=-0.819 | THS=-1394.239| Router Utilization Summary Global Vertical Routing Utilization = 0.0127084 % Global Horizontal Routing Utilization = 0.00937766 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 11071 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 11035 Number of Partially Routed Nets = 36 Number of Node Overlaps = 34 Phase 2 Router Initialization | Checksum: 275fb3ded Time (s): cpu = 00:01:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2859.523 ; gain = 3.922 ; free physical = 7845 ; free virtual = 27893 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 275fb3ded Time (s): cpu = 00:01:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2859.523 ; gain = 3.922 ; free physical = 7845 ; free virtual = 27893 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 3743fa785 Time (s): cpu = 00:01:21 ; elapsed = 00:00:39 . Memory (MB): peak = 2881.523 ; gain = 25.922 ; free physical = 7828 ; free virtual = 27875 Phase 3 Initial Routing | Checksum: 3743fa785 Time (s): cpu = 00:01:21 ; elapsed = 00:00:39 . Memory (MB): peak = 2881.523 ; gain = 25.922 ; free physical = 7827 ; free virtual = 27875 INFO: [Route 35-580] Design has 1289 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +====================+===================+====================================================+ | Launch Setup Clock | Launch Hold Clock | Pin | +====================+===================+====================================================+ | sys_clk_pin | sys_clk_pin | Processor/N1/First_Stage/IFID_IR_o_reg[3]/R | | sys_clk_pin | sys_clk_pin | Processor/N1/First_Stage/finish_unaligned_pc_reg/D | | sys_clk_pin | sys_clk_pin | Processor/N1/First_Stage/IFID_PC_o_reg[23]/R | | sys_clk_pin | sys_clk_pin | Processor/N1/First_Stage/IFID_PC_o_reg[24]/R | | sys_clk_pin | sys_clk_pin | Processor/N1/First_Stage/IFID_PC_o_reg[11]/R | +--------------------+-------------------+----------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 3686 Number of Nodes with overlaps = 709 Number of Nodes with overlaps = 261 Number of Nodes with overlaps = 144 Number of Nodes with overlaps = 88 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 29 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.778 | TNS=-8994.112| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 261846044 Time (s): cpu = 00:02:23 ; elapsed = 00:01:16 . Memory (MB): peak = 2881.523 ; gain = 25.922 ; free physical = 7767 ; free virtual = 27815 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 2034 Number of Nodes with overlaps = 631 Number of Nodes with overlaps = 189 Number of Nodes with overlaps = 106 Number of Nodes with overlaps = 41 Number of Nodes with overlaps = 32 Number of Nodes with overlaps = 22 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.687 | TNS=-8825.411| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 1d69214fe Time (s): cpu = 00:03:26 ; elapsed = 00:01:51 . Memory (MB): peak = 2881.523 ; gain = 25.922 ; free physical = 7767 ; free virtual = 27823 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 1910 Number of Nodes with overlaps = 425 Number of Nodes with overlaps = 284 Number of Nodes with overlaps = 82 Number of Nodes with overlaps = 74 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-5.193 | TNS=-9737.661| WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 1834223d9 Time (s): cpu = 00:04:30 ; elapsed = 00:02:23 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 Phase 4 Rip-up And Reroute | Checksum: 1834223d9 Time (s): cpu = 00:04:30 ; elapsed = 00:02:23 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 16707376c Time (s): cpu = 00:04:33 ; elapsed = 00:02:24 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.679 | TNS=-8779.914| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 298ad2988 Time (s): cpu = 00:04:34 ; elapsed = 00:02:24 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 298ad2988 Time (s): cpu = 00:04:34 ; elapsed = 00:02:24 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 Phase 5 Delay and Skew Optimization | Checksum: 298ad2988 Time (s): cpu = 00:04:34 ; elapsed = 00:02:24 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27808 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 242daa966 Time (s): cpu = 00:04:39 ; elapsed = 00:02:26 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-4.655 | TNS=-8747.078| WHS=0.042 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 296eacc34 Time (s): cpu = 00:04:39 ; elapsed = 00:02:26 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 Phase 6 Post Hold Fix | Checksum: 296eacc34 Time (s): cpu = 00:04:39 ; elapsed = 00:02:26 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 4.46381 % Global Horizontal Routing Utilization = 5.45588 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 70.2703%, No Congested Regions. South Dir 1x1 Area, Max Cong = 76.5766%, No Congested Regions. East Dir 1x1 Area, Max Cong = 86.7647%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_L_X32Y153 -> INT_L_X32Y153 INT_R_X35Y149 -> INT_R_X35Y149 West Dir 1x1 Area, Max Cong = 86.7647%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X31Y158 -> INT_R_X31Y158 INT_R_X45Y149 -> INT_R_X45Y149 ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Phase 7 Route finalize | Checksum: 296eacc34 Time (s): cpu = 00:04:39 ; elapsed = 00:02:26 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 296eacc34 Time (s): cpu = 00:04:39 ; elapsed = 00:02:26 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 26cd5361f Time (s): cpu = 00:04:42 ; elapsed = 00:02:27 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7752 ; free virtual = 27807 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-4.655 | TNS=-8747.078| WHS=0.042 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 26cd5361f Time (s): cpu = 00:04:45 ; elapsed = 00:02:28 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7750 ; free virtual = 27805 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1bdfaa56e Time (s): cpu = 00:04:46 ; elapsed = 00:02:28 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7750 ; free virtual = 27806 Ending Routing Task | Checksum: 1bdfaa56e Time (s): cpu = 00:04:46 ; elapsed = 00:02:28 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7750 ; free virtual = 27806 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:04:49 ; elapsed = 00:02:30 . Memory (MB): peak = 2898.523 ; gain = 42.922 ; free physical = 7743 ; free virtual = 27798 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -4.656 -8747.004 3089 28935 0.042 0.000 0 28935 3.750 0.000 0 6522 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -4.656 -8747.004 3089 28935 0.042 0.000 0 28935 3.750 0.000 0 6522 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0 output Processor/N1/Second_Stage/Mdu/acumulador0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0__0 output Processor/N1/Second_Stage/Mdu/acumulador0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador0__0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador_reg multiplier stage Processor/N1/Second_Stage/Mdu/acumulador_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP Processor/N1/Second_Stage/Mdu/acumulador_reg__0 multiplier stage Processor/N1/Second_Stage/Mdu/acumulador_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:23 . Memory (MB): peak = 3239.898 ; gain = 230.465 ; free physical = 7362 ; free virtual = 27452 # exit INFO: [Common 17-206] Exiting Vivado at Fri Mar 14 21:23:34 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b digilent_arty_a7_100t -l Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [================ ] 31.00% Load SRAM: [================================ ] 63.00% Load SRAM: [================================================ ] 95.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv:8:28: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 2. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:49:59: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 3. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:50:74: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 4. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:81:40: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 5. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:25:22: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 6. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:74:63: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 7. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:77:11: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 8. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 9. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:6:72: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 10. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 11. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:46:95: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 12. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:130:63: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 13. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 14. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:3:77: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 15. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 16. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:7:60: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 17. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220:77: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 18. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 19. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 20. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:7:60: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 21. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 0 22. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:222:8: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 23. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/Grande-Risco-5.v Parsing Verilog input from `/eda/processor_ci/rtl/Grande-Risco-5.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 24. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/slpp_all/surelog.log". [INF:CP0300] Compilation... [INF:CP0301] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/grande_risco5_types.sv:3:1: Compile package "opcodes_pkg". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:1:1: Compile module "work@ALU_Control". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:1:1: Compile module "work@Alu". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:1:1: Compile module "work@Branch_Prediction". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:1:1: Compile module "work@CSR_Unit". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:1:1: Compile module "work@Cache_request_Multiplexer". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:3:1: Compile module "work@Core". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:1:1: Compile module "work@DCache". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:3:1: Compile module "work@EXMEM". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:1:1: Compile module "work@Forwarding_Unit". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1:1: Compile module "work@Grande_Risco5". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:1:1: Compile module "work@ICache". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:3:1: Compile module "work@IDEX". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:3:1: Compile module "work@IFID". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:3:1: Compile module "work@IR_Decompression". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:1:1: Compile module "work@Immediate_Generator". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:1:1: Compile module "work@Invalid_IR_Check". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:4:1: Compile module "work@MDU". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:3:1: Compile module "work@MEMWB". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:1:1: Compile module "work@MUX". [INF:CP0303] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:1:1: Compile module "work@Registers". [INF:EL0526] Design Elaboration... [NTE:EL0503] /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/Grande_Risco5.sv:1:1: Top level module "work@Grande_Risco5". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 4. [NTE:EL0510] Nb instances: 21. [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 5 Generating RTLIL representation for module `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000'. Generating RTLIL representation for module `\CSR_Unit'. Generating RTLIL representation for module `\Registers'. Generating RTLIL representation for module `\EXMEM'. Generating RTLIL representation for module `\MDU'. Generating RTLIL representation for module `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core'. Generating RTLIL representation for module `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000'. Generating RTLIL representation for module `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID'. Generating RTLIL representation for module `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000'. Generating RTLIL representation for module `\IDEX'. Generating RTLIL representation for module `\IR_Decompression'. Generating RTLIL representation for module `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer'. Generating RTLIL representation for module `\Invalid_IR_Check'. Generating RTLIL representation for module `\ALU_Control'. Generating RTLIL representation for module `\MEMWB'. Generating RTLIL representation for module `\Alu'. Generating RTLIL representation for module `\Grande_Risco5'. Generating RTLIL representation for module `\Immediate_Generator'. Generating RTLIL representation for module `\Forwarding_Unit'. Generating RTLIL representation for module `\MUX'. 25. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 34. Executing SYNTH_ECP5 pass. 34.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 34.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 34.3. Executing HIERARCHY pass (managing design hierarchy). 34.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \Grande_Risco5 Used module: $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer Used module: $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core Used module: \CSR_Unit Used module: \Registers Used module: \MEMWB Used module: \EXMEM Used module: \IDEX Used module: \MDU Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID Used module: \Invalid_IR_Check Used module: $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000 Used module: \IR_Decompression Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \CYCLES = 20 34.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 34.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 34.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 34.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 34.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 34.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 34.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 34.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 34.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 34.3.11. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer Used module: $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core Used module: \CSR_Unit Used module: \Registers Used module: \MEMWB Used module: \EXMEM Used module: \IDEX Used module: \MDU Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID Used module: \Invalid_IR_Check Used module: $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000 Used module: \IR_Decompression Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 34.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 34.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 34.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 34.3.15. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer Used module: $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core Used module: \CSR_Unit Used module: \Registers Used module: \MEMWB Used module: \EXMEM Used module: \IDEX Used module: \MDU Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID Used module: \Invalid_IR_Check Used module: $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000 Used module: \IR_Decompression Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 34.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 34.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 34.3.18. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer Used module: $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core Used module: \CSR_Unit Used module: \Registers Used module: \MEMWB Used module: \EXMEM Used module: \IDEX Used module: \MDU Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID Used module: \Invalid_IR_Check Used module: $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000 Used module: \IR_Decompression Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 34.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \Grande_Risco5 Used module: $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer Used module: $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000 Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core Used module: \CSR_Unit Used module: \Registers Used module: \MEMWB Used module: \EXMEM Used module: \IDEX Used module: \MDU Used module: \MUX Used module: \Forwarding_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID Used module: \Invalid_IR_Check Used module: $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000 Used module: \IR_Decompression Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removed 14 unused modules. 34.4. Executing PROC pass (convert processes to netlists). 34.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1031'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1213'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1213'. Cleaned up 2 empty switches. 34.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1138 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1393 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1385 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1584 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1576 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1573 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1567 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1557 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1548 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1535 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1533 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1525 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1511 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1500 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1487 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1442 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1434 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1434 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1429 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1424 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1419 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$1202 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$1191 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$1141 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633 in module MUX. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633 in module MUX. Marked 6 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620 in module Forwarding_Unit. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$619 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$583 in module Alu. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554 in module MEMWB. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:72$550 in module MEMWB. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545 in module ALU_Control. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545 in module ALU_Control. Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$542 in module Invalid_IR_Check. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533 in module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer. Removed 6 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520 in module IR_Decompression. Marked 17 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520 in module IR_Decompression. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488 in module IDEX. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478 in module IDEX. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477 in module IDEX. Marked 9 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349 in module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000. Marked 11 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299 in module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$292 in module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224 in module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194 in module MDU. Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158 in module MDU. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104 in module EXMEM. Marked 16 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104 in module EXMEM. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91 in module Registers. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64 in module CSR_Unit. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17 in module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000. Removed a total of 10 dead cases. 34.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 9 redundant assignments. Promoted 159 assignments to connections. 34.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1139'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1418'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1588'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1541'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1493'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1471'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1441'. Set init value: \read_response = 1'0 Set init value: \read_data = 0 Set init value: \write_response = 1'0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1148'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 34.4.5. Executing PROC_ARST pass (detect async resets in processes). 34.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~232 debug messages> 34.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1139'. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1138'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090'. 1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_EN[3:0]$1096 2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_DATA[3:0]$1095 3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_ADDR[3:0]$1094 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_EN[3:0]$1038 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_DATA[3:0]$1037 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_ADDR[3:0]$1036 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1031'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1418'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1405 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_DATA[7:0]$1404 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1403 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1399 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_DATA[7:0]$1398 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1397 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1385'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1588'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1584'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1576'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1573'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1567'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1557'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1548'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1541'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1535'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1533'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1525'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1511'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1500'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1493'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1487'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1471'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\address[31:0] 27/28: $0\counter[7:0] 28/28: $0\write_data[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1441'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1429'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1212'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1211 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_DATA[31:0]$1210 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_ADDR[31:0]$1209 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1191'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1148'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633'. 1/1: $1\S_o[31:0] Creating decoders for process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620'. 1/6: $3\fwd_rs2_o[1:0] 2/6: $2\fwd_rs2_o[1:0] 3/6: $1\fwd_rs2_o[1:0] 4/6: $3\fwd_rs1_o[1:0] 5/6: $2\fwd_rs1_o[1:0] 6/6: $1\fwd_rs1_o[1:0] Creating decoders for process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$619'. 1/2: $2\imm_o[31:0] 2/2: $1\imm_o[31:0] Creating decoders for process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$583'. 1/1: $1\ALU_RD_o[31:0] Creating decoders for process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. 1/7: $0\MEMWB_IR[31:0] 2/7: $0\instruction_finished_o[0:0] 3/7: $0\mem_to_reg[0:0] 4/7: $0\reg_wr_en_o[0:0] 5/7: $0\MEMWBALUOut[31:0] 6/7: $0\MEMWB_mem_read_data[31:0] 7/7: $0\MEMWB_PC_o[31:0] Creating decoders for process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:72$550'. 1/1: $1\read_data_normalized[31:0] Creating decoders for process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545'. 1/3: $3\ALU_OP_o[3:0] 2/3: $2\ALU_OP_o[3:0] 3/3: $1\ALU_OP_o[3:0] Creating decoders for process `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$542'. 1/5: $5\invalid_instruction_o[0:0] 2/5: $4\invalid_instruction_o[0:0] 3/5: $3\invalid_instruction_o[0:0] 4/5: $2\invalid_instruction_o[0:0] 5/5: $1\invalid_instruction_o[0:0] Creating decoders for process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. 1/10: $0\d_cache_response[0:0] 2/10: $0\i_cache_response[0:0] 3/10: $0\d_cache_read_data[31:0] 4/10: $0\i_cache_read_data[31:0] 5/10: $0\access_pedding[0:0] 6/10: $0\response_out[0:0] 7/10: $0\requested_memory_addr[31:0] 8/10: $0\write_request[0:0] 9/10: $0\write_data[31:0] 10/10: $0\read_request[0:0] Creating decoders for process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520'. 1/25: $11\instr_d_o[31:0] 2/25: $10\instr_d_o[31:0] 3/25: $14\instr_illegal_o[0:0] 4/25: $9\instr_d_o[31:0] 5/25: $13\instr_illegal_o[0:0] 6/25: $12\instr_illegal_o[0:0] 7/25: $8\instr_d_o[31:0] 8/25: $11\instr_illegal_o[0:0] 9/25: $10\instr_illegal_o[0:0] 10/25: $9\instr_illegal_o[0:0] 11/25: $7\instr_d_o[31:0] 12/25: $6\instr_d_o[31:0] 13/25: $8\instr_illegal_o[0:0] 14/25: $7\instr_illegal_o[0:0] 15/25: $6\instr_illegal_o[0:0] 16/25: $5\instr_d_o[31:0] 17/25: $5\instr_illegal_o[0:0] 18/25: $4\instr_d_o[31:0] 19/25: $3\instr_d_o[31:0] 20/25: $4\instr_illegal_o[0:0] 21/25: $3\instr_illegal_o[0:0] 22/25: $2\instr_illegal_o[0:0] 23/25: $2\instr_d_o[31:0] 24/25: $1\instr_illegal_o[0:0] 25/25: $1\instr_d_o[31:0] Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. 1/8: $0\previous_instruction_is_lw[0:0] 2/8: $0\mdu_start[0:0] 3/8: $0\IDEXB[31:0] 4/8: $0\IDEXA[31:0] 5/8: $0\alu_op_o[3:0] 6/8: $0\mdu_operation_o[0:0] 7/8: $0\IDEXPC_o[31:0] 8/8: $0\IDEXIR_o[31:0] Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478'. 1/2: $1\alu_input_b[31:0] 2/2: $1\alu_input_a[31:0] Creating decoders for process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477'. 1/2: $1\is_immediate_o[0:0] 2/2: $1\aluop[1:0] Creating decoders for process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. 1/56: $9$lookahead\prediction$348[1023:0]$465 2/56: $5$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339[31:0]$464 3/56: $8$lookahead\prediction$348[1023:0]$460 4/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339[31:0]$456 5/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$459 6/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_DATA[31:0]$458 7/56: $4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_ADDR[8:0]$457 8/56: $7$lookahead\prediction$348[1023:0]$444 9/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$338[31:0]$443 10/56: $6$lookahead\prediction$348[1023:0]$439 11/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$338[31:0]$431 12/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$435 13/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_DATA[31:0]$434 14/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_ADDR[8:0]$433 15/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$438 16/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_DATA[31:0]$437 17/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_ADDR[8:0]$436 18/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339[31:0]$432 19/56: $5$lookahead\prediction$348[1023:0]$419 20/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$337[31:0]$418 21/56: $4$lookahead\prediction$348[1023:0]$403 22/56: $4$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$336[31:0]$402 23/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$397 24/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_DATA[31:0]$396 25/56: $3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_ADDR[8:0]$395 26/56: $3$lookahead\prediction$348[1023:0]$398 27/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$336[31:0]$393 28/56: $3$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$337[31:0]$394 29/56: $2$lookahead\prediction$348[1023:0]$392 30/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$385 31/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_DATA[31:0]$384 32/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_ADDR[8:0]$383 33/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$337[31:0]$380 34/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$336[31:0]$379 35/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$391 36/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_DATA[31:0]$390 37/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_ADDR[8:0]$389 38/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$388 39/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_DATA[31:0]$387 40/56: $2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_ADDR[8:0]$386 41/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339[31:0]$382 42/56: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$338[31:0]$381 43/56: $1$lookahead\prediction$348[1023:0]$378 44/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$377 45/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_DATA[31:0]$376 46/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_ADDR[8:0]$375 47/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$374 48/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_DATA[31:0]$373 49/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_ADDR[8:0]$372 50/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$371 51/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_DATA[31:0]$370 52/56: $1$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_ADDR[8:0]$369 53/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339[31:0]$368 54/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$338[31:0]$367 55/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$337[31:0]$366 56/56: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$336[31:0]$365 Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. 1/11: $0\IFID_is_compressed_instruction_o[0:0] 2/11: $0\jump_is_predicted[0:0] 3/11: $0\flush_bus_o[0:0] 4/11: $0\instruction_request_o[0:0] 5/11: $0\temp_pc[31:0] 6/11: $0\temp_instruction[31:0] 7/11: $0\finish_unaligned_pc[0:0] 8/11: $0\pc_is_unaligned[0:0] 9/11: $0\PC[31:0] 10/11: $0\IFID_IR_o[31:0] 11/11: $0\IFID_PC_o[31:0] Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$292'. 1/1: $1\is_jump[0:0] Creating decoders for process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. 1/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$281 2/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_DATA[31:0]$280 3/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_ADDR[2:0]$279 4/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$278 5/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_DATA[26:0]$277 6/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_ADDR[2:0]$276 7/33: $3$lookahead\cache_valid$223[7:0]$282 8/33: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$209[31:0]$275 9/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$265 10/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_DATA[31:0]$264 11/33: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_ADDR[2:0]$263 12/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$262 13/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_DATA[26:0]$261 14/33: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_ADDR[2:0]$260 15/33: $2$lookahead\cache_valid$223[7:0]$266 16/33: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$208[31:0]$259 17/33: $1$lookahead\cache_valid$223[7:0]$255 18/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$254 19/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_DATA[31:0]$253 20/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_ADDR[2:0]$252 21/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$251 22/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_DATA[26:0]$250 23/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_ADDR[2:0]$249 24/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$248 25/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_DATA[31:0]$247 26/33: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_ADDR[2:0]$246 27/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$245 28/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_DATA[26:0]$244 29/33: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_ADDR[2:0]$243 30/33: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$209[31:0]$242 31/33: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$208[31:0]$241 32/33: $0\miss_finished[0:0] 33/33: $0\write_through[0:0] Creating decoders for process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:288$203'. Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. 1/6: $0\state_mul[1:0] 2/6: $0\mul_ready_o[0:0] 3/6: $0\acumulador[63:0] 4/6: $0\Data_Y[31:0] 5/6: $0\Data_X[31:0] 6/6: $0\MUL_RD[31:0] Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. 1/8: $0\state_div[1:0] 2/8: $0\div_ready_o[0:0] 3/8: $0\divisor[62:0] 4/8: $0\DIV_RD[31:0] 5/8: $0\quociente_msk[31:0] 6/8: $0\quociente[31:0] 7/8: $0\dividendo[31:0] 8/8: $0\negativo[0:0] Creating decoders for process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. 1/16: $0\memory_read[0:0] 2/16: $0\memory_write[0:0] 3/16: $0\memory_operation_o[0:0] 4/16: $0\Merged_Word_o[31:0] 5/16: $0\IMMEDIATE_REG_o[31:0] 6/16: $0\EXMEMPC_o[31:0] 7/16: $0\EXMEMIR_o[31:0] 8/16: $0\EXMEMALUOut_o[31:0] 9/16: $0\Data_Address[31:0] 10/16: $0\Second_Word[31:0] 11/16: $0\First_Word[31:0] 12/16: $0\unaligned_access_state[3:0] 13/16: $0\subword[0:0] 14/16: $0\unaligned_access_in_progress[0:0] 15/16: $0\EXMEM_mem_data_value[31:0] 16/16: $0\subword_store[0:0] Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. 1/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$98 2/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_DATA[31:0]$97 3/3: $1$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_ADDR[4:0]$96 Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'. 1/1: $1\csr_write_data[31:0] Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. 1/8: $0\MSCRATCH_reg[31:0] 2/8: $0\MTVEC_reg[31:0] 3/8: $0\MIE_reg[31:0] 4/8: $0\MIP_reg[31:0] 5/8: $0\MTVAL_reg[31:0] 6/8: $0\MCAUSE_reg[31:0] 7/8: $0\MSTATUS_reg[31:0] 8/8: $0\MEPC_reg[31:0] Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'. 1/2: $0\MCYCLE_reg[63:0] 2/2: $0\MINSTRET_reg[63:0] Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'. 1/1: $1\csr_read_data[31:0] Creating decoders for process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. 1/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$54 2/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA[31:0]$53 3/19: $2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR[2:0]$52 4/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$51 5/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA[26:0]$50 6/19: $2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR[2:0]$49 7/19: $2$lookahead\cache_valid$16[7:0]$55 8/19: $2$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5[31:0]$48 9/19: $1$lookahead\cache_valid$16[7:0]$34 10/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$33 11/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA[31:0]$32 12/19: $1$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR[2:0]$31 13/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$30 14/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA[26:0]$29 15/19: $1$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR[2:0]$28 16/19: $1$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5[31:0]$27 17/19: $0\miss_finished[0:0] 18/19: $0\clear_response[0:0] 19/19: $0\request_to_memory[0:0] 34.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1557'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1500'. No latch inferred for signal `\MUX.\S_o' from process `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633'. No latch inferred for signal `\Forwarding_Unit.\fwd_rs1_o' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620'. No latch inferred for signal `\Forwarding_Unit.\fwd_rs2_o' from process `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620'. No latch inferred for signal `\Immediate_Generator.\imm_o' from process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$619'. No latch inferred for signal `\Alu.\ALU_RD_o' from process `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$583'. No latch inferred for signal `\MEMWB.\read_data_normalized' from process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:72$550'. No latch inferred for signal `\ALU_Control.\ALU_OP_o' from process `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545'. No latch inferred for signal `\Invalid_IR_Check.\invalid_instruction_o' from process `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$542'. No latch inferred for signal `\IR_Decompression.\instr_d_o' from process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520'. No latch inferred for signal `\IR_Decompression.\instr_illegal_o' from process `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520'. No latch inferred for signal `\IDEX.\alu_input_a' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478'. No latch inferred for signal `\IDEX.\alu_input_b' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478'. No latch inferred for signal `\IDEX.\is_immediate_o' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477'. No latch inferred for signal `\IDEX.\aluop' from process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477'. No latch inferred for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_jump' from process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$292'. No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'. No latch inferred for signal `\CSR_Unit.\csr_read_data' from process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'. 34.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1138'. created $dff cell `$procdff$5178' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1074_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1075_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1076_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1077_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1078_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1079_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1080_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1081_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1082_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1083_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1084_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1085_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1086_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1087_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$1088_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090'. created $dff cell `$procdff$5179' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090'. created $dff cell `$procdff$5180' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$1089_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090'. created $dff cell `$procdff$5181' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1014_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1015_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1016_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1017_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1018_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1019_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1020_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1021_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1022_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1023_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1024_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1025_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1026_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1027_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1028_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$1029_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032'. created $dff cell `$procdff$5182' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032'. created $dff cell `$procdff$5183' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$1030_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032'. created $dff cell `$procdff$5184' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1031'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. created $dff cell `$procdff$5185' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. created $dff cell `$procdff$5186' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. created $dff cell `$procdff$5187' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. created $dff cell `$procdff$5188' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1385'. created $dff cell `$procdff$5189' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1385'. created $dff cell `$procdff$5190' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586'. created $dff cell `$procdff$5191' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586'. created $dff cell `$procdff$5192' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1584'. created $dff cell `$procdff$5193' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1576'. created $dff cell `$procdff$5194' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1573'. created $dff cell `$procdff$5195' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1567'. created $dff cell `$procdff$5196' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562'. created $dff cell `$procdff$5197' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562'. created $dff cell `$procdff$5198' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1548'. created $dff cell `$procdff$5199' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1535'. created $dff cell `$procdff$5200' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1533'. created $dff cell `$procdff$5201' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1525'. created $dff cell `$procdff$5202' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1511'. created $dff cell `$procdff$5203' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505'. created $dff cell `$procdff$5204' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505'. created $dff cell `$procdff$5205' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1487'. created $dff cell `$procdff$5206' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478'. created $dff cell `$procdff$5207' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478'. created $dff cell `$procdff$5208' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5209' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5210' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5211' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5212' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5213' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5214' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5215' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5216' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5217' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5218' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5219' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5220' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5221' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5222' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5223' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5224' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5225' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5226' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5227' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5228' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5229' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5230' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5231' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5232' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5233' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5234' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5235' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. created $dff cell `$procdff$5236' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. created $dff cell `$procdff$5237' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. created $dff cell `$procdff$5238' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. created $dff cell `$procdff$5239' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. created $dff cell `$procdff$5240' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1429'. created $dff cell `$procdff$5241' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1429'. created $dff cell `$procdff$5242' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5243' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5244' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5245' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5246' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5247' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. created $dff cell `$procdff$5248' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. created $dff cell `$procdff$5249' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. created $dff cell `$procdff$5250' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. created $dff cell `$procdff$5251' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. created $dff cell `$procdff$5252' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. created $dff cell `$procdff$5253' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1212'. created $dff cell `$procdff$5254' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1212'. created $dff cell `$procdff$5255' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. created $dff cell `$procdff$5256' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. created $dff cell `$procdff$5257' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. created $dff cell `$procdff$5258' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. created $dff cell `$procdff$5259' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1191'. created $dff cell `$procdff$5260' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. created $dff cell `$procdff$5261' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. created $dff cell `$procdff$5262' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. created $dff cell `$procdff$5263' with positive edge clock. Creating register for signal `\MEMWB.\instruction_finished_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5264' with positive edge clock. Creating register for signal `\MEMWB.\reg_wr_en_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5265' with positive edge clock. Creating register for signal `\MEMWB.\MEMWB_PC_o' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5266' with positive edge clock. Creating register for signal `\MEMWB.\mem_to_reg' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5267' with positive edge clock. Creating register for signal `\MEMWB.\MEMWB_mem_read_data' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5268' with positive edge clock. Creating register for signal `\MEMWB.\MEMWBALUOut' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5269' with positive edge clock. Creating register for signal `\MEMWB.\MEMWB_IR' using process `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. created $dff cell `$procdff$5270' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\read_request' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5271' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\write_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5272' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\write_request' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5273' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\requested_memory_addr' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5274' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\response_out' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5275' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\access_pedding' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5276' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\i_cache_read_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5277' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\d_cache_read_data' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5278' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\i_cache_response' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5279' with positive edge clock. Creating register for signal `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.\d_cache_response' using process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. created $dff cell `$procdff$5280' with positive edge clock. Creating register for signal `\IDEX.\take_jalr_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5281' with positive edge clock. Creating register for signal `\IDEX.\is_branch_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5282' with positive edge clock. Creating register for signal `\IDEX.\is_jalr_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5283' with positive edge clock. Creating register for signal `\IDEX.\IDEX_is_compressed_instruction_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5284' with positive edge clock. Creating register for signal `\IDEX.\BRANCH_ADDRESS_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5285' with positive edge clock. Creating register for signal `\IDEX.\NON_BRANCH_ADDRESS_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5286' with positive edge clock. Creating register for signal `\IDEX.\IDEXIR_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5287' with positive edge clock. Creating register for signal `\IDEX.\IDEXPC_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5288' with positive edge clock. Creating register for signal `\IDEX.\mdu_operation_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5289' with positive edge clock. Creating register for signal `\IDEX.\mdu_start' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5290' with positive edge clock. Creating register for signal `\IDEX.\is_immediate_reg_not' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5291' with positive edge clock. Creating register for signal `\IDEX.\alu_op_o' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5292' with positive edge clock. Creating register for signal `\IDEX.\previous_instruction_is_lw' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5293' with positive edge clock. Creating register for signal `\IDEX.\IDEXA' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5294' with positive edge clock. Creating register for signal `\IDEX.\IDEXB' using process `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. created $dff cell `$procdff$5295' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.\prediction' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5296' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$336' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5297' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$337' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5298' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:71$338' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5299' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$339' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5300' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5301' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5302' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5303' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5304' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5305' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5306' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_ADDR' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5307' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_DATA' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5308' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5309' with positive edge clock. Creating register for signal `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$lookahead\prediction$348' using process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. created $dff cell `$procdff$5310' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\take_jal_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5311' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_jal_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5312' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_is_compressed_instruction_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5313' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_PC_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5314' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\IFID_IR_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5315' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\flush_bus_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5316' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\instruction_request_o' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5317' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5318' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\jump_is_predicted' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5319' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_different_branch_address' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5320' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\pc_is_unaligned' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5321' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\finish_unaligned_pc' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5322' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\is_different_no_branch_address' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5323' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\temp_instruction' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5324' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\temp_pc' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5325' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\JAL_PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5326' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.\JALR_PC' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. created $dff cell `$procdff$5327' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\miss_finished' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5328' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\cache_valid' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5329' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.\write_through' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5330' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:53$208' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5331' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:59$209' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5332' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5333' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5334' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5335' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5336' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5337' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5338' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5339' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5340' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5341' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_ADDR' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5342' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_DATA' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5343' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5344' with positive edge clock. Creating register for signal `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$lookahead\cache_valid$223' using process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. created $dff cell `$procdff$5345' with positive edge clock. Creating register for signal `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.\software_interruption' using process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:288$203'. created $dff cell `$procdff$5346' with positive edge clock. Creating register for signal `\MDU.\mul_ready_o' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5347' with positive edge clock. Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5348' with positive edge clock. Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5349' with positive edge clock. Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5350' with positive edge clock. Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5351' with positive edge clock. Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. created $dff cell `$procdff$5352' with positive edge clock. Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5353' with positive edge clock. Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5354' with positive edge clock. Creating register for signal `\MDU.\div_ready_o' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5355' with positive edge clock. Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5356' with positive edge clock. Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5357' with positive edge clock. Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5358' with positive edge clock. Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5359' with positive edge clock. Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. created $dff cell `$procdff$5360' with positive edge clock. Creating register for signal `\EXMEM.\subword_store' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5361' with positive edge clock. Creating register for signal `\EXMEM.\memory_read' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5362' with positive edge clock. Creating register for signal `\EXMEM.\memory_write' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5363' with positive edge clock. Creating register for signal `\EXMEM.\EXMEM_mem_data_value' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5364' with positive edge clock. Creating register for signal `\EXMEM.\unaligned_access_in_progress' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5365' with positive edge clock. Creating register for signal `\EXMEM.\subword' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5366' with positive edge clock. Creating register for signal `\EXMEM.\unaligned_access_state' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5367' with positive edge clock. Creating register for signal `\EXMEM.\First_Word' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5368' with positive edge clock. Creating register for signal `\EXMEM.\Second_Word' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5369' with positive edge clock. Creating register for signal `\EXMEM.\Data_Address' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5370' with positive edge clock. Creating register for signal `\EXMEM.\EXMEMALUOut_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5371' with positive edge clock. Creating register for signal `\EXMEM.\EXMEMIR_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5372' with positive edge clock. Creating register for signal `\EXMEM.\EXMEMPC_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5373' with positive edge clock. Creating register for signal `\EXMEM.\IMMEDIATE_REG_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5374' with positive edge clock. Creating register for signal `\EXMEM.\Merged_Word_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5375' with positive edge clock. Creating register for signal `\EXMEM.\memory_operation_o' using process `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. created $dff cell `$procdff$5376' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_ADDR' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. created $dff cell `$procdff$5377' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_DATA' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. created $dff cell `$procdff$5378' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. created $dff cell `$procdff$5379' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:28$78_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. created $dff cell `$procdff$5380' with positive edge clock. Creating register for signal `\CSR_Unit.\MEPC_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5381' with positive edge clock. Creating register for signal `\CSR_Unit.\MSTATUS_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5382' with positive edge clock. Creating register for signal `\CSR_Unit.\MCAUSE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5383' with positive edge clock. Creating register for signal `\CSR_Unit.\MTVAL_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5384' with positive edge clock. Creating register for signal `\CSR_Unit.\MIP_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5385' with positive edge clock. Creating register for signal `\CSR_Unit.\MIE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5386' with positive edge clock. Creating register for signal `\CSR_Unit.\MTVEC_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5387' with positive edge clock. Creating register for signal `\CSR_Unit.\MSCRATCH_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. created $dff cell `$procdff$5388' with positive edge clock. Creating register for signal `\CSR_Unit.\MCYCLE_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'. created $dff cell `$procdff$5389' with positive edge clock. Creating register for signal `\CSR_Unit.\MINSTRET_reg' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'. created $dff cell `$procdff$5390' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\request_to_memory' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5391' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\clear_response' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5392' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\miss_finished' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5393' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.\cache_valid' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5394' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$bitselwrite$pos$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:63$5' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5395' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_ADDR' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5396' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_DATA' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5397' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5398' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_ADDR' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5399' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_DATA' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5400' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5401' with positive edge clock. Creating register for signal `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$lookahead\cache_valid$16' using process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. created $dff cell `$procdff$5402' with positive edge clock. 34.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 34.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1139'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1138'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$1138'. Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1113'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$1090'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$1056'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$1032'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$1031'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1418'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1393'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1385'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1385'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1588'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1586'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1584'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1584'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1576'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1576'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1573'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1573'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1567'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1567'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1562'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1557'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1557'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1548'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1548'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1541'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1535'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1535'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1533'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1533'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1525'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1525'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1511'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1511'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1505'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1500'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1500'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1493'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1487'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1487'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1478'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1471'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1442'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1441'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1434'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1429'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1429'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1424'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1419'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1212'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1202'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1191'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1191'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1148'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1141'. Found and cleaned up 1 empty switch in `\MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633'. Removing empty process `MUX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mux.sv:10$633'. Found and cleaned up 6 empty switches in `\Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620'. Removing empty process `Forwarding_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/forwarding_unit.sv:13$620'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$619'. Removing empty process `Immediate_Generator.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/immediate_generator.sv:20$619'. Found and cleaned up 1 empty switch in `\Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$583'. Removing empty process `Alu.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:28$583'. Found and cleaned up 3 empty switches in `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. Removing empty process `MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:36$554'. Found and cleaned up 1 empty switch in `\MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:72$550'. Removing empty process `MEMWB.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:72$550'. Found and cleaned up 3 empty switches in `\ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545'. Removing empty process `ALU_Control.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:25$545'. Found and cleaned up 5 empty switches in `\Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$542'. Removing empty process `Invalid_IR_Check.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/invalid_ir_check.sv:15$542'. Found and cleaned up 6 empty switches in `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. Removing empty process `$paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/cache_request_multiplexer.sv:41$533'. Found and cleaned up 17 empty switches in `\IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520'. Removing empty process `IR_Decompression.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:25$520'. Found and cleaned up 3 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:75$488'. Found and cleaned up 2 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478'. Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:136$478'. Found and cleaned up 2 empty switches in `\IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477'. Removing empty process `IDEX.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:119$477'. Found and cleaned up 9 empty switches in `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. Removing empty process `$paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:53$349'. Found and cleaned up 18 empty switches in `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:84$299'. Found and cleaned up 1 empty switch in `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$292'. Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:214$292'. Found and cleaned up 4 empty switches in `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. Removing empty process `$paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:44$224'. Removing empty process `$paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/core.sv:288$203'. Found and cleaned up 4 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:66$194'. Found and cleaned up 6 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:212$158'. Found and cleaned up 32 empty switches in `\EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. Removing empty process `EXMEM.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:85$104'. Found and cleaned up 1 empty switch in `\Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:23$91'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'. Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:87$73'. Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:149$69'. Found and cleaned up 2 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'. Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:136$65'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'. Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:99$64'. Found and cleaned up 5 empty switches in `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. Removing empty process `$paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:39$17'. Cleaned up 232 empty switches. 34.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Forwarding_Unit. Optimizing module Immediate_Generator. Optimizing module Grande_Risco5. <suppressed ~2 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module MEMWB. <suppressed ~2 debug messages> Optimizing module ALU_Control. <suppressed ~1 debug messages> Optimizing module Invalid_IR_Check. <suppressed ~5 debug messages> Optimizing module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer. <suppressed ~16 debug messages> Optimizing module IR_Decompression. <suppressed ~35 debug messages> Optimizing module IDEX. Optimizing module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000. <suppressed ~57 debug messages> Optimizing module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID. <suppressed ~15 debug messages> Optimizing module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000. <suppressed ~33 debug messages> Optimizing module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core. Optimizing module MDU. <suppressed ~29 debug messages> Optimizing module EXMEM. <suppressed ~16 debug messages> Optimizing module Registers. Optimizing module CSR_Unit. <suppressed ~11 debug messages> Optimizing module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000. <suppressed ~19 debug messages> Optimizing module processorci_top. 34.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module MUX. Deleting now unused module Forwarding_Unit. Deleting now unused module Immediate_Generator. Deleting now unused module Grande_Risco5. Deleting now unused module Alu. Deleting now unused module MEMWB. Deleting now unused module ALU_Control. Deleting now unused module Invalid_IR_Check. Deleting now unused module $paramod$32ff7bf57b195fc60e573423b8bfbc6dfa6c0fc6\Cache_request_Multiplexer. Deleting now unused module IR_Decompression. Deleting now unused module IDEX. Deleting now unused module $paramod\Branch_Prediction\BRANCH_PREDICTION_SIZE=32'00000000000000000000001000000000. Deleting now unused module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\IFID. Deleting now unused module $paramod\DCache\CACHE_SIZE=32'00000000000000000000000000100000. Deleting now unused module $paramod$4d177e2be02c34978d79f6caeec53a01d504d17f\Core. Deleting now unused module MDU. Deleting now unused module EXMEM. Deleting now unused module Registers. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ICache\CACHE_SIZE=32'00000000000000000000000000100000. <suppressed ~32 debug messages> 34.6. Executing TRIBUF pass. 34.7. Executing DEMINOUT pass (demote inout ports to input or output). 34.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~263 debug messages> 34.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 253 unused cells and 1735 unused wires. <suppressed ~286 debug messages> 34.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver. Warning: Wire processorci_top.\Controller.core_write_memory_data is used but has no driver. Warning: Wire processorci_top.\Controller.core_read_memory_data is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [31] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [30] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [29] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [28] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [27] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [26] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [25] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [24] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [23] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [22] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [21] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [20] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [19] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [18] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [17] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [16] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [15] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [14] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [13] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [12] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [11] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [10] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [9] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [8] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [7] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [6] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [5] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [4] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [3] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [2] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [1] is used but has no driver. Warning: Wire processorci_top.\Controller.core_address_memory_data [0] is used but has no driver. Found and reported 69 problems. 34.11. Executing OPT pass (performing simple optimizations). 34.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~1317 debug messages> Removed a total of 439 cells. 34.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\Processor.\N1.\First_Stage.$procmux$4130: \Processor.N1.First_Stage.finish_unaligned_pc -> 1'0 Analyzing evaluation results. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1616. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1622. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1628. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1616. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1622. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1628. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4292. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4298. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4304. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4310. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4316. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4322. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4328. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4340. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4346. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4352. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4358. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4364. dead port 1/2 on $mux $flatten\Processor.\DCache.$procmux$4370. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5087. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5093. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5099. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5105. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5111. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5117. dead port 1/2 on $mux $flatten\Processor.\ICache.$procmux$5123. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3579. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3582. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3585. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3588. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3609. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3612. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3615. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3633. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3636. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3639. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3645. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3648. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3651. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3657. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3660. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3663. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3669. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3672. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3675. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3693. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3696. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3711. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3714. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3720. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3723. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3729. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3732. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3738. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3741. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3747. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3750. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3756. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3759. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3775. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3777. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3780. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3799. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3801. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3804. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3822. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3825. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3831. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3834. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3840. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3843. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3849. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3852. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3876. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3882. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3888. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3894. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3912. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3918. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3924. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3930. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3936. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3942. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3228. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3231. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3233. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3235. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3244. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3246. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3248. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3258. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3260. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3262. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3264. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3273. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3275. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3277. dead port 1/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3286. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3288. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3290. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3298. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3300. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3308. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3310. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3319. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3321. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3331. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3333. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3342. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3351. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3362. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3364. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3366. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3377. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3379. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3381. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3391. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3393. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3395. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3404. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3406. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3415. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3417. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3426. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3428. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3437. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3439. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3450. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3461. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3472. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3474. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3484. dead port 2/2 on $mux $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3494. dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3036. dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3047. dead port 1/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2931. dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2937. dead port 1/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2946. dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2952. dead port 2/2 on $mux $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2966. dead port 1/2 on $mux $flatten\Processor.\N1.\Third_Stage.$procmux$4929. Removed 141 multiplexer ports. <suppressed ~250 debug messages> 34.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4289: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4289_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4289_Y [0] New connections: $flatten\Processor.\DCache.$procmux$4289_Y [31:1] = { $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] $flatten\Processor.\DCache.$procmux$4289_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4307: Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4307_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4307_Y [0] New connections: $flatten\Processor.\DCache.$procmux$4307_Y [26:1] = { $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] $flatten\Processor.\DCache.$procmux$4307_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4337: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4337_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4337_Y [0] New connections: $flatten\Processor.\DCache.$procmux$4337_Y [31:1] = { $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] $flatten\Processor.\DCache.$procmux$4337_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4355: Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\DCache.$procmux$4355_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\DCache.$procmux$4355_Y [0] New connections: $flatten\Processor.\DCache.$procmux$4355_Y [26:1] = { $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] $flatten\Processor.\DCache.$procmux$4355_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5084: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\ICache.$procmux$5084_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\ICache.$procmux$5084_Y [0] New connections: $flatten\Processor.\ICache.$procmux$5084_Y [31:1] = { $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] $flatten\Processor.\ICache.$procmux$5084_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5102: Old ports: A=27'000000000000000000000000000, B=27'111111111111111111111111111, Y=$flatten\Processor.\ICache.$procmux$5102_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\ICache.$procmux$5102_Y [0] New connections: $flatten\Processor.\ICache.$procmux$5102_Y [26:1] = { $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] $flatten\Processor.\ICache.$procmux$5102_Y [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0] } New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5004: $auto$opt_reduce.cc:137:opt_pmux$5449 New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5065: { $auto$opt_reduce.cc:137:opt_pmux$5457 $auto$opt_reduce.cc:137:opt_pmux$5455 $auto$opt_reduce.cc:137:opt_pmux$5453 $auto$opt_reduce.cc:137:opt_pmux$5451 $flatten\Processor.\N1.\CSR.$procmux$5074_CMP $flatten\Processor.\N1.\CSR.$procmux$5040_CMP $flatten\Processor.\N1.\CSR.$procmux$5006_CMP $flatten\Processor.\N1.\CSR.$procmux$4998_CMP $flatten\Processor.\N1.\CSR.$procmux$4986_CMP $flatten\Processor.\N1.\CSR.$procmux$5050_CMP $flatten\Processor.\N1.\CSR.$procmux$5026_CMP $flatten\Processor.\N1.\CSR.$procmux$5017_CMP $flatten\Processor.\N1.\CSR.$procmux$5005_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2052: $auto$opt_reduce.cc:137:opt_pmux$5459 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2076: $auto$opt_reduce.cc:137:opt_pmux$5461 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2098: $auto$opt_reduce.cc:137:opt_pmux$5463 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2109: $auto$opt_reduce.cc:137:opt_pmux$5465 Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2157: $auto$opt_reduce.cc:137:opt_pmux$5467 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2199: $auto$opt_reduce.cc:137:opt_pmux$5469 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2224: { $flatten\Controller.\Interpreter.$procmux$1992_CMP $auto$opt_reduce.cc:137:opt_pmux$5471 $flatten\Controller.\Interpreter.$procmux$1982_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2277: { $auto$opt_reduce.cc:137:opt_pmux$5475 $auto$opt_reduce.cc:137:opt_pmux$5473 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3371: { $auto$opt_reduce.cc:137:opt_pmux$5477 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3357_CTRL } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2346: $auto$opt_reduce.cc:137:opt_pmux$5479 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2371: { $flatten\Controller.\Interpreter.$procmux$1992_CMP $auto$opt_reduce.cc:137:opt_pmux$5481 $flatten\Controller.\Interpreter.$procmux$1982_CMP } Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2862: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2399: { $flatten\Controller.\Interpreter.$procmux$1978_CMP $flatten\Controller.\Interpreter.$procmux$1971_CMP $flatten\Controller.\Interpreter.$procmux$1960_CMP $flatten\Controller.\Interpreter.$procmux$1954_CMP $auto$opt_reduce.cc:137:opt_pmux$5483 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3454: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337_CMP [1] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3234_CMP $auto$opt_reduce.cc:137:opt_pmux$5485 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2431: { $auto$opt_reduce.cc:137:opt_pmux$5489 $auto$opt_reduce.cc:137:opt_pmux$5487 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3479: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3332_CMP $auto$opt_reduce.cc:137:opt_pmux$5491 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3480_CTRL } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2513: { $flatten\Controller.\Interpreter.$procmux$1972_CMP $auto$opt_reduce.cc:137:opt_pmux$5493 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2524: { $flatten\Controller.\Interpreter.$procmux$2113_CMP $flatten\Controller.\Interpreter.$procmux$2012_CMP $auto$opt_reduce.cc:137:opt_pmux$5495 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2534: { $flatten\Controller.\Interpreter.$procmux$2011_CMP $auto$opt_reduce.cc:137:opt_pmux$5499 $auto$opt_reduce.cc:137:opt_pmux$5497 } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\RegisterBank.$procmux$4968: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 New ports: A=1'0, B=1'1, Y=$flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] New connections: $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [31:1] = { $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] $flatten\Processor.\N1.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:25$77_EN[31:0]$94 [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2588: { $auto$opt_reduce.cc:137:opt_pmux$5501 $flatten\Controller.\Interpreter.$procmux$2078_CMP $flatten\Controller.\Interpreter.$procmux$1997_CMP $flatten\Controller.\Interpreter.$procmux$1992_CMP $flatten\Controller.\Interpreter.$procmux$1982_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1952: { $flatten\Controller.\Interpreter.$procmux$2046_CMP $flatten\Controller.\Interpreter.$procmux$2042_CMP $flatten\Controller.\Interpreter.$procmux$2038_CMP $flatten\Controller.\Interpreter.$procmux$2012_CMP $flatten\Controller.\Interpreter.$procmux$2011_CMP $flatten\Controller.\Interpreter.$procmux$2007_CMP $flatten\Controller.\Interpreter.$procmux$2006_CMP $flatten\Controller.\Interpreter.$procmux$2002_CMP $flatten\Controller.\Interpreter.$procmux$1992_CMP $flatten\Controller.\Interpreter.$procmux$1988_CMP $auto$opt_reduce.cc:137:opt_pmux$5509 $flatten\Controller.\Interpreter.$procmux$1983_CMP $flatten\Controller.\Interpreter.$procmux$1982_CMP $auto$opt_reduce.cc:137:opt_pmux$5507 $flatten\Controller.\Interpreter.$procmux$1977_CMP $flatten\Controller.\Interpreter.$procmux$1976_CMP $flatten\Controller.\Interpreter.$procmux$1971_CMP $flatten\Controller.\Interpreter.$procmux$1967_CMP $flatten\Controller.\Interpreter.$procmux$1966_CMP $auto$opt_reduce.cc:137:opt_pmux$5505 $flatten\Controller.\Interpreter.$procmux$1960_CMP $flatten\Controller.\Interpreter.$procmux$1959_CMP $flatten\Controller.\Interpreter.$procmux$1958_CMP $auto$opt_reduce.cc:137:opt_pmux$5503 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2642: { $auto$opt_reduce.cc:137:opt_pmux$5511 $flatten\Controller.\Interpreter.$procmux$2011_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2666: { $flatten\Controller.\Interpreter.$procmux$2079_CMP $flatten\Controller.\Interpreter.$procmux$2078_CMP $auto$opt_reduce.cc:137:opt_pmux$5513 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2969: { $flatten\Processor.\N1.\Second_Stage.$0\is_branch_o[0:0] $flatten\Processor.\N1.\First_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:89$300_Y $auto$opt_reduce.cc:137:opt_pmux$5517 $flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP [0] $auto$opt_reduce.cc:137:opt_pmux$5515 $flatten\Processor.\N1.\Second_Stage.$procmux$3573_CMP [1] $flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP [2] } Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2862: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_EN[31:0]$1205 [0] } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4607: { $auto$opt_reduce.cc:137:opt_pmux$5519 $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4635: $auto$opt_reduce.cc:137:opt_pmux$5521 New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4807: { $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP $auto$opt_reduce.cc:137:opt_pmux$5523 } New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2730: $auto$opt_reduce.cc:137:opt_pmux$5525 New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4825: { $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4836_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4830_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP $auto$opt_reduce.cc:137:opt_pmux$5527 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4914: { $flatten\Processor.\N1.\Third_Stage.$procmux$4920_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4919_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4918_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4917_CMP $auto$opt_reduce.cc:137:opt_pmux$5529 } New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2794: $auto$opt_reduce.cc:137:opt_pmux$5531 New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$5484: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3338_CMP $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337_CMP [3:2] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337_CMP [0] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3332_CMP $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3320_CMP } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4388: Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$281, B=0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 New ports: A=$flatten\Processor.\DCache.$procmux$4289_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] New connections: $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [31:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:61$213_EN[31:0]$238 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4397: Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$278, B=27'000000000000000000000000000, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 New ports: A=$flatten\Processor.\DCache.$procmux$4307_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] New connections: $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [26:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:60$212_EN[26:0]$235 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4406: Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$265, B=0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 New ports: A=$flatten\Processor.\DCache.$procmux$4337_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] New connections: $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [31:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] $flatten\Processor.\DCache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:55$211_EN[31:0]$232 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\DCache.$procmux$4415: Old ports: A=$flatten\Processor.\DCache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$262, B=27'000000000000000000000000000, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 New ports: A=$flatten\Processor.\DCache.$procmux$4355_Y [0], B=1'0, Y=$flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] New connections: $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [26:1] = { $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] $flatten\Processor.\DCache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:54$210_EN[26:0]$229 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5135: Old ports: A=$flatten\Processor.\ICache.$2$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$54, B=0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 New ports: A=$flatten\Processor.\ICache.$procmux$5084_Y [0], B=1'0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] New connections: $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [31:1] = { $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] $flatten\Processor.\ICache.$0$memwr$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:65$7_EN[31:0]$24 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\ICache.$procmux$5144: Old ports: A=$flatten\Processor.\ICache.$2$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$51, B=27'000000000000000000000000000, Y=$flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 New ports: A=$flatten\Processor.\ICache.$procmux$5102_Y [0], B=1'0, Y=$flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] New connections: $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [26:1] = { $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] $flatten\Processor.\ICache.$0$memwr$\cache_tag$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:64$6_EN[26:0]$21 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1631: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1405, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1613_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$4$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$459, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3630_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1631: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1405, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1613_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_EN[7:0]$1396 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879: Old ports: A=0, B=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$397, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y New ports: A=1'0, B=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3820_Y [0], Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$435, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3708_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0] } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$3$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$438, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3735_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3969: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$388, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3927_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:68$341_EN[31:0]$359 [0] } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3978: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$385, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3879_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:62$340_EN[31:0]$356 [0] } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3960: Old ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$391, B=0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 New ports: A=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procmux$3909_Y [0], B=1'0, Y=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] New connections: $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [31:1] = { $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$0$memwr$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:73$342_EN[31:0]$362 [0] } Optimizing cells in module \processorci_top. Performed a total of 62 changes. 34.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~120 debug messages> Removed a total of 40 cells. 34.11.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\Processor.\N1.\First_Stage.$procdff$5317 ($dff) from module processorci_top. 34.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 615 unused wires. <suppressed ~23 debug messages> 34.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~2 debug messages> 34.11.9. Rerunning OPT passes. (Maybe there is more to do..) 34.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~252 debug messages> 34.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2224: { $auto$opt_reduce.cc:137:opt_pmux$5471 $auto$opt_reduce.cc:137:opt_pmux$5533 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2371: { $auto$opt_reduce.cc:137:opt_pmux$5471 $auto$opt_reduce.cc:137:opt_pmux$5535 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2588: { $auto$opt_reduce.cc:137:opt_pmux$5501 $flatten\Controller.\Interpreter.$procmux$2078_CMP $flatten\Controller.\Interpreter.$procmux$1997_CMP $auto$opt_reduce.cc:137:opt_pmux$5537 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2980: { $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2994_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2993_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2992_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2991_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2990_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2989_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2988_CMP $auto$opt_reduce.cc:137:opt_pmux$5541 $auto$opt_reduce.cc:137:opt_pmux$5539 $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2983_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2982_CMP $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2981_CMP } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4607: { $auto$opt_reduce.cc:137:opt_pmux$5519 $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP $auto$opt_reduce.cc:137:opt_pmux$5543 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4775: $auto$opt_reduce.cc:137:opt_pmux$5545 New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4795: $auto$opt_reduce.cc:137:opt_pmux$5547 New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4807: { $auto$opt_reduce.cc:137:opt_pmux$5549 $auto$opt_reduce.cc:137:opt_pmux$5523 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4825: { $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP $auto$opt_reduce.cc:137:opt_pmux$5551 $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP $auto$opt_reduce.cc:137:opt_pmux$5527 } New ctrl vector for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4893: { $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP $auto$opt_reduce.cc:137:opt_pmux$5553 } Optimizing cells in module \processorci_top. Performed a total of 10 changes. 34.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 34.11.13. Executing OPT_DFF pass (perform DFF optimizations). 34.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 5 unused wires. <suppressed ~1 debug messages> 34.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.11.16. Rerunning OPT passes. (Maybe there is more to do..) 34.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~252 debug messages> 34.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.11.20. Executing OPT_DFF pass (perform DFF optimizations). 34.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.11.23. Finished OPT passes. (There is nothing left to do.) 34.12. Executing FSM pass (extract and optimize FSM). 34.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.Processor.N1.CSR.MIP_reg as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Processor.N1.Second_Stage.Mdu.state_div. Found FSM state register processorci_top.Processor.N1.Second_Stage.Mdu.state_mul. Not marking processorci_top.Processor.N1.Second_Stage.alu_op_o as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Processor.N1.Third_Stage.unaligned_access_state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. 34.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$5193 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1552_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1565_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1578_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1564_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1578_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1569_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1565_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1564_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1552_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1552_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1564_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1565_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1569_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1578_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$5240 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2691_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2686_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2693_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2680_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1438_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2680_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2686_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2691_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2693_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1438_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2693_CMP $flatten\Controller.\Uart.$procmux$2691_CMP $flatten\Controller.\Uart.$procmux$2686_CMP $flatten\Controller.\Uart.$procmux$2680_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 Extracting FSM `\Processor.N1.Second_Stage.Mdu.state_div' from module `\processorci_top'. found $dff cell for state register: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5353 root of input selection tree: $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4508_CMP found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4512_CMP found state code: 2'00 found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$179_Y found state code: 2'01 found state code: 2'10 found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$160_Y found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4508_CMP found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4512_CMP found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4518_CMP ctrl inputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$179_Y $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$160_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4518_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4512_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4508_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] } transition: 2'00 3'-00 -> 2'00 5'01000 transition: 2'00 3'-10 -> 2'01 5'01001 transition: 2'00 3'--1 -> 2'00 5'01000 transition: 2'10 3'--0 -> 2'00 5'10000 transition: 2'10 3'--1 -> 2'00 5'10000 transition: 2'01 3'0-0 -> 2'01 5'00101 transition: 2'01 3'1-0 -> 2'10 5'00110 transition: 2'01 3'--1 -> 2'00 5'00100 Extracting FSM `\Processor.N1.Second_Stage.Mdu.state_mul' from module `\processorci_top'. found $dff cell for state register: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5349 root of input selection tree: $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4448_CMP found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4452_CMP found state code: 2'00 found state code: 2'10 found ctrl input: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$197_Y found state code: 2'01 found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4448_CMP found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4452_CMP found ctrl output: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4458_CMP ctrl inputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$197_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4458_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4452_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4448_CMP $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] } transition: 2'00 2'00 -> 2'00 5'01000 transition: 2'00 2'10 -> 2'01 5'01001 transition: 2'00 2'-1 -> 2'00 5'01000 transition: 2'10 2'-0 -> 2'00 5'10000 transition: 2'10 2'-1 -> 2'00 5'10000 transition: 2'01 2'-0 -> 2'10 5'00110 transition: 2'01 2'-1 -> 2'00 5'00100 Extracting FSM `\Processor.N1.Third_Stage.unaligned_access_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Processor.\N1.\Third_Stage.$procdff$5367 root of input selection tree: $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found ctrl input: $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:96$107_Y found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5527 found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5551 found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP found ctrl input: $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP found state code: 4'1001 found ctrl input: $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:240$123_Y found state code: 4'1101 found state code: 4'0110 found ctrl input: \Processor.N1.Third_Stage.data_memory_response found state code: 4'0000 found state code: 4'1100 found ctrl input: \Processor.N1.Third_Stage.subword found state code: 4'1000 found state code: 4'1111 found state code: 4'0111 found state code: 4'0101 found state code: 4'1110 found state code: 4'1010 found state code: 4'0011 found state code: 4'0010 found ctrl input: \Processor.N1.Third_Stage.subword_store found ctrl input: $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:58$570_Y found ctrl input: $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:104$109_Y found state code: 4'0100 found state code: 4'0001 found state code: 4'1011 found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4836_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4830_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4641_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4639_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4636_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP found ctrl output: $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP ctrl inputs: { $auto$opt_reduce.cc:137:opt_pmux$5551 $auto$opt_reduce.cc:137:opt_pmux$5527 $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:58$570_Y \Processor.N1.Third_Stage.subword_store \Processor.N1.Third_Stage.subword \Processor.N1.Third_Stage.data_memory_response $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:96$107_Y $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:104$109_Y $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:240$123_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4636_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4639_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4641_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4830_CMP $flatten\Processor.\N1.\Third_Stage.$procmux$4836_CMP } transition: 4'0000 10'------0--0 -> 4'0000 20'00000000001000000000 transition: 4'0000 10'--00--10-0 -> 4'0000 20'00000000001000000000 transition: 4'0000 10'--00--11-0 -> 4'0100 20'01000000001000000000 transition: 4'0000 10'--10--1--0 -> 4'0001 20'00010000001000000000 transition: 4'0000 10'---1--1--0 -> 4'1011 20'10110000001000000000 transition: 4'0000 10'---------1 -> 4'0000 20'00000000001000000000 transition: 4'1000 10'------0--0 -> 4'1000 20'10000000000000100000 transition: 4'1000 10'0-----1--0 -> 4'1001 20'10010000000000100000 transition: 4'1000 10'---------1 -> 4'0000 20'00000000000000100000 transition: 4'0100 10'------0--0 -> 4'0100 20'01000001000000000000 transition: 4'0100 10'-----01--0 -> 4'0100 20'01000001000000000000 transition: 4'0100 10'----011--0 -> 4'0101 20'01010001000000000000 transition: 4'0100 10'----111--0 -> 4'1110 20'11100001000000000000 transition: 4'0100 10'---------1 -> 4'0000 20'00000001000000000000 transition: 4'1100 10'------0--0 -> 4'1100 20'11000000000001000000 transition: 4'1100 10'------1--0 -> 4'1100 20'11000000000001000000 transition: 4'1100 10'---------1 -> 4'0000 20'00000000000001000000 transition: 4'0010 10'------0--0 -> 4'0010 20'00100000100000000000 transition: 4'0010 10'-----01--0 -> 4'0010 20'00100000100000000000 transition: 4'0010 10'-----11--0 -> 4'0011 20'00110000100000000000 transition: 4'0010 10'---------1 -> 4'0000 20'00000000100000000000 transition: 4'1010 10'------0--0 -> 4'1010 20'10100000000000001000 transition: 4'1010 10'------1--0 -> 4'0000 20'00000000000000001000 transition: 4'1010 10'---------1 -> 4'0000 20'00000000000000001000 transition: 4'0110 10'------0--0 -> 4'0110 20'01100010000000000000 transition: 4'0110 10'-----01--0 -> 4'0110 20'01100010000000000000 transition: 4'0110 10'-----11--0 -> 4'0111 20'01110010000000000000 transition: 4'0110 10'---------1 -> 4'0000 20'00000010000000000000 transition: 4'1110 10'------0--0 -> 4'1110 20'11100000000010000000 transition: 4'1110 10'------1-00 -> 4'1101 20'11010000000010000000 transition: 4'1110 10'------1-10 -> 4'0110 20'01100000000010000000 transition: 4'1110 10'---------1 -> 4'0000 20'00000000000010000000 transition: 4'0001 10'------0--0 -> 4'0001 20'00010000010000000000 transition: 4'0001 10'-----01--0 -> 4'0001 20'00010000010000000000 transition: 4'0001 10'-----11--0 -> 4'0010 20'00100000010000000000 transition: 4'0001 10'---------1 -> 4'0000 20'00000000010000000000 transition: 4'1001 10'------0--0 -> 4'1001 20'10010000000000000001 transition: 4'1001 10'-----01--0 -> 4'1001 20'10010000000000000001 transition: 4'1001 10'-----11--0 -> 4'0000 20'00000000000000000001 transition: 4'1001 10'---------1 -> 4'0000 20'00000000000000000001 transition: 4'0101 10'------0--0 -> 4'0101 20'01010000000000010000 transition: 4'0101 10'------1--0 -> 4'0110 20'01100000000000010000 transition: 4'0101 10'---------1 -> 4'0000 20'00000000000000010000 transition: 4'1101 10'------0--0 -> 4'1101 20'11010000000000000010 transition: 4'1101 10'-----01--0 -> 4'1101 20'11010000000000000010 transition: 4'1101 10'-----11--0 -> 4'0000 20'00000000000000000010 transition: 4'1101 10'---------1 -> 4'0000 20'00000000000000000010 transition: 4'0011 10'------0--0 -> 4'0011 20'00110000000000000100 transition: 4'0011 10'------1--0 -> 4'1010 20'10100000000000000100 transition: 4'0011 10'---------1 -> 4'0000 20'00000000000000000100 transition: 4'1011 10'------0--0 -> 4'1011 20'10111000000000000000 transition: 4'1011 10'-----01--0 -> 4'1011 20'10111000000000000000 transition: 4'1011 10'-----11--0 -> 4'1100 20'11001000000000000000 transition: 4'1011 10'---------1 -> 4'0000 20'00001000000000000000 transition: 4'0111 10'------0--0 -> 4'0111 20'01110100000000000000 transition: 4'0111 10'-----01--0 -> 4'0111 20'01110100000000000000 transition: 4'0111 10'----011--0 -> 4'1000 20'10000100000000000000 transition: 4'0111 10'----111--0 -> 4'1111 20'11110100000000000000 transition: 4'0111 10'---------1 -> 4'0000 20'00000100000000000000 transition: 4'1111 10'------0--0 -> 4'1111 20'11110000000100000000 transition: 4'1111 10'0-----1--0 -> 4'1001 20'10010000000100000000 transition: 4'1111 10'---------1 -> 4'0000 20'00000000000100000000 34.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577' from module `\processorci_top'. Merging pattern 10'------0--0 and 10'------1--0 from group (3 3 20'11000000000001000000). Merging pattern 10'------1--0 and 10'------0--0 from group (3 3 20'11000000000001000000). Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5527. Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572' from module `\processorci_top'. Merging pattern 2'-0 and 2'-1 from group (1 0 5'10000). Merging pattern 2'-1 and 2'-0 from group (1 0 5'10000). Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567' from module `\processorci_top'. Merging pattern 3'--0 and 3'--1 from group (1 0 5'10000). Merging pattern 3'--1 and 3'--0 from group (1 0 5'10000). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5561' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5554' from module `\processorci_top'. 34.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 64 unused cells and 64 unused wires. <suppressed ~65 debug messages> 34.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5554' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5561' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2691_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2693_CMP. Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567' from module `\processorci_top'. Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] [0]. Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_div[1:0] [1]. Optimizing FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572' from module `\processorci_top'. Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] [0]. Removing unused output signal $flatten\Processor.\N1.\Second_Stage.\Mdu.$0\state_mul[1:0] [1]. Optimizing FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577' from module `\processorci_top'. Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [0]. Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [1]. Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [2]. Removing unused output signal $flatten\Processor.\N1.\Third_Stage.$0\unaligned_access_state[3:0] [3]. 34.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5554' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5561' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ---------------1 1000 -> --------------1- 0100 -> -------------1-- 1100 -> ------------1--- 0010 -> -----------1---- 1010 -> ----------1----- 0110 -> ---------1------ 1110 -> --------1------- 0001 -> -------1-------- 1001 -> ------1--------- 0101 -> -----1---------- 1101 -> ----1----------- 0011 -> ---1------------ 1011 -> --1------------- 0111 -> -1-------------- 1111 -> 1--------------- 34.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5554' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$5554 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1578_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1569_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1565_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1564_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1552_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5561' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$5561 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1438_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2680_CMP 1: $flatten\Controller.\Uart.$procmux$2686_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567 (\Processor.N1.Second_Stage.Mdu.state_div): Number of input signals: 3 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:220$160_Y 2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$179_Y Output signals: 0: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4508_CMP 1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4512_CMP 2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4518_CMP State encoding: 0: 3'--1 <RESET STATE> 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'-00 -> 0 3'010 1: 0 3'--1 -> 0 3'010 2: 0 3'-10 -> 2 3'010 3: 1 3'--- -> 0 3'100 4: 2 3'--1 -> 0 3'001 5: 2 3'1-0 -> 1 3'001 6: 2 3'0-0 -> 2 3'001 ------------------------------------- FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572 (\Processor.N1.Second_Stage.Mdu.state_mul): Number of input signals: 2 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:77$197_Y Output signals: 0: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4448_CMP 1: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4452_CMP 2: $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4458_CMP State encoding: 0: 3'--1 <RESET STATE> 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 3'010 1: 0 2'-1 -> 0 3'010 2: 0 2'10 -> 2 3'010 3: 1 2'-- -> 0 3'100 4: 2 2'-1 -> 0 3'001 5: 2 2'-0 -> 1 3'001 ------------------------------------- FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577 (\Processor.N1.Third_Stage.unaligned_access_state): Number of input signals: 9 Number of output signals: 16 Number of state bits: 16 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\Processor.\N1.\Third_Stage.$reduce_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:240$123_Y 2: $flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:104$109_Y 3: $flatten\Processor.\N1.\Third_Stage.$logic_or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:96$107_Y 4: \Processor.N1.Third_Stage.data_memory_response 5: \Processor.N1.Third_Stage.subword 6: \Processor.N1.Third_Stage.subword_store 7: $flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:58$570_Y 8: $auto$opt_reduce.cc:137:opt_pmux$5551 Output signals: 0: $flatten\Processor.\N1.\Third_Stage.$procmux$4836_CMP 1: $flatten\Processor.\N1.\Third_Stage.$procmux$4830_CMP 2: $flatten\Processor.\N1.\Third_Stage.$procmux$4705_CMP 3: $flatten\Processor.\N1.\Third_Stage.$procmux$4696_CMP 4: $flatten\Processor.\N1.\Third_Stage.$procmux$4642_CMP 5: $flatten\Processor.\N1.\Third_Stage.$procmux$4641_CMP 6: $flatten\Processor.\N1.\Third_Stage.$procmux$4639_CMP 7: $flatten\Processor.\N1.\Third_Stage.$procmux$4637_CMP 8: $flatten\Processor.\N1.\Third_Stage.$procmux$4636_CMP 9: $flatten\Processor.\N1.\Third_Stage.$procmux$4620_CMP 10: $flatten\Processor.\N1.\Third_Stage.$procmux$4619_CMP 11: $flatten\Processor.\N1.\Third_Stage.$procmux$4618_CMP 12: $flatten\Processor.\N1.\Third_Stage.$procmux$4617_CMP 13: $flatten\Processor.\N1.\Third_Stage.$procmux$4614_CMP 14: $flatten\Processor.\N1.\Third_Stage.$procmux$4611_CMP 15: $flatten\Processor.\N1.\Third_Stage.$procmux$4608_CMP State encoding: 0: 16'---------------1 <RESET STATE> 1: 16'--------------1- 2: 16'-------------1-- 3: 16'------------1--- 4: 16'-----------1---- 5: 16'----------1----- 6: 16'---------1------ 7: 16'--------1------- 8: 16'-------1-------- 9: 16'------1--------- 10: 16'-----1---------- 11: 16'----1----------- 12: 16'---1------------ 13: 16'--1------------- 14: 16'-1-------------- 15: 16'1--------------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 9'-00--10-0 -> 0 16'0000001000000000 1: 0 9'-----0--0 -> 0 16'0000001000000000 2: 0 9'--------1 -> 0 16'0000001000000000 3: 0 9'-00--11-0 -> 2 16'0000001000000000 4: 0 9'-10--1--0 -> 8 16'0000001000000000 5: 0 9'--1--1--0 -> 13 16'0000001000000000 6: 1 9'--------1 -> 0 16'0000000000100000 7: 1 9'-----0--0 -> 1 16'0000000000100000 8: 1 9'0----1--0 -> 9 16'0000000000100000 9: 2 9'--------1 -> 0 16'0001000000000000 10: 2 9'-----0--0 -> 2 16'0001000000000000 11: 2 9'----01--0 -> 2 16'0001000000000000 12: 2 9'---111--0 -> 7 16'0001000000000000 13: 2 9'---011--0 -> 10 16'0001000000000000 14: 3 9'--------1 -> 0 16'0000000001000000 15: 3 9'--------0 -> 3 16'0000000001000000 16: 4 9'--------1 -> 0 16'0000100000000000 17: 4 9'-----0--0 -> 4 16'0000100000000000 18: 4 9'----01--0 -> 4 16'0000100000000000 19: 4 9'----11--0 -> 12 16'0000100000000000 20: 5 9'-----1--0 -> 0 16'0000000000001000 21: 5 9'--------1 -> 0 16'0000000000001000 22: 5 9'-----0--0 -> 5 16'0000000000001000 23: 6 9'--------1 -> 0 16'0010000000000000 24: 6 9'-----0--0 -> 6 16'0010000000000000 25: 6 9'----01--0 -> 6 16'0010000000000000 26: 6 9'----11--0 -> 14 16'0010000000000000 27: 7 9'--------1 -> 0 16'0000000010000000 28: 7 9'-----1-10 -> 6 16'0000000010000000 29: 7 9'-----0--0 -> 7 16'0000000010000000 30: 7 9'-----1-00 -> 11 16'0000000010000000 31: 8 9'--------1 -> 0 16'0000010000000000 32: 8 9'----11--0 -> 4 16'0000010000000000 33: 8 9'-----0--0 -> 8 16'0000010000000000 34: 8 9'----01--0 -> 8 16'0000010000000000 35: 9 9'----11--0 -> 0 16'0000000000000001 36: 9 9'--------1 -> 0 16'0000000000000001 37: 9 9'-----0--0 -> 9 16'0000000000000001 38: 9 9'----01--0 -> 9 16'0000000000000001 39: 10 9'--------1 -> 0 16'0000000000010000 40: 10 9'-----1--0 -> 6 16'0000000000010000 41: 10 9'-----0--0 -> 10 16'0000000000010000 42: 11 9'----11--0 -> 0 16'0000000000000010 43: 11 9'--------1 -> 0 16'0000000000000010 44: 11 9'-----0--0 -> 11 16'0000000000000010 45: 11 9'----01--0 -> 11 16'0000000000000010 46: 12 9'--------1 -> 0 16'0000000000000100 47: 12 9'-----1--0 -> 5 16'0000000000000100 48: 12 9'-----0--0 -> 12 16'0000000000000100 49: 13 9'--------1 -> 0 16'1000000000000000 50: 13 9'----11--0 -> 3 16'1000000000000000 51: 13 9'-----0--0 -> 13 16'1000000000000000 52: 13 9'----01--0 -> 13 16'1000000000000000 53: 14 9'--------1 -> 0 16'0100000000000000 54: 14 9'---011--0 -> 1 16'0100000000000000 55: 14 9'-----0--0 -> 14 16'0100000000000000 56: 14 9'----01--0 -> 14 16'0100000000000000 57: 14 9'---111--0 -> 15 16'0100000000000000 58: 15 9'--------1 -> 0 16'0000000100000000 59: 15 9'0----1--0 -> 9 16'0000000100000000 60: 15 9'-----0--0 -> 15 16'0000000100000000 ------------------------------------- 34.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$5554' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$5561' from module `\processorci_top'. Mapping FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_div$5567' from module `\processorci_top'. Mapping FSM `$fsm$\Processor.N1.Second_Stage.Mdu.state_mul$5572' from module `\processorci_top'. Mapping FSM `$fsm$\Processor.N1.Third_Stage.unaligned_access_state$5577' from module `\processorci_top'. 34.13. Executing OPT pass (performing simple optimizations). 34.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~32 debug messages> 34.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~102 debug messages> Removed a total of 34 cells. 34.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~247 debug messages> 34.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$5263 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$5261 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5376 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4672_Y, Q = \Processor.N1.Third_Stage.memory_operation_o). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5375 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y [7:0], Q = \Processor.N1.Third_Stage.Merged_Word_o [7:0]). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5375 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y [15:8], Q = \Processor.N1.Third_Stage.Merged_Word_o [15:8]). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5375 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y [31:16], Q = \Processor.N1.Third_Stage.Merged_Word_o [31:16]). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5374 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.IMMEDIATE_i, Q = \Processor.N1.Third_Stage.IMMEDIATE_REG_o). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5373 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4729_Y, Q = \Processor.N1.Third_Stage.EXMEMPC_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$5981 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4726_Y, Q = \Processor.N1.Third_Stage.EXMEMPC_o). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5372 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4741_Y, Q = \Processor.N1.Third_Stage.EXMEMIR_o, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$5989 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y, Q = \Processor.N1.Third_Stage.EXMEMIR_o). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5371 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:271$148_Y, Q = \Processor.N1.Third_Stage.EXMEMALUOut_o). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5370 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4780_Y, Q = \Processor.N1.Third_Stage.Data_Address). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5369 ($dff) from module processorci_top (D = \Processor.N1.Fourth_Stage.read_data_i, Q = \Processor.N1.Third_Stage.Second_Word). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5368 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4807_Y, Q = \Processor.N1.Third_Stage.First_Word). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5366 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4877_Y, Q = \Processor.N1.Third_Stage.subword, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6035 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$logic_not$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:223$170_Y, Q = \Processor.N1.Third_Stage.subword). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5365 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4899_Y, Q = \Processor.N1.Third_Stage.unaligned_access_in_progress, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6045 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4899_Y, Q = \Processor.N1.Third_Stage.unaligned_access_in_progress). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5364 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4944_Y [7:0], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0]). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5364 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4944_Y [15:8], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:8]). Adding EN signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5364 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4944_Y [31:16], Q = \Processor.N1.Third_Stage.EXMEM_mem_data_value [31:16]). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5363 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4643_Y, Q = \Processor.N1.Third_Stage.memory_write, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5362 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4621_Y, Q = \Processor.N1.Third_Stage.memory_read, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\Third_Stage.$procdff$5361 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4962_Y, Q = \Processor.N1.Third_Stage.subword_store, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6120 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4962_Y, Q = \Processor.N1.Third_Stage.subword_store). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5360 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4524_Y, Q = \Processor.N1.Second_Stage.Mdu.divisor). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5359 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4535_Y, Q = \Processor.N1.Second_Stage.Mdu.DIV_RD). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5358 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4544_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente_msk). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5357 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4557_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6155 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4557_Y, Q = \Processor.N1.Second_Stage.Mdu.quociente). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5356 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4570_Y, Q = \Processor.N1.Second_Stage.Mdu.dividendo). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5355 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4517_Y, Q = \Processor.N1.Second_Stage.Mdu.div_ready_o, rval = 1'0). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5354 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:223$178_Y, Q = \Processor.N1.Second_Stage.Mdu.negativo). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5352 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199_Y, Q = \Processor.N1.Second_Stage.Mdu.acumulador). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5351 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4477_Y, Q = \Processor.N1.Second_Stage.Mdu.Data_Y, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6187 ($sdff) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.MDU_RS2_i, Q = \Processor.N1.Second_Stage.Mdu.Data_Y). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5350 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4491_Y, Q = \Processor.N1.Second_Stage.Mdu.Data_X, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6191 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_data_in, Q = \Processor.N1.Second_Stage.Mdu.Data_X). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5348 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4497_Y, Q = \Processor.N1.Second_Stage.Mdu.MUL_RD, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6195 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:97$201_Y, Q = \Processor.N1.Second_Stage.Mdu.MUL_RD). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.\Mdu.$procdff$5347 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4457_Y, Q = \Processor.N1.Second_Stage.Mdu.mul_ready_o, rval = 1'0). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5295 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y, Q = \Processor.N1.Second_Stage.IDEXB). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5294 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y, Q = \Processor.N1.Second_Stage.IDEXA). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5293 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3507_Y, Q = \Processor.N1.Second_Stage.previous_instruction_is_lw, rval = 1'0). Adding EN signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5292 ($dff) from module processorci_top (D = \Processor.N1.Second_Stage.aluop_out, Q = \Processor.N1.Second_Stage.alu_op_o). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5290 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3514_Y, Q = \Processor.N1.Second_Stage.mdu_start, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5289 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3543_Y, Q = \Processor.N1.Second_Stage.mdu_operation_o, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6211 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3514_Y, Q = \Processor.N1.Second_Stage.mdu_operation_o). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5288 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3549_Y, Q = \Processor.N1.Second_Stage.IDEXPC_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6213 ($sdff) from module processorci_top (D = \Processor.N1.First_Stage.IFID_PC_o, Q = \Processor.N1.Second_Stage.IDEXPC_o). Adding SRST signal on $flatten\Processor.\N1.\Second_Stage.$procdff$5287 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.$procmux$3555_Y, Q = \Processor.N1.Second_Stage.IDEXIR_o, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$6215 ($sdff) from module processorci_top (D = \Processor.N1.First_Stage.IFID_IR_o, Q = \Processor.N1.Second_Stage.IDEXIR_o). Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5270 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEMIR_o, Q = \Processor.N1.Fourth_Stage.MEMWB_IR, rval = 51). Adding EN signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5269 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEMALUOut_o, Q = \Processor.N1.Fourth_Stage.MEMWBALUOut). Adding EN signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5268 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y, Q = \Processor.N1.Fourth_Stage.MEMWB_mem_read_data). Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5267 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$procmux$3001_Y, Q = \Processor.N1.Fourth_Stage.mem_to_reg, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\Fourth_Stage.$procdff$5265 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\Fourth_Stage.$procmux$3006_Y, Q = \Processor.N1.Fourth_Stage.reg_wr_en_o, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$procdff$5296 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$lookahead\prediction$348[1023:0]$392, Q = \Processor.N1.First_Stage.Branch_Prediction.prediction, rval = 1024'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6222 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$2$lookahead\prediction$348[1023:0]$392, Q = \Processor.N1.First_Stage.Branch_Prediction.prediction). Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5325 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.PC, Q = \Processor.N1.First_Stage.temp_pc). Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5324 ($dff) from module processorci_top (D = { 16'0000000000000000 \Processor.N1.First_Stage.instruction_data_i [31:16] }, Q = \Processor.N1.First_Stage.temp_instruction). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5322 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4138_Y, Q = \Processor.N1.First_Stage.finish_unaligned_pc, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6262 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4133_Y, Q = \Processor.N1.First_Stage.finish_unaligned_pc). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5321 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4182_Y, Q = \Processor.N1.First_Stage.pc_is_unaligned, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6270 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4182_Y, Q = \Processor.N1.First_Stage.pc_is_unaligned). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5318 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4217_Y, Q = \Processor.N1.First_Stage.PC, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6280 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4217_Y, Q = \Processor.N1.First_Stage.PC). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5316 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4066_Y, Q = \Processor.N1.First_Stage.flush_bus_o, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5315 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4235_Y, Q = \Processor.N1.First_Stage.IFID_IR_o, rval = 51). Adding EN signal on $auto$ff.cc:266:slice$6291 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4233_Y, Q = \Processor.N1.First_Stage.IFID_IR_o). Adding EN signal on $flatten\Processor.\N1.\First_Stage.$procdff$5314 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4277_Y, Q = \Processor.N1.First_Stage.IFID_PC_o). Adding SRST signal on $auto$ff.cc:266:slice$6295 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4265_Y, Q = \Processor.N1.First_Stage.IFID_PC_o, rval = 0). Adding SRST signal on $flatten\Processor.\N1.\First_Stage.$procdff$5313 ($dff) from module processorci_top (D = \Processor.N1.First_Stage.is_compressed_instruction, Q = \Processor.N1.First_Stage.IFID_is_compressed_instruction_o, rval = 1'0). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5390 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5059_Y, Q = \Processor.N1.CSR.MINSTRET_reg, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6310 ($sdff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68_Y, Q = \Processor.N1.CSR.MINSTRET_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5389 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67_Y, Q = \Processor.N1.CSR.MCYCLE_reg, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5388 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$4987_Y, Q = \Processor.N1.CSR.MSCRATCH_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6313 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MSCRATCH_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5387 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$4999_Y, Q = \Processor.N1.CSR.MTVEC_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6317 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MTVEC_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5386 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5007_Y, Q = \Processor.N1.CSR.MIE_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6321 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MIE_reg). Adding EN signal on $flatten\Processor.\N1.\CSR.$procdff$5385 ($dff) from module processorci_top (D = 0, Q = \Processor.N1.CSR.MIP_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5384 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5018_Y, Q = \Processor.N1.CSR.MTVAL_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6326 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MTVAL_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5383 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5027_Y, Q = \Processor.N1.CSR.MCAUSE_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6330 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MCAUSE_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5382 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5041_Y, Q = \Processor.N1.CSR.MSTATUS_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6334 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MSTATUS_reg). Adding SRST signal on $flatten\Processor.\N1.\CSR.$procdff$5381 ($dff) from module processorci_top (D = $flatten\Processor.\N1.\CSR.$procmux$5051_Y, Q = \Processor.N1.CSR.MEPC_reg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6338 ($sdff) from module processorci_top (D = \Processor.N1.CSR.csr_write_data, Q = \Processor.N1.CSR.MEPC_reg). Adding SRST signal on $flatten\Processor.\M1.$procdff$5280 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3126_Y, Q = \Processor.M1.d_cache_response, rval = 1'0). Adding SRST signal on $flatten\Processor.\M1.$procdff$5279 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3134_Y, Q = \Processor.M1.i_cache_response, rval = 1'0). Adding EN signal on $flatten\Processor.\M1.$procdff$5278 ($dff) from module processorci_top (D = \Processor.M1.memory_read_data, Q = \Processor.M1.d_cache_read_data). Adding EN signal on $flatten\Processor.\M1.$procdff$5277 ($dff) from module processorci_top (D = \Processor.M1.memory_read_data, Q = \Processor.M1.i_cache_read_data). Adding SRST signal on $flatten\Processor.\M1.$procdff$5276 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3164_Y, Q = \Processor.M1.access_pedding, rval = 1'0). Adding SRST signal on $flatten\Processor.\M1.$procdff$5275 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3174_Y, Q = \Processor.M1.response_out, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6365 ($sdff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3172_Y, Q = \Processor.M1.response_out). Adding SRST signal on $flatten\Processor.\M1.$procdff$5274 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3184_Y, Q = \Processor.M1.requested_memory_addr, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6373 ($sdff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3182_Y, Q = \Processor.M1.requested_memory_addr). Adding SRST signal on $flatten\Processor.\M1.$procdff$5273 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3196_Y, Q = \Processor.M1.write_request, rval = 1'0). Adding EN signal on $flatten\Processor.\M1.$procdff$5272 ($dff) from module processorci_top (D = \Processor.N1.Third_Stage.EXMEM_mem_data_value, Q = \Processor.M1.write_data). Adding SRST signal on $flatten\Processor.\M1.$procdff$5271 ($dff) from module processorci_top (D = $flatten\Processor.\M1.$procmux$3216_Y, Q = \Processor.M1.read_request, rval = 1'0). Adding SRST signal on $flatten\Processor.\ICache.$procdff$5394 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$2$lookahead\cache_valid$16[7:0]$55, Q = \Processor.ICache.cache_valid, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6390 ($sdff) from module processorci_top (D = $flatten\Processor.\ICache.$or$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$63_Y, Q = \Processor.ICache.cache_valid). Adding SRST signal on $flatten\Processor.\ICache.$procdff$5392 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$procmux$5161_Y, Q = \Processor.ICache.clear_response, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6392 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.ICache.clear_response). Adding SRST signal on $flatten\Processor.\ICache.$procdff$5391 ($dff) from module processorci_top (D = $flatten\Processor.\ICache.$procmux$5168_Y, Q = \Processor.ICache.request_to_memory, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6396 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.ICache.request_to_memory). Adding SRST signal on $flatten\Processor.\DCache.$procdff$5330 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$procmux$4438_Y, Q = \Processor.DCache.write_through, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6400 ($sdff) from module processorci_top (D = 1'1, Q = \Processor.DCache.write_through). Adding SRST signal on $flatten\Processor.\DCache.$procdff$5329 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$3$lookahead\cache_valid$223[7:0]$282, Q = \Processor.DCache.cache_valid, rval = 8'00000000). Adding SRST signal on $flatten\Processor.\DCache.$procdff$5328 ($dff) from module processorci_top (D = $flatten\Processor.\DCache.$procmux$4432_Y, Q = \Processor.DCache.miss_finished, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5205 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1902_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1896_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1887_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1878_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1869_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1860_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1842_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1851_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6406 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$6406 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1896_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1887_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1878_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1869_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1860_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1842_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1851_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5203 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1818_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6411 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1818_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5202 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1807_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6417 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1532_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5201 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$5200 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1796_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$6422 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1796_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5199 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1785_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6428 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5197 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1762_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1753_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1744_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1735_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1726_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1717_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1699_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1708_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6430 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5196 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1681_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6434 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1572_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5195 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1676_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6438 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5194 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1668_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6440 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1583_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5192 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$5191 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5190 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1645_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6446 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5189 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1389_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$5185 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1640_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6453 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5190 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1645_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6455 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5189 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1389_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$5185 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1640_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6462 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5253 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2816_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6464 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2816_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5252 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2841_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6468 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2841_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5251 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2805_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5250 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2856_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6485 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2854_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5249 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2794_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5248 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2738_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6492 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2738_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5247 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2760_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6496 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2760_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5246 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2774_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6506 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2774_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5245 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2788_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6516 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5244 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2720_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5243 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2730_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5242 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2711_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6530 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5241 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2706_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5239 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2701_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6533 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5238 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2677_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$5237 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2685_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5236 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2224_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5235 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2267_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6550 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2267_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$6550 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2267_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5234 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2277_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6565 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2277_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5233 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5232 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2318_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5231 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2346_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6581 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5230 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2371_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5229 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2393_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6592 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5228 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2399_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6594 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2399_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5227 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2423_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5226 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2431_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6609 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2431_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5225 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2471_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6613 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2471_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5223 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2513_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6617 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2513_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5222 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2052_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5221 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2524_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5220 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2157_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5219 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2534_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6630 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2534_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5218 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5217 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2176_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5216 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2199_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5215 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2588_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5214 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2109_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5213 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2642_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6655 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2642_Y, Q = \Controller.Interpreter.counter). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5212 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1952_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$5211 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2666_Y, Q = \Controller.Interpreter.write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5210 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2076_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$5209 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2098_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$5206 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1926_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6669 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1926_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$5260 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2877_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6677 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2877_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6569 ($dffe) from module processorci_top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6325 ($dffe) from module processorci_top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6247 ($dffe) from module processorci_top. 34.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 300 unused cells and 370 unused wires. <suppressed ~301 debug messages> 34.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~42 debug messages> 34.13.9. Rerunning OPT passes. (Maybe there is more to do..) 34.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~187 debug messages> 34.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6436: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] } New ctrl vector for $pmux cell $flatten\Processor.\N1.\CSR.$procmux$5065: { $auto$opt_reduce.cc:137:opt_pmux$5457 $auto$opt_reduce.cc:137:opt_pmux$5455 $auto$opt_reduce.cc:137:opt_pmux$5453 $auto$opt_reduce.cc:137:opt_pmux$5451 $flatten\Processor.\N1.\CSR.$procmux$5074_CMP $flatten\Processor.\N1.\CSR.$procmux$5040_CMP $flatten\Processor.\N1.\CSR.$procmux$5006_CMP $flatten\Processor.\N1.\CSR.$procmux$4998_CMP $flatten\Processor.\N1.\CSR.$procmux$4986_CMP $flatten\Processor.\N1.\CSR.$procmux$5050_CMP $flatten\Processor.\N1.\CSR.$procmux$5026_CMP $flatten\Processor.\N1.\CSR.$procmux$5017_CMP } Optimizing cells in module \processorci_top. Performed a total of 2 changes. 34.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~333 debug messages> Removed a total of 111 cells. 34.13.13. Executing OPT_DFF pass (perform DFF optimizations). 34.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 112 unused wires. <suppressed ~2 debug messages> 34.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.13.16. Rerunning OPT passes. (Maybe there is more to do..) 34.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~188 debug messages> 34.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.13.20. Executing OPT_DFF pass (perform DFF optimizations). 34.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.13.23. Finished OPT passes. (There is nothing left to do.) 34.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$5404 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1199 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$5404 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1199 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5403 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1389 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$5403 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1389 (Controller.Uart.TX_FIFO.memory). Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Processor.\N1.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$5413 (Processor.N1.RegisterBank.registers). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5615 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5604 ($eq). Removed top 2 bits (of 5) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5739 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5922 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5629 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5830 ($eq). Removed top 4 bits (of 5) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5931 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5654 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1490 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1447 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1451 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1454 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1463 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1468 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1470 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1953_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1954_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1956 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1958_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1959_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1960_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1961_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1962_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1964 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1966_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1967_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1969 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1971_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1972_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1976_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1977_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1978_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1980 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1982_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1983_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1984_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1986 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1988_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1990 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1992_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1993_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1994_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1995_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1996_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1997_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1998_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2000 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2002_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2004 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2006_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2007_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2009 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2011_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2012_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2015_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2014 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2016_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2017_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2018_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2019_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2020_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2021_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2022_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2023_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2024_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2025_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2026_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2027_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2028_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2029_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2030_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2031_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2032_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2033_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2034_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2035_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2036_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2037_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2038_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2040 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2044 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2078_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2079_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2080_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2113_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2268_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2269_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2270_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2313_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2439_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2472_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2473_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2546_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2547_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1421 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1426 ($lt). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2725_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2731_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2732_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2744_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2746 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2795_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2796_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2810_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2818_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2826 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1637 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1625 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1406 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1390 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1637 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1625 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1406 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1390 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5908 ($ne). Removed top 2 bits (of 5) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5709 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1561 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1560 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1559 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1558 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1553 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1551 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1527 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1519 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1517 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1514 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1513 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1509 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1504 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1503 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1502 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1501 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1497 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1495 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2868 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2868 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$1176 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1160 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1159 ($mux). Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5841 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5885 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6050 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5984 ($ne). Removed top 2 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6010 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6014 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6063 ($ne). Removed top 1 bits (of 7) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6067 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6125 ($ne). Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6227 ($ne). Removed top 2 bits (of 6) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6275 ($ne). Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6277 ($ne). Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5941 ($ne). Removed top 28 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\DCache.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$215 ($shiftx). Removed top 29 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268 ($neg). Converting cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268 ($neg) from signed to unsigned. Removed top 1 bits (of 4) from port A of cell processorci_top.$flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268 ($neg). Removed top 28 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\ICache.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$9 ($shiftx). Removed top 29 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg). Converting cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg) from signed to unsigned. Removed top 1 bits (of 4) from port A of cell processorci_top.$flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg). Removed top 29 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$479 ($mux). Removed top 22 bits (of 32) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$345 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$345 ($add). Removed top 21 bits (of 32) from port Y of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$345 ($add). Removed top 20 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$346 ($shiftx). Removed top 21 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$400 ($shiftx). Removed top 22 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405 ($neg). Converting cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405 ($neg) from signed to unsigned. Removed top 1 bits (of 11) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405 ($neg). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$411 ($add). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$427 ($sub). Removed top 21 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$462 ($shiftx). Removed top 22 bits (of 33) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467 ($neg). Converting cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467 ($neg) from signed to unsigned. Removed top 1 bits (of 11) from port A of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467 ($neg). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$473 ($add). Removed top 3 bits (of 5) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/ir_decomp.sv:104$523 ($eq). Removed top 11 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3225 ($mux). Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3241 ($mux). Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3271 ($mux). Removed top 7 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3306 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3320_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3337_CMP1 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3358_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3359_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3360_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3367_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3392_CMP1 ($eq). Removed top 3 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3435 ($mux). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333 ($add). Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$313 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:233$179 ($eq). Removed top 31 bits (of 63) from port Y of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181 ($sub). Removed top 31 bits (of 63) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181 ($sub). Removed top 32 bits (of 64) from port A of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199 ($mul). Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199 ($mul). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ForwardBMUX.$procmux$2925_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ForwardAMUX.$procmux$2925_CMP0 ($eq). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2928 ($mux). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2935 ($mux). Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$procmux$2943 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ne$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:26$581 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$592 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$594 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$598 ($mux). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2981_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2982_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2983_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2988_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2992_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2993_CMP0 ($eq). Removed top 2 bits (of 4) from mux cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$549 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3032_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3033_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3034_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$procmux$3048_CMP0 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6217 ($sdff). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP4 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP3 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP2 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP1 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3570_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3562_CMP3 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3562_CMP2 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3562_CMP1 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$procmux$3562_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:104$515 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Second_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:97$514 ($eq). Removed top 22 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$5982 ($sdffe). Removed top 17 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$5990 ($sdffe). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6672 ($ne). Removed top 16 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4923 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4920_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4919_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6682 ($ne). Removed top 17 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4738 ($mux). Removed top 17 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4735 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4726 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4723 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:127$111 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:116$110 ($add). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Third_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:104$109 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$procmux$3024_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:58$570 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:57$568 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:55$561 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:54$559 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Processor.\N1.\Fourth_Stage.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:53$558 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5074_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5050_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5040_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5026_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5017_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5006_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$5005_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$4998_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$4986_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Processor.\N1.\CSR.$procmux$4980_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2894_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1146 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1144 ($lt). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1159_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_ADDR[31:0]$1203. Removed top 3 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1199_DATA. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1956_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1964_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1969_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1980_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1986_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1990_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2000_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2004_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2009_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2014_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2040_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$2044_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1197_ADDR[31:0]$1203. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2746_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2826_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1394. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1403. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1394. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1384_ADDR[5:0]$1403. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1392_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1408_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1558_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1559_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1560_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1561_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1501_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1502_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1503_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1504_Y. Removed top 21 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$345_Y. Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$10\instr_d_o[31:0]. Removed top 11 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$11\instr_d_o[31:0]. Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$8\instr_d_o[31:0]. Removed top 7 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$9\instr_d_o[31:0]. Removed top 29 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$479_Y. Removed top 2 bits (of 4) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$549_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$592_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$594_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Alu.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$598_Y. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$2\fwd_rs1_o[1:0]. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$3\fwd_rs1_o[1:0]. Removed top 1 bits (of 2) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Forwarding_Unit.$3\fwd_rs2_o[1:0]. Removed top 31 bits (of 63) from wire processorci_top.$flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4723_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4726_Y. Removed top 20 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4735_Y. Removed top 17 bits (of 32) from wire processorci_top.$flatten\Processor.\N1.\Third_Stage.$procmux$4738_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145_Y. 34.15. Executing PEEPOPT pass (run peephole optimizers). shiftadd pattern in processorci_top: shift=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$shiftx$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$346, add/sub=$flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$345, offset: 1 34.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 58 unused wires. <suppressed ~2 debug messages> 34.17. Executing SHARE pass (SAT-based resource sharing). Found 9 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2981_CMP. No candidates found. Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$602 ($shr): Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2982_CMP. No candidates found. Analyzing resource sharing options for $flatten\Processor.\N1.\Second_Stage.\Alu.$shl$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:45$601 ($shl): Found 1 activation_patterns using ctrl signal $flatten\Processor.\N1.\Second_Stage.\Alu.$procmux$2983_CMP. No candidates found. Analyzing resource sharing options for $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:20$89 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y }. Found 1 candidates: $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83 Analyzing resource sharing with $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y }. Activation pattern for cell $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:20$89: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y } = 2'01 Activation pattern for cell $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y } = 2'01 Size of SAT problem: 0 cells, 594 variables, 1410 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:18$88_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y } = 3'001 Analyzing resource sharing options for $flatten\Processor.\N1.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:16$83 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\Processor.\N1.\RegisterBank.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/registers.sv:14$82_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$328_Y }. No candidates found. Analyzing resource sharing options for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$memrd$\address_to_jump$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:82$343 ($memrd): Found 1 activation_patterns using ctrl signal { \Processor.N1.Second_Stage.branch_flush_i \Processor.N1.Second_Stage.take_jalr_o \Processor.N1.First_Stage.pc_is_unaligned \Processor.N1.First_Stage.finish_unaligned_pc \Processor.N1.First_Stage.take_jal_o $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:151$325_Y $flatten\Processor.\N1.\First_Stage.$logic_and$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:154$330_Y \Processor.N1.First_Stage.Branch_Prediction.prediction_taken_o }. No candidates found. Analyzing resource sharing options for $flatten\Processor.\DCache.$memrd$\cache_data$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:79$222 ($memrd): Found 1 activation_patterns using ctrl signal \Processor.N1.Third_Stage.Data_Address [31]. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1199 ($memrd): Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1996_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1199 ($memrd): Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1996_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }. No candidates found. 34.18. Executing TECHMAP pass (map to technology primitives). 34.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 34.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. No more expansions possible. <suppressed ~223 debug messages> 34.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 34.21. Executing TECHMAP pass (map to technology primitives). 34.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 34.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 34.21.3. Continuing TECHMAP pass. Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul. Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul. Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul. Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul. Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul. Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul. Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul. Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. <suppressed ~670 debug messages> 34.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6756 ($add). creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6753 ($add). creating $macc model for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.$add$/usr/local/share/synlig/mul2dsp.v:173$6750 ($add). creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1491 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1446 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1450 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1451 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1454 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1461 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1465 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1453 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1428 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1423 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1572 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1583 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1521 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1532 ($add). creating $macc model for $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268 ($neg). creating $macc model for $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57 ($neg). creating $macc model for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67 ($add). creating $macc model for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$306 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$310 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$313 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$411 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$473 ($add). creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405 ($neg). creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467 ($neg). creating $macc model for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$427 ($sub). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$586 ($add). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587 ($sub). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$163 ($neg). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$167 ($neg). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$187 ($neg). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$189 ($neg). creating $macc model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181 ($sub). creating $macc model for $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:116$110 ($add). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145 ($add). creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145. creating $alu model for $macc $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:116$110. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$189. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$187. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$167. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$163. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587. creating $alu model for $macc $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$586. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$427. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$473. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$411. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$313. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$310. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$306. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333. creating $alu model for $macc $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332. creating $alu model for $macc $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68. creating $alu model for $macc $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67. creating $alu model for $macc $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57. creating $alu model for $macc $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1532. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1521. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1583. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1572. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1423. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1428. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1453. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1465. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1461. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1454. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1451. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1450. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1446. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1491. creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.$add$/usr/local/share/synlig/mul2dsp.v:173$6750. creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6753. creating $alu model for $macc $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6756. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1490 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1470 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1463 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1470. creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$597 ($ge): merged with $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587. creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$593 ($lt): merged with $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587. creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Mdu.$le$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:240$180 ($le): new $alu creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1144 ($lt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1468 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1470. creating $alu model for $flatten\Processor.\N1.\Second_Stage.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$591 ($eq): merged with $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1146 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1144. creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1144, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1146: $auto$alumacc.cc:485:replace_alu$6769 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$le$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:240$180: $auto$alumacc.cc:485:replace_alu$6780 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1470, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1463, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1468: $auto$alumacc.cc:485:replace_alu$6793 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1490: $auto$alumacc.cc:485:replace_alu$6806 creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/local/share/synlig/mul2dsp.v:230$6756: $auto$alumacc.cc:485:replace_alu$6811 creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/usr/local/share/synlig/mul2dsp.v:230$6753: $auto$alumacc.cc:485:replace_alu$6814 creating $alu cell for $techmap$flatten\Processor.\N1.\Second_Stage.\Mdu.$mul$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:91$199.$add$/usr/local/share/synlig/mul2dsp.v:173$6750: $auto$alumacc.cc:485:replace_alu$6817 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1491: $auto$alumacc.cc:485:replace_alu$6820 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1446: $auto$alumacc.cc:485:replace_alu$6823 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1450: $auto$alumacc.cc:485:replace_alu$6826 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1451: $auto$alumacc.cc:485:replace_alu$6829 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1454: $auto$alumacc.cc:485:replace_alu$6832 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1461: $auto$alumacc.cc:485:replace_alu$6835 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1465: $auto$alumacc.cc:485:replace_alu$6838 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1453: $auto$alumacc.cc:485:replace_alu$6841 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1428: $auto$alumacc.cc:485:replace_alu$6844 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1423: $auto$alumacc.cc:485:replace_alu$6847 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391: $auto$alumacc.cc:485:replace_alu$6850 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407: $auto$alumacc.cc:485:replace_alu$6853 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409: $auto$alumacc.cc:485:replace_alu$6856 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1391: $auto$alumacc.cc:485:replace_alu$6859 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1407: $auto$alumacc.cc:485:replace_alu$6862 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1409: $auto$alumacc.cc:485:replace_alu$6865 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1572: $auto$alumacc.cc:485:replace_alu$6868 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1583: $auto$alumacc.cc:485:replace_alu$6871 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1521: $auto$alumacc.cc:485:replace_alu$6874 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1532: $auto$alumacc.cc:485:replace_alu$6877 creating $alu cell for $flatten\Processor.\DCache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/d_cache.sv:0$268: $auto$alumacc.cc:485:replace_alu$6880 creating $alu cell for $flatten\Processor.\ICache.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/i_cache.sv:0$57: $auto$alumacc.cc:485:replace_alu$6883 creating $alu cell for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:141$67: $auto$alumacc.cc:485:replace_alu$6886 creating $alu cell for $flatten\Processor.\N1.\CSR.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/csr_unit.sv:143$68: $auto$alumacc.cc:485:replace_alu$6889 creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332: $auto$alumacc.cc:485:replace_alu$6892 creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333: $auto$alumacc.cc:485:replace_alu$6895 creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:90$306: $auto$alumacc.cc:485:replace_alu$6898 creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:93$310: $auto$alumacc.cc:485:replace_alu$6901 creating $alu cell for $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:96$313: $auto$alumacc.cc:485:replace_alu$6904 creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:61$411: $auto$alumacc.cc:485:replace_alu$6907 creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:76$473: $auto$alumacc.cc:485:replace_alu$6910 creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$405: $auto$alumacc.cc:485:replace_alu$6913 creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:0$467: $auto$alumacc.cc:485:replace_alu$6916 creating $alu cell for $flatten\Processor.\N1.\First_Stage.\Branch_Prediction.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/branch_prediction.sv:65$427: $auto$alumacc.cc:485:replace_alu$6919 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Alu.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:32$586: $auto$alumacc.cc:485:replace_alu$6922 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Alu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:33$587, $flatten\Processor.\N1.\Second_Stage.\Alu.$ge$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:41$597, $flatten\Processor.\N1.\Second_Stage.\Alu.$lt$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:39$593, $flatten\Processor.\N1.\Second_Stage.\Alu.$eq$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:36$591: $auto$alumacc.cc:485:replace_alu$6925 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:221$163: $auto$alumacc.cc:485:replace_alu$6938 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:222$167: $auto$alumacc.cc:485:replace_alu$6941 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:254$187: $auto$alumacc.cc:485:replace_alu$6944 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$neg$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:256$189: $auto$alumacc.cc:485:replace_alu$6947 creating $alu cell for $flatten\Processor.\N1.\Second_Stage.\Mdu.$sub$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/mdu.sv:241$181: $auto$alumacc.cc:485:replace_alu$6950 creating $alu cell for $flatten\Processor.\N1.\Third_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/EXMEM.sv:116$110: $auto$alumacc.cc:485:replace_alu$6953 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1145: $auto$alumacc.cc:485:replace_alu$6956 created 50 $alu and 0 $macc cells. 34.23. Executing OPT pass (performing simple optimizations). 34.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 34.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~188 debug messages> 34.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 34.23.6. Executing OPT_DFF pass (perform DFF optimizations). 34.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 63 unused wires. <suppressed ~1 debug messages> 34.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.23.9. Rerunning OPT passes. (Maybe there is more to do..) 34.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~188 debug messages> 34.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.23.13. Executing OPT_DFF pass (perform DFF optimizations). 34.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.23.16. Finished OPT passes. (There is nothing left to do.) 34.24. Executing MEMORY pass. 34.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 34.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 34.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.Processor.DCache.cache_data write port 0. Analyzing processorci_top.Processor.DCache.cache_data write port 1. Analyzing processorci_top.Processor.DCache.cache_tag write port 0. Analyzing processorci_top.Processor.DCache.cache_tag write port 1. Analyzing processorci_top.Processor.ICache.cache_data write port 0. Analyzing processorci_top.Processor.ICache.cache_tag write port 0. Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 0. Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 1. Analyzing processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump write port 2. Analyzing processorci_top.Processor.N1.RegisterBank.registers write port 0. Analyzing processorci_top.Processor.N1.RegisterBank.registers write port 1. 34.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 34.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Processor.DCache.cache_data'[0] in module `\processorci_top': no output FF found. Checking read port `\Processor.DCache.cache_tag'[0] in module `\processorci_top': no output FF found. Checking read port `\Processor.ICache.cache_data'[0] in module `\processorci_top': no output FF found. Checking read port `\Processor.ICache.cache_tag'[0] in module `\processorci_top': no output FF found. Checking read port `\Processor.N1.First_Stage.Branch_Prediction.address_to_jump'[0] in module `\processorci_top': no output FF found. Checking read port `\Processor.N1.RegisterBank.registers'[0] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic. Checking read port `\Processor.N1.RegisterBank.registers'[1] in module `\processorci_top': FF found, but with a mux select that doesn't seem to correspond to transparency logic. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Processor.DCache.cache_data'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.DCache.cache_tag'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.ICache.cache_data'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.ICache.cache_tag'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.N1.First_Stage.Branch_Prediction.address_to_jump'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.N1.RegisterBank.registers'[0] in module `\processorci_top': merged address FF to cell. Checking read port address `\Processor.N1.RegisterBank.registers'[1] in module `\processorci_top': merged address FF to cell. 34.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 18 unused wires. <suppressed ~3 debug messages> 34.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory processorci_top.Processor.DCache.cache_data by address: Merging ports 0, 1 (address \Processor.N1.Third_Stage.Data_Address [4:2]). Consolidating write ports of memory processorci_top.Processor.DCache.cache_tag by address: Merging ports 0, 1 (address \Processor.N1.Third_Stage.Data_Address [4:2]). Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump by address: Merging ports 0, 1 (address \Processor.N1.Second_Stage.IDEXPC_o [9:1]). Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump by address: Consolidating read ports of memory processorci_top.Processor.N1.RegisterBank.registers by address: Consolidating write ports of memory processorci_top.Processor.N1.RegisterBank.registers by address: Consolidating write ports of memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump using sat-based resource sharing: Checking group clocked with posedge \Processor.DCache.clk, width 32: ports 0, 1. Common input cone for all EN signals: 86 cells. Size of unconstrained SAT problem: 5574 variables, 14673 clauses Merging port 1 into port 0. 34.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 34.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 10 unused cells and 10 unused wires. <suppressed ~11 debug messages> 34.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 34.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] mapping memory processorci_top.Processor.DCache.cache_data via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of processorci_top.Processor.DCache.cache_data: $\Processor.DCache.cache_data$rdreg[0] mapping memory processorci_top.Processor.DCache.cache_tag via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of processorci_top.Processor.DCache.cache_tag: $\Processor.DCache.cache_tag$rdreg[0] mapping memory processorci_top.Processor.ICache.cache_data via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of processorci_top.Processor.ICache.cache_data: $\Processor.ICache.cache_data$rdreg[0] mapping memory processorci_top.Processor.ICache.cache_tag via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of processorci_top.Processor.ICache.cache_tag: $\Processor.ICache.cache_tag$rdreg[0] mapping memory processorci_top.Processor.N1.First_Stage.Branch_Prediction.address_to_jump via $__ECP5_PDPW16KD_ using FF mapping for memory processorci_top.Processor.N1.RegisterBank.registers <suppressed ~3395 debug messages> 34.27. Executing TECHMAP pass (map to technology primitives). 34.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 34.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 34.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$02d10cc8049219b734b94ed56325542341e7b150\$__ECP5_PDPW16KD_ for cells of type $__ECP5_PDPW16KD_. No more expansions possible. <suppressed ~1100 debug messages> 34.28. Executing OPT pass (performing simple optimizations). 34.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~353 debug messages> 34.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 34.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$5262 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$8232 ($dffe) from module processorci_top. Adding SRST signal on $\Processor.ICache.cache_data$rdreg[0] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$6996, Q = $\Processor.ICache.cache_data$rdreg[0]$q, rval = 3'000). Adding SRST signal on $auto$ff.cc:266:slice$6602 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1465_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6541 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2224_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding EN signal on $auto$ff.cc:266:slice$6281 ($sdffe) from module processorci_top (D = $flatten\Processor.\N1.\First_Stage.$procmux$4217_Y [0], Q = \Processor.N1.First_Stage.PC [0]). Adding SRST signal on $auto$ff.cc:266:slice$6146 ($dffe) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.quociente_msk [31:1], Q = \Processor.N1.Second_Stage.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000). Adding SRST signal on $auto$ff.cc:266:slice$6132 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4527_Y [62], Q = \Processor.N1.Second_Stage.Mdu.divisor [62], rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6008 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4780_Y [1:0], Q = \Processor.N1.Third_Stage.Data_Address [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$5918 ($dffe) from module processorci_top (D = $flatten\Processor.\N1.\Third_Stage.$procmux$4652_Y, Q = \Processor.N1.Third_Stage.memory_operation_o, rval = 1'0). Adding SRST signal on $auto$ff.cc:266:slice$5902 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2891_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 34.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 13 unused cells and 7602 unused wires. <suppressed ~14 debug messages> 34.28.5. Rerunning OPT passes. (Removed registers in this run.) 34.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~10 debug messages> 34.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 34.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$9533 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$6743 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). Adding SRST signal on $auto$ff.cc:266:slice$9525 ($dffe) from module processorci_top (D = \Processor.N1.Second_Stage.Mdu.divisor [31:1], Q = \Processor.N1.Second_Stage.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000). 34.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 7 unused wires. <suppressed ~2 debug messages> 34.28.10. Rerunning OPT passes. (Removed registers in this run.) 34.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.28.13. Executing OPT_DFF pass (perform DFF optimizations). 34.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.28.15. Finished fast OPT passes. 34.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \Processor.N1.RegisterBank.registers in module \processorci_top: created 32 $dff cells and 0 static cells of width 32. Extracted addr FF from read port 0 of processorci_top.Processor.N1.RegisterBank.registers: $\Processor.N1.RegisterBank.registers$rdreg[0] Extracted addr FF from read port 1 of processorci_top.Processor.N1.RegisterBank.registers: $\Processor.N1.RegisterBank.registers$rdreg[1] read interface: 2 $dff and 62 $mux cells. write interface: 64 write mux blocks. 34.30. Executing OPT pass (performing simple optimizations). 34.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~88 debug messages> 34.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$7038: $auto$rtlil.cc:2728:ReduceOr$7032 -> 1'1 Analyzing evaluation results. dead port 1/2 on $mux $memory\Processor.N1.RegisterBank.registers$wrmux[0][0][0]$9811. dead port 2/2 on $mux $memory\Processor.N1.RegisterBank.registers$wrmux[0][0][0]$9811. Removed 2 multiplexer ports. <suppressed ~166 debug messages> 34.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9530: { $auto$opt_dff.cc:194:make_patterns_logic$9527 $auto$fsm_map.cc:74:implement_pattern_cache$5696 $auto$opt_dff.cc:194:make_patterns_logic$6013 $auto$opt_dff.cc:194:make_patterns_logic$6011 $auto$opt_dff.cc:194:make_patterns_logic$6009 $auto$opt_dff.cc:194:make_patterns_logic$5921 } New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9508: { $auto$opt_dff.cc:194:make_patterns_logic$9505 $auto$opt_dff.cc:194:make_patterns_logic$6544 $auto$opt_dff.cc:194:make_patterns_logic$6542 $auto$fsm_map.cc:74:implement_pattern_cache$5649 } New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9520: { $auto$opt_dff.cc:194:make_patterns_logic$9511 $auto$opt_dff.cc:194:make_patterns_logic$9513 $auto$opt_dff.cc:194:make_patterns_logic$9515 $auto$opt_dff.cc:194:make_patterns_logic$9517 $auto$opt_dff.cc:194:make_patterns_logic$6272 $auto$opt_dff.cc:194:make_patterns_logic$6274 $auto$opt_dff.cc:194:make_patterns_logic$6276 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1159: Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$6687 [11:0] New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$6687 [11:6] New connections: $auto$wreduce.cc:461:run$6687 [5:0] = \Controller.core_address_memory [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1964: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$6691 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$6691 [2] $auto$wreduce.cc:461:run$6691 [0] } New connections: $auto$wreduce.cc:461:run$6691 [1] = $auto$wreduce.cc:461:run$6691 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1969: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$6692 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6692 [1:0] New connections: $auto$wreduce.cc:461:run$6692 [6:2] = { $auto$wreduce.cc:461:run$6692 [1] 3'010 $auto$wreduce.cc:461:run$6692 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1980: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$6693 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6693 [2] New connections: { $auto$wreduce.cc:461:run$6693 [3] $auto$wreduce.cc:461:run$6693 [1:0] } = { $auto$wreduce.cc:461:run$6693 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1990: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$6695 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6695 [0] New connections: $auto$wreduce.cc:461:run$6695 [3:1] = { $auto$wreduce.cc:461:run$6695 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$2004: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$6697 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6697 [0] New connections: $auto$wreduce.cc:461:run$6697 [6:1] = { $auto$wreduce.cc:461:run$6697 [0] 1'0 $auto$wreduce.cc:461:run$6697 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2399: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2399_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2399_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$2399_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2524: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2524_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2524_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2524_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2534: $auto$opt_reduce.cc:137:opt_pmux$5499 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2738: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$6703 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2738_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$6703 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2738_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2738_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2746: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$6703 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6703 [2] New connections: $auto$wreduce.cc:461:run$6703 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2822: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2822_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2822_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2822_Y [3] $flatten\Controller.\Uart.$procmux$2822_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1780: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$6717 [0] 1'0 $auto$wreduce.cc:461:run$6718 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$6720 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$6717 [0] $auto$wreduce.cc:461:run$6718 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$6720 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1561: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6720 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6720 [0] New connections: $auto$wreduce.cc:461:run$6720 [1] = $auto$wreduce.cc:461:run$6720 [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1917: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$6722 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$6724 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$6722 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$6724 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1504: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6724 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6724 [0] New connections: $auto$wreduce.cc:461:run$6724 [1] = $auto$wreduce.cc:461:run$6724 [0] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.$procmux$4191: Old ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333_Y [31:2] \Processor.N1.First_Stage.PC [1] 1'x }, B={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332_Y [31:1] 1'x }, Y=$flatten\Processor.\N1.\First_Stage.$procmux$4191_Y New ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333_Y [31:2] \Processor.N1.First_Stage.PC [1] }, B=$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332_Y [31:1], Y=$flatten\Processor.\N1.\First_Stage.$procmux$4191_Y [31:1] New connections: $flatten\Processor.\N1.\First_Stage.$procmux$4191_Y [0] = 1'x Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.$procmux$4198: Old ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333_Y [31:2] \Processor.N1.First_Stage.PC [1] 1'x }, B={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332_Y [31:1] 1'x }, Y=$flatten\Processor.\N1.\First_Stage.$procmux$4198_Y New ports: A={ $flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:175$333_Y [31:2] \Processor.N1.First_Stage.PC [1] }, B=$flatten\Processor.\N1.\First_Stage.$add$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IFID.sv:172$332_Y [31:1], Y=$flatten\Processor.\N1.\First_Stage.$procmux$4198_Y [31:1] New connections: $flatten\Processor.\N1.\First_Stage.$procmux$4198_Y [0] = 1'x Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3225: Old ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 15'000000011100111 }, B=21'100000000000001110011, Y=$auto$wreduce.cc:461:run$6727 [20:0] New ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 2'01 }, B=7'0000010, Y={ $auto$wreduce.cc:461:run$6727 [19:15] $auto$wreduce.cc:461:run$6727 [4] $auto$wreduce.cc:461:run$6727 [2] } New connections: { $auto$wreduce.cc:461:run$6727 [20] $auto$wreduce.cc:461:run$6727 [14:5] $auto$wreduce.cc:461:run$6727 [3] $auto$wreduce.cc:461:run$6727 [1:0] } = { $auto$wreduce.cc:461:run$6727 [4] 7'0000000 $auto$wreduce.cc:461:run$6727 [2] 5'11011 } Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3271: Old ports: A={ 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 15'000000001100111 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 8'00000000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110011 }, Y=$auto$wreduce.cc:461:run$6729 [24:0] New ports: A={ 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0000001 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 2'10 }, Y={ $auto$wreduce.cc:461:run$6729 [24:15] $auto$wreduce.cc:461:run$6729 [11:7] $auto$wreduce.cc:461:run$6729 [4] $auto$wreduce.cc:461:run$6729 [2] } New connections: { $auto$wreduce.cc:461:run$6729 [14:12] $auto$wreduce.cc:461:run$6729 [6:5] $auto$wreduce.cc:461:run$6729 [3] $auto$wreduce.cc:461:run$6729 [1:0] } = { 3'000 $auto$wreduce.cc:461:run$6729 [2] 4'1011 } Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3356: Old ports: A={ 9'010000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'00001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0110011 }, B={ 9'000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'10001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 16'0110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 16'0110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0110011 \Processor.N1.First_Stage.IR_Decompression.instr_c_i }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] New ports: A={ 9'010000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'000010110011 }, B={ 9'000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 21'100010110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 21'110010110011000000001 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'111010110011 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [31:10] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:0] }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [6:0] } New connections: $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [9:7] = \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3435: Old ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110111 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:3] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [5] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6] 24'000000010000000100010011 }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [28:0] New ports: A={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 1'1 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [4:3] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [5] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6] 12'010000000100 }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [28:24] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17:7] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [2] } New connections: { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [23:18] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [6:3] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [1:0] } = { $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [17] 1'0 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$4\instr_d_o[31:0] [2] 4'1011 } Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Fourth_Stage.$procmux$3021: Old ports: A=\Processor.N1.Fourth_Stage.read_data_i, B={ \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7:0] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15:0] 24'000000000000000000000000 \Processor.N1.Fourth_Stage.read_data_i [7:0] 16'0000000000000000 \Processor.N1.Fourth_Stage.read_data_i [15:0] }, Y=\Processor.N1.Fourth_Stage.read_data_normalized New ports: A=\Processor.N1.Fourth_Stage.read_data_i [31:8], B={ \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [7] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15] \Processor.N1.Fourth_Stage.read_data_i [15:8] 40'0000000000000000000000000000000000000000 \Processor.N1.Fourth_Stage.read_data_i [15:8] }, Y=\Processor.N1.Fourth_Stage.read_data_normalized [31:8] New connections: \Processor.N1.Fourth_Stage.read_data_normalized [7:0] = \Processor.N1.Fourth_Stage.read_data_i [7:0] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/IDEX.sv:144$479: Old ports: A=3'100, B=3'010, Y=$auto$wreduce.cc:461:run$6730 [2:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6730 [2:1] New connections: $auto$wreduce.cc:461:run$6730 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$548: Old ports: A=4'1010, B=4'0010, Y=$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$548_Y New ports: A=1'1, B=1'0, Y=$flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$548_Y [3] New connections: $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:42$548_Y [2:0] = 3'010 Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Second_Stage.\ALU_Control.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu_control.sv:47$549: Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:461:run$6731 [1:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6731 [1] New connections: $auto$wreduce.cc:461:run$6731 [0] = 1'1 Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$procmux$2962: Old ports: A={ \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31:20] }, B={ \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24:20] 20'00000000000000000000 \Processor.N1.First_Stage.IFID_IR_o [31:20] 27'000000000000000000000000000 \Processor.N1.First_Stage.IFID_IR_o [24:20] }, Y=$flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] New ports: A={ \Processor.N1.First_Stage.IFID_IR_o [31] \Processor.N1.First_Stage.IFID_IR_o [31:25] }, B={ \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] \Processor.N1.First_Stage.IFID_IR_o [24] 1'0 \Processor.N1.First_Stage.IFID_IR_o [31:25] 8'00000000 }, Y=$flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12:5] New connections: { $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [31:13] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [4:0] } = { $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] $flatten\Processor.\N1.\Second_Stage.\Immediate_Generator.$2\imm_o[31:0] [12] \Processor.N1.First_Stage.IFID_IR_o [24:20] } Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4690: Old ports: A={ \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] 8'x }, B={ \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] \Processor.N1.Third_Stage.Merged_Word_o [15] 80'xxxxxxxxxxxxxxxx000000000000000000000000xxxxxxxx0000000000000000xxxxxxxxxxxxxxxx }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y New ports: A={ \Processor.N1.Third_Stage.Merged_Word_o [7] \Processor.N1.Third_Stage.Merged_Word_o [7] }, B={ \Processor.N1.Third_Stage.Merged_Word_o [15] 5'x000x }, Y={ $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] } New connections: { $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [31:17] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [15:9] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [7:0] } = { $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [16] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] $flatten\Processor.\N1.\Third_Stage.$procmux$4690_Y [8] 8'x } Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4914: Old ports: A={ \Processor.N1.Third_Stage.First_Word [31:16] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [7:0] }, B={ \Processor.N1.Third_Stage.First_Word [31:24] \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [7:0] \Processor.N1.Third_Stage.First_Word [31:24] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [15:0] \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [15:0] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:0] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4914_Y New ports: A={ \Processor.N1.Third_Stage.First_Word [31:16] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] }, B={ \Processor.N1.Third_Stage.First_Word [31:24] \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [31:24] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [15:8] \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [15:8] \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:8] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4914_Y [31:8] New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4914_Y [7:0] = \Processor.N1.Third_Stage.First_Word [7:0] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4932: Old ports: A={ \Processor.N1.Third_Stage.Second_Word [31:24] \Processor.N1.Third_Stage.First_Word [31:8] }, B={ \Processor.N1.Third_Stage.Second_Word [31:8] \Processor.N1.Third_Stage.First_Word [31:24] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4932_Y New ports: A=\Processor.N1.Third_Stage.First_Word [31:8], B={ \Processor.N1.Third_Stage.Second_Word [23:8] \Processor.N1.Third_Stage.First_Word [31:24] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4932_Y [23:0] New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4932_Y [31:24] = \Processor.N1.Third_Stage.Second_Word [31:24] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4938: Old ports: A={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:0] }, B={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0] \Processor.N1.Third_Stage.First_Word [15:0] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4938_Y New ports: A={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [7:0] \Processor.N1.Third_Stage.First_Word [23:16] }, B=\Processor.N1.Third_Stage.EXMEM_mem_data_value [15:0], Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4938_Y [31:16] New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4938_Y [15:0] = \Processor.N1.Third_Stage.First_Word [15:0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2902: { $flatten\ResetBootSystem.$procmux$2895_CMP $flatten\ResetBootSystem.$procmux$2894_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2905: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2905_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2905_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2905_Y [0] = 1'0 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2816: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2822_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2816_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2822_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2816_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2816_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3241: Old ports: A={ 4'0000 $auto$wreduce.cc:461:run$6727 [20:0] }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 3'000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 7'0110011 }, Y=$auto$wreduce.cc:461:run$6726 [24:0] New ports: A={ 4'0000 $auto$wreduce.cc:461:run$6727 [4] $auto$wreduce.cc:461:run$6727 [19:15] 4'0000 $auto$wreduce.cc:461:run$6727 [2] 1'1 $auto$wreduce.cc:461:run$6727 [4] $auto$wreduce.cc:461:run$6727 [2] }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [11:7] 3'010 }, Y={ $auto$wreduce.cc:461:run$6726 [24:15] $auto$wreduce.cc:461:run$6726 [11:6] $auto$wreduce.cc:461:run$6726 [4] $auto$wreduce.cc:461:run$6726 [2] } New connections: { $auto$wreduce.cc:461:run$6726 [14:12] $auto$wreduce.cc:461:run$6726 [5] $auto$wreduce.cc:461:run$6726 [3] $auto$wreduce.cc:461:run$6726 [1:0] } = 7'0001011 Consolidated identical input bits for $pmux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3411: Old ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [10] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'10101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0010011 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 5'11101 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 7'0010011 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] }, Y=$flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] New ports: A={ 1'0 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [10] 5'00000 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'101010010011 }, B={ \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [12] \Processor.N1.First_Stage.IR_Decompression.instr_c_i [6:2] 2'01 \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] 12'111010010011 $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$6\instr_d_o[31:0] [6:0] }, Y={ $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [31:10] $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [6:0] } New connections: $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$5\instr_d_o[31:0] [9:7] = \Processor.N1.First_Stage.IR_Decompression.instr_c_i [9:7] Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\Third_Stage.$procmux$4941: Old ports: A=$flatten\Processor.\N1.\Third_Stage.$procmux$4938_Y, B={ \Processor.N1.Third_Stage.EXMEM_mem_data_value [23:0] \Processor.N1.Third_Stage.First_Word [7:0] }, Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4941_Y New ports: A={ $flatten\Processor.\N1.\Third_Stage.$procmux$4938_Y [31:16] \Processor.N1.Third_Stage.First_Word [15:8] }, B=\Processor.N1.Third_Stage.EXMEM_mem_data_value [23:0], Y=$flatten\Processor.\N1.\Third_Stage.$procmux$4941_Y [31:8] New connections: $flatten\Processor.\N1.\Third_Stage.$procmux$4941_Y [7:0] = \Processor.N1.Third_Stage.First_Word [7:0] Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2911: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2905_Y, Y=$flatten\ResetBootSystem.$procmux$2911_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2905_Y [1], Y=$flatten\ResetBootSystem.$procmux$2911_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2911_Y [0] = 1'0 Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Processor.\N1.\First_Stage.\IR_Decompression.$procmux$3306: Old ports: A=$auto$wreduce.cc:461:run$6729 [24:0], B=$auto$wreduce.cc:461:run$6726 [24:0], Y=$auto$wreduce.cc:461:run$6728 [24:0] New ports: A={ $auto$wreduce.cc:461:run$6729 [24:15] $auto$wreduce.cc:461:run$6729 [11:7] $auto$wreduce.cc:461:run$6729 [2] $auto$wreduce.cc:461:run$6729 [4] $auto$wreduce.cc:461:run$6729 [2] }, B={ $auto$wreduce.cc:461:run$6726 [24:15] $auto$wreduce.cc:461:run$6726 [11:6] $auto$wreduce.cc:461:run$6726 [4] $auto$wreduce.cc:461:run$6726 [2] }, Y={ $auto$wreduce.cc:461:run$6728 [24:15] $auto$wreduce.cc:461:run$6728 [11:6] $auto$wreduce.cc:461:run$6728 [4] $auto$wreduce.cc:461:run$6728 [2] } New connections: { $auto$wreduce.cc:461:run$6728 [14:12] $auto$wreduce.cc:461:run$6728 [5] $auto$wreduce.cc:461:run$6728 [3] $auto$wreduce.cc:461:run$6728 [1:0] } = 7'0001011 Optimizing cells in module \processorci_top. Performed a total of 42 changes. 34.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 34.30.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $\Processor.N1.RegisterBank.registers$rdreg[0] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$7011, Q = $\Processor.N1.RegisterBank.registers$rdreg[0]$q, rval = 5'00000). Adding SRST signal on $\Processor.N1.RegisterBank.registers$rdreg[1] ($dff) from module processorci_top (D = $auto$rtlil.cc:2859:Mux$7016, Q = $\Processor.N1.RegisterBank.registers$rdreg[1]$q, rval = 5'00000). Setting constant 0-bit at position 0 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 1 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 2 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 3 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 4 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 6 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 7 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 8 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 9 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 10 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 11 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 12 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 13 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 14 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 15 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 16 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 17 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 18 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 19 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 20 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 21 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 22 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 23 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 24 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 25 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 26 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 27 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 28 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 29 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 30 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. Setting constant 0-bit at position 31 on $memory\Processor.N1.RegisterBank.registers[0]$9541 ($dff) from module processorci_top. 34.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 4 unused cells and 185 unused wires. <suppressed ~5 debug messages> 34.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 34.30.9. Rerunning OPT passes. (Maybe there is more to do..) 34.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~166 debug messages> 34.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.30.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[9]$9559 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[9]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[8]$9557 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[8]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[7]$9555 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[7]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[6]$9553 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[6]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[5]$9551 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[5]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[4]$9549 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[4]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[3]$9547 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[3]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[31]$9603 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[31]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[30]$9601 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[30]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[2]$9545 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[2]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[29]$9599 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[29]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[28]$9597 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[28]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[27]$9595 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[27]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[26]$9593 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[26]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[25]$9591 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[25]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[24]$9589 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[24]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[23]$9587 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[23]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[22]$9585 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[22]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[21]$9583 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[21]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[20]$9581 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[20]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[1]$9543 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[1]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[19]$9579 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[19]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[18]$9577 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[18]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[17]$9575 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[17]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[16]$9573 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[16]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[15]$9571 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[15]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[14]$9569 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[14]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[13]$9567 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[13]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[12]$9565 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[12]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[11]$9563 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[11]). Adding EN signal on $memory\Processor.N1.RegisterBank.registers[10]$9561 ($dff) from module processorci_top (D = \Processor.N1.RegisterBank.data_i, Q = \Processor.N1.RegisterBank.registers[10]). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6421 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6465 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6493 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6595 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6595 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6595 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6622 ($dffe) from module processorci_top. 34.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 31 unused cells and 31 unused wires. <suppressed ~32 debug messages> 34.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 34.30.16. Rerunning OPT passes. (Maybe there is more to do..) 34.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~135 debug messages> 34.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1974: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1974_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1974_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1974_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1952: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$6701 [0] 6'000000 $auto$wreduce.cc:461:run$6694 [1:0] 1'0 $auto$wreduce.cc:461:run$6699 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$6698 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$6697 [6] 1'0 $auto$wreduce.cc:461:run$6697 [6] 3'011 $auto$wreduce.cc:461:run$6697 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$6693 [3] 2'00 $auto$wreduce.cc:461:run$6693 [3] 6'000010 $auto$wreduce.cc:461:run$6694 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$6693 [3] $auto$wreduce.cc:461:run$6693 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1974_Y 1'0 $auto$wreduce.cc:461:run$6692 [6] 3'010 $auto$wreduce.cc:461:run$6692 [2] $auto$wreduce.cc:461:run$6692 [6] $auto$wreduce.cc:461:run$6692 [2] 13'0001001100010 $auto$wreduce.cc:461:run$6691 [2:1] $auto$wreduce.cc:461:run$6691 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$6690 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1952_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$6701 [0] 5'00000 $auto$wreduce.cc:461:run$6694 [1:0] $auto$wreduce.cc:461:run$6699 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$6698 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$6697 [6] 1'0 $auto$wreduce.cc:461:run$6697 [6] 3'011 $auto$wreduce.cc:461:run$6697 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$6693 [3] 2'00 $auto$wreduce.cc:461:run$6693 [3] 5'00010 $auto$wreduce.cc:461:run$6694 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$6693 [3] $auto$wreduce.cc:461:run$6693 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1974_Y [4:0] $auto$wreduce.cc:461:run$6692 [6] 3'010 $auto$wreduce.cc:461:run$6692 [2] $auto$wreduce.cc:461:run$6692 [6] $auto$wreduce.cc:461:run$6692 [2] 11'00100110010 $auto$wreduce.cc:461:run$6691 [2:1] $auto$wreduce.cc:461:run$6691 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$6690 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1952_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1952_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 34.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.30.20. Executing OPT_DFF pass (perform DFF optimizations). 34.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.30.23. Rerunning OPT passes. (Maybe there is more to do..) 34.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~135 debug messages> 34.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6659 ($sdff) from module processorci_top. 34.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 34.30.30. Rerunning OPT passes. (Maybe there is more to do..) 34.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~135 debug messages> 34.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.30.34. Executing OPT_DFF pass (perform DFF optimizations). 34.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.30.37. Finished OPT passes. (There is nothing left to do.) 34.31. Executing TECHMAP pass (map to technology primitives). 34.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 34.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 34.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $eq. Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $lut. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$e9679b690548ba55b1f1b57f80da909b90290ccf\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $bmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:de64642e95807af510ec2f372d99917387e547b5$paramod$2cd5a0fc12c713b111b124c014c3805512a5d620\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:51fb3526f3621c6ba109a6fa670766d42e57f474$paramod$3a55d5cb0043d442f8310a0b82c3ba1d6d3f1032\_90_shift_shiftx for cells of type $shift. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:02e205211af79b2de8410595a9b352a9c0a22e28$paramod$8a857a6eaa058823edfcd7a5ef47a9d072c90c39\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:7d50daff0345024d4d0c5d6b0021827b46f8ee12$paramod$46fb6c6807392d1f812af275dc46f0337caa65d5\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$40ec39fdbb40e313957832362e47914160e3dfcb\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:d44722790a942a23012b84b456a3acf7a7153600$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx for cells of type $shift. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Analyzing pattern of constant bits for this cell: Creating constmapped module `$paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx'. 34.31.96. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $procmux$22598. dead port 2/2 on $mux $procmux$22592. dead port 2/2 on $mux $procmux$22586. dead port 2/2 on $mux $procmux$22580. dead port 2/2 on $mux $procmux$22574. dead port 2/2 on $mux $procmux$22568. dead port 2/2 on $mux $procmux$22562. dead port 2/2 on $mux $procmux$22556. dead port 2/2 on $mux $procmux$22550. dead port 2/2 on $mux $procmux$22544. dead port 2/2 on $mux $procmux$22538. Removed 11 multiplexer ports. <suppressed ~2517 debug messages> 34.31.97. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx. <suppressed ~23 debug messages> Removed 0 unused cells and 16 unused wires. Using template $paramod$constmap:a2ff8f2efa668e673a64c3e66dab1c1d55454434$paramod$3c14200e3307b7bce81105727af302e48093c600\_90_shift_shiftx for cells of type $shift. Using template $paramod$ba698a254f9a5947e85cbe7beae6b161eefc5386\_90_alu for cells of type $alu. Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$a75cda08a00cd2ec286ea508f3ad43ec36b77618\_90_pmux for cells of type $pmux. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$3aec434ea322cab681ad20f744a80c5503010ba7\_90_pmux for cells of type $pmux. Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux. Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux. Using template $paramod$788c3d57e5abb3a3f89aea6d4acd665be37f4e9b\_80_ecp5_alu for cells of type $alu. Using template $paramod$b6b58933bcf3c8b9e3e5de18c2637bd0e12c7c47\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~7453 debug messages> 34.32. Executing OPT pass (performing simple optimizations). 34.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~221021 debug messages> 34.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6975 debug messages> Removed a total of 2325 cells. 34.32.3. Executing OPT_DFF pass (perform DFF optimizations). 34.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 32859 unused cells and 9294 unused wires. <suppressed ~32865 debug messages> 34.32.5. Finished fast OPT passes. 34.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 34.35. Executing TECHMAP pass (map to technology primitives). 34.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 34.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. No more expansions possible. <suppressed ~4410 debug messages> 34.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~78 debug messages> 34.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 34.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 34.39. Executing ATTRMVCP pass (move or copy attributes). 34.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 23347 unused wires. <suppressed ~1 debug messages> 34.41. Executing TECHMAP pass (map to technology primitives). 34.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 34.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 34.42. Executing ABC9 pass. 34.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.3. Executing PROC pass (convert processes to netlists). 34.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330296'. Cleaned up 1 empty switch. 34.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 34.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 34.42.3.4. Executing PROC_INIT pass (extract init attributes). 34.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 34.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 34.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_EN[3:0]$330303 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_DATA[3:0]$330302 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_ADDR[3:0]$330301 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330296'. 34.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 34.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330289_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330283_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330279_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330280_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330284_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330285_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330286_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330290_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330291_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330281_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330292_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330282_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330287_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330288_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330293_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$330294_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297'. created $dff cell `$procdff$330347' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297'. created $dff cell `$procdff$330348' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$330295_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297'. created $dff cell `$procdff$330349' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330296'. created direct connection (no actual register cell created). 34.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 34.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$330321'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$330297'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$330296'. Cleaned up 1 empty switch. 34.42.3.12. Executing OPT_EXPR pass (perform const folding). 34.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$21316 $auto$simplemap.cc:225:simplemap_logbin$22034 $auto$simplemap.cc:225:simplemap_logbin$22036 $auto$ff.cc:266:slice$22211 $auto$simplemap.cc:126:simplemap_reduce$21318 $auto$simplemap.cc:225:simplemap_logbin$22040 $auto$simplemap.cc:225:simplemap_logbin$22038 $auto$simplemap.cc:225:simplemap_logbin$22037 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$324857 $auto$ff.cc:266:slice$42021 $auto$ff.cc:266:slice$42020 $auto$ff.cc:266:slice$42019 $auto$ff.cc:266:slice$42018 $auto$ff.cc:266:slice$42017 $auto$simplemap.cc:267:simplemap_mux$22227 $auto$simplemap.cc:267:simplemap_mux$22255 $auto$simplemap.cc:267:simplemap_mux$22257 $auto$simplemap.cc:267:simplemap_mux$22256 $auto$simplemap.cc:267:simplemap_mux$22254 $auto$simplemap.cc:267:simplemap_mux$22253 $auto$simplemap.cc:267:simplemap_mux$22252 $auto$simplemap.cc:267:simplemap_mux$22251 $auto$simplemap.cc:267:simplemap_mux$22250 $auto$simplemap.cc:267:simplemap_mux$22249 $auto$simplemap.cc:267:simplemap_mux$22248 $auto$simplemap.cc:267:simplemap_mux$22247 $auto$simplemap.cc:267:simplemap_mux$22246 $auto$simplemap.cc:267:simplemap_mux$22245 $auto$simplemap.cc:267:simplemap_mux$22244 $auto$simplemap.cc:267:simplemap_mux$22243 $auto$simplemap.cc:267:simplemap_mux$22242 $auto$simplemap.cc:267:simplemap_mux$22241 $auto$simplemap.cc:267:simplemap_mux$22240 $auto$simplemap.cc:267:simplemap_mux$22239 $auto$simplemap.cc:267:simplemap_mux$22238 $auto$simplemap.cc:267:simplemap_mux$22237 $auto$simplemap.cc:267:simplemap_mux$22236 $auto$simplemap.cc:267:simplemap_mux$22235 $auto$simplemap.cc:267:simplemap_mux$22234 $auto$simplemap.cc:267:simplemap_mux$22233 $auto$simplemap.cc:267:simplemap_mux$22232 $auto$simplemap.cc:267:simplemap_mux$22231 $auto$simplemap.cc:267:simplemap_mux$22230 $auto$simplemap.cc:267:simplemap_mux$22229 $auto$simplemap.cc:267:simplemap_mux$22228 $auto$simplemap.cc:38:simplemap_not$191032 $auto$simplemap.cc:75:simplemap_bitop$316358 $auto$simplemap.cc:75:simplemap_bitop$38894 $auto$simplemap.cc:75:simplemap_bitop$39980 $auto$simplemap.cc:75:simplemap_bitop$40006 $auto$ff.cc:266:slice$42079 $auto$simplemap.cc:75:simplemap_bitop$39979 $auto$simplemap.cc:75:simplemap_bitop$40005 $auto$ff.cc:266:slice$42078 $auto$simplemap.cc:126:simplemap_reduce$39985 $auto$simplemap.cc:75:simplemap_bitop$39978 $auto$simplemap.cc:126:simplemap_reduce$40011 $auto$simplemap.cc:75:simplemap_bitop$40004 $auto$simplemap.cc:126:simplemap_reduce$45465 $auto$ff.cc:266:slice$42077 $auto$simplemap.cc:75:simplemap_bitop$39977 $auto$simplemap.cc:75:simplemap_bitop$40003 $auto$ff.cc:266:slice$42076 $auto$simplemap.cc:196:simplemap_lognot$39991 $auto$simplemap.cc:126:simplemap_reduce$39989 $auto$simplemap.cc:126:simplemap_reduce$39987 $auto$simplemap.cc:126:simplemap_reduce$39984 $auto$simplemap.cc:75:simplemap_bitop$39976 $auto$simplemap.cc:196:simplemap_lognot$40017 $auto$simplemap.cc:126:simplemap_reduce$40015 $auto$simplemap.cc:126:simplemap_reduce$40013 $auto$simplemap.cc:126:simplemap_reduce$40010 $auto$simplemap.cc:75:simplemap_bitop$40002 $auto$opt_expr.cc:617:replace_const_cells$324797 $auto$simplemap.cc:225:simplemap_logbin$39999 $auto$simplemap.cc:225:simplemap_logbin$40018 $auto$simplemap.cc:126:simplemap_reduce$39998 $auto$simplemap.cc:126:simplemap_reduce$45471 $auto$simplemap.cc:126:simplemap_reduce$45464 $auto$ff.cc:266:slice$42075 $auto$simplemap.cc:75:simplemap_bitop$39961 $auto$simplemap.cc:75:simplemap_bitop$42681 $auto$ff.cc:266:slice$42074 $auto$simplemap.cc:75:simplemap_bitop$39960 $auto$simplemap.cc:75:simplemap_bitop$42680 $auto$ff.cc:266:slice$42073 $auto$simplemap.cc:126:simplemap_reduce$39949 $auto$simplemap.cc:126:simplemap_reduce$39966 $auto$simplemap.cc:75:simplemap_bitop$39959 $auto$simplemap.cc:126:simplemap_reduce$42686 $auto$simplemap.cc:75:simplemap_bitop$42679 $auto$ff.cc:266:slice$42072 $auto$simplemap.cc:75:simplemap_bitop$39958 $auto$simplemap.cc:75:simplemap_bitop$42678 $auto$ff.cc:266:slice$42071 $auto$simplemap.cc:126:simplemap_reduce$39953 $auto$simplemap.cc:126:simplemap_reduce$39951 $auto$simplemap.cc:126:simplemap_reduce$39948 $auto$simplemap.cc:225:simplemap_logbin$39973 $auto$simplemap.cc:196:simplemap_lognot$39972 $auto$simplemap.cc:126:simplemap_reduce$39970 $auto$simplemap.cc:126:simplemap_reduce$39968 $auto$simplemap.cc:126:simplemap_reduce$39965 $auto$simplemap.cc:75:simplemap_bitop$39957 $auto$opt_expr.cc:617:replace_const_cells$324743 $auto$simplemap.cc:225:simplemap_logbin$39954 $auto$simplemap.cc:196:simplemap_lognot$42692 $auto$simplemap.cc:126:simplemap_reduce$42690 $auto$simplemap.cc:126:simplemap_reduce$42688 $auto$simplemap.cc:126:simplemap_reduce$42685 $auto$simplemap.cc:75:simplemap_bitop$42677 $auto$ff.cc:266:slice$42070 $auto$opt_expr.cc:617:replace_const_cells$324783 $auto$ff.cc:266:slice$42061 $auto$opt_expr.cc:617:replace_const_cells$324785 $auto$ff.cc:266:slice$42060 $auto$simplemap.cc:126:simplemap_reduce$42391 $auto$simplemap.cc:126:simplemap_reduce$42388 $auto$simplemap.cc:126:simplemap_reduce$42413 $auto$simplemap.cc:126:simplemap_reduce$42410 $auto$opt_expr.cc:617:replace_const_cells$324775 $auto$simplemap.cc:126:simplemap_reduce$42523 $auto$simplemap.cc:126:simplemap_reduce$42520 $auto$simplemap.cc:126:simplemap_reduce$42369 $auto$simplemap.cc:126:simplemap_reduce$42649 $auto$simplemap.cc:126:simplemap_reduce$42646 $auto$ff.cc:266:slice$42059 $auto$opt_expr.cc:617:replace_const_cells$324763 $auto$ff.cc:266:slice$42058 $auto$simplemap.cc:126:simplemap_reduce$42519 $auto$simplemap.cc:126:simplemap_reduce$42314 $auto$simplemap.cc:126:simplemap_reduce$42645 $auto$opt_expr.cc:617:replace_const_cells$324781 $auto$ff.cc:266:slice$42057 $auto$opt_expr.cc:617:replace_const_cells$324779 $auto$ff.cc:266:slice$42056 $auto$ff.cc:266:slice$42054 $auto$ff.cc:266:slice$42053 $auto$ff.cc:266:slice$42052 $auto$ff.cc:266:slice$42051 $auto$ff.cc:266:slice$42050 $auto$ff.cc:266:slice$42049 $auto$ff.cc:266:slice$42048 $auto$ff.cc:266:slice$42047 $auto$ff.cc:266:slice$42046 $auto$ff.cc:266:slice$42045 $auto$ff.cc:266:slice$42044 $auto$ff.cc:266:slice$42043 $auto$ff.cc:266:slice$42042 $auto$ff.cc:266:slice$42041 $auto$ff.cc:266:slice$42040 $auto$ff.cc:266:slice$42039 $auto$ff.cc:266:slice$42038 $auto$ff.cc:266:slice$42037 $auto$ff.cc:266:slice$42036 $auto$ff.cc:266:slice$42035 $auto$ff.cc:266:slice$42034 $auto$ff.cc:266:slice$42033 $auto$ff.cc:266:slice$42032 $auto$ff.cc:266:slice$42031 $auto$ff.cc:266:slice$42030 $auto$ff.cc:266:slice$42029 $auto$ff.cc:266:slice$42028 $auto$ff.cc:266:slice$42027 $auto$ff.cc:266:slice$42026 $auto$ff.cc:266:slice$42025 $auto$ff.cc:266:slice$42024 $auto$simplemap.cc:196:simplemap_lognot$42322 $auto$simplemap.cc:126:simplemap_reduce$42320 $auto$simplemap.cc:126:simplemap_reduce$42317 $auto$simplemap.cc:196:simplemap_lognot$42351 $auto$simplemap.cc:126:simplemap_reduce$42349 $auto$simplemap.cc:126:simplemap_reduce$42325 $auto$simplemap.cc:196:simplemap_lognot$42373 $auto$simplemap.cc:126:simplemap_reduce$42371 $auto$simplemap.cc:196:simplemap_lognot$42527 $auto$simplemap.cc:126:simplemap_reduce$42525 $auto$simplemap.cc:126:simplemap_reduce$42522 $auto$simplemap.cc:196:simplemap_lognot$42395 $auto$simplemap.cc:126:simplemap_reduce$42393 $auto$simplemap.cc:126:simplemap_reduce$42296 $auto$simplemap.cc:75:simplemap_bitop$190806 $auto$simplemap.cc:75:simplemap_bitop$190807 $auto$simplemap.cc:75:simplemap_bitop$190808 $auto$simplemap.cc:75:simplemap_bitop$190809 $auto$simplemap.cc:75:simplemap_bitop$190810 $auto$simplemap.cc:75:simplemap_bitop$190811 $auto$simplemap.cc:75:simplemap_bitop$190812 $auto$simplemap.cc:75:simplemap_bitop$190813 $auto$simplemap.cc:75:simplemap_bitop$190814 $auto$simplemap.cc:75:simplemap_bitop$190815 $auto$simplemap.cc:75:simplemap_bitop$190816 $auto$simplemap.cc:75:simplemap_bitop$190817 $auto$simplemap.cc:75:simplemap_bitop$190818 $auto$simplemap.cc:75:simplemap_bitop$190819 $auto$simplemap.cc:75:simplemap_bitop$190820 $auto$simplemap.cc:75:simplemap_bitop$190821 $auto$simplemap.cc:75:simplemap_bitop$190822 $auto$simplemap.cc:75:simplemap_bitop$190823 $auto$simplemap.cc:75:simplemap_bitop$190824 $auto$simplemap.cc:75:simplemap_bitop$190825 $auto$simplemap.cc:75:simplemap_bitop$190826 $auto$simplemap.cc:75:simplemap_bitop$190827 $auto$simplemap.cc:75:simplemap_bitop$190828 $auto$simplemap.cc:75:simplemap_bitop$190829 $auto$simplemap.cc:75:simplemap_bitop$190830 $auto$simplemap.cc:75:simplemap_bitop$190831 $auto$simplemap.cc:75:simplemap_bitop$190832 $auto$simplemap.cc:75:simplemap_bitop$190833 $auto$simplemap.cc:75:simplemap_bitop$190834 $auto$simplemap.cc:75:simplemap_bitop$190835 $auto$simplemap.cc:75:simplemap_bitop$190836 $auto$simplemap.cc:75:simplemap_bitop$190837 $auto$simplemap.cc:126:simplemap_reduce$42329 $auto$simplemap.cc:126:simplemap_reduce$42327 $auto$simplemap.cc:126:simplemap_reduce$42324 $auto$simplemap.cc:196:simplemap_lognot$42417 $auto$simplemap.cc:126:simplemap_reduce$42415 $auto$simplemap.cc:75:simplemap_bitop$190417 $auto$simplemap.cc:75:simplemap_bitop$190418 $auto$simplemap.cc:75:simplemap_bitop$190419 $auto$simplemap.cc:75:simplemap_bitop$190420 $auto$simplemap.cc:75:simplemap_bitop$190421 $auto$simplemap.cc:75:simplemap_bitop$190422 $auto$simplemap.cc:75:simplemap_bitop$190423 $auto$simplemap.cc:75:simplemap_bitop$190424 $auto$simplemap.cc:75:simplemap_bitop$190425 $auto$simplemap.cc:75:simplemap_bitop$190426 $auto$simplemap.cc:75:simplemap_bitop$190427 $auto$simplemap.cc:75:simplemap_bitop$190428 $auto$simplemap.cc:75:simplemap_bitop$190429 $auto$simplemap.cc:75:simplemap_bitop$190430 $auto$simplemap.cc:75:simplemap_bitop$190431 $auto$simplemap.cc:75:simplemap_bitop$190432 $auto$simplemap.cc:75:simplemap_bitop$190433 $auto$simplemap.cc:75:simplemap_bitop$190434 $auto$simplemap.cc:75:simplemap_bitop$190435 $auto$simplemap.cc:75:simplemap_bitop$190436 $auto$simplemap.cc:75:simplemap_bitop$190437 $auto$simplemap.cc:75:simplemap_bitop$190438 $auto$simplemap.cc:75:simplemap_bitop$190439 $auto$simplemap.cc:75:simplemap_bitop$190440 $auto$simplemap.cc:75:simplemap_bitop$190441 $auto$simplemap.cc:75:simplemap_bitop$190442 $auto$simplemap.cc:75:simplemap_bitop$190443 $auto$simplemap.cc:75:simplemap_bitop$190444 $auto$simplemap.cc:75:simplemap_bitop$190445 $auto$simplemap.cc:75:simplemap_bitop$190446 $auto$simplemap.cc:75:simplemap_bitop$190447 $auto$simplemap.cc:126:simplemap_reduce$190513 $auto$simplemap.cc:126:simplemap_reduce$42298 $auto$simplemap.cc:126:simplemap_reduce$190873 $auto$simplemap.cc:75:simplemap_bitop$190839 $auto$simplemap.cc:126:simplemap_reduce$190875 $auto$simplemap.cc:75:simplemap_bitop$190840 $auto$simplemap.cc:126:simplemap_reduce$190935 $auto$simplemap.cc:126:simplemap_reduce$42300 $auto$simplemap.cc:196:simplemap_lognot$42653 $auto$simplemap.cc:126:simplemap_reduce$42651 $auto$simplemap.cc:126:simplemap_reduce$42648 $auto$simplemap.cc:126:simplemap_reduce$42644 $auto$opt_expr.cc:617:replace_const_cells$324777 $auto$ff.cc:266:slice$42055 $auto$simplemap.cc:75:simplemap_bitop$190416 $auto$ff.cc:266:slice$42023 $auto$simplemap.cc:225:simplemap_logbin$42732 $auto$ff.cc:266:slice$42022 $auto$simplemap.cc:75:simplemap_bitop$190578 $auto$simplemap.cc:75:simplemap_bitop$190579 $auto$simplemap.cc:75:simplemap_bitop$190580 $auto$simplemap.cc:75:simplemap_bitop$190581 $auto$simplemap.cc:75:simplemap_bitop$190582 $auto$simplemap.cc:75:simplemap_bitop$190583 $auto$simplemap.cc:75:simplemap_bitop$190584 $auto$simplemap.cc:75:simplemap_bitop$190585 $auto$simplemap.cc:75:simplemap_bitop$190586 $auto$simplemap.cc:75:simplemap_bitop$190587 $auto$simplemap.cc:75:simplemap_bitop$190588 $auto$simplemap.cc:75:simplemap_bitop$190589 $auto$simplemap.cc:75:simplemap_bitop$190590 $auto$simplemap.cc:75:simplemap_bitop$190591 $auto$simplemap.cc:75:simplemap_bitop$190592 $auto$simplemap.cc:75:simplemap_bitop$190593 $auto$simplemap.cc:75:simplemap_bitop$190594 $auto$simplemap.cc:75:simplemap_bitop$190595 $auto$simplemap.cc:75:simplemap_bitop$190596 $auto$simplemap.cc:75:simplemap_bitop$190597 $auto$simplemap.cc:75:simplemap_bitop$190598 $auto$simplemap.cc:75:simplemap_bitop$190599 $auto$simplemap.cc:75:simplemap_bitop$190600 $auto$simplemap.cc:75:simplemap_bitop$190601 $auto$simplemap.cc:75:simplemap_bitop$190602 $auto$simplemap.cc:75:simplemap_bitop$190603 $auto$simplemap.cc:75:simplemap_bitop$190604 $auto$simplemap.cc:75:simplemap_bitop$190605 $auto$simplemap.cc:75:simplemap_bitop$190606 $auto$simplemap.cc:75:simplemap_bitop$190607 $auto$simplemap.cc:75:simplemap_bitop$190608 $auto$simplemap.cc:75:simplemap_bitop$190609 $auto$simplemap.cc:196:simplemap_lognot$39916 $auto$simplemap.cc:126:simplemap_reduce$39914 $auto$simplemap.cc:126:simplemap_reduce$190649 $auto$simplemap.cc:75:simplemap_bitop$190611 $auto$simplemap.cc:126:simplemap_reduce$190653 $auto$simplemap.cc:75:simplemap_bitop$190612 $auto$simplemap.cc:126:simplemap_reduce$190657 $auto$simplemap.cc:75:simplemap_bitop$190613 $auto$simplemap.cc:126:simplemap_reduce$190661 $auto$simplemap.cc:75:simplemap_bitop$190614 $auto$simplemap.cc:126:simplemap_reduce$190665 $auto$simplemap.cc:75:simplemap_bitop$190615 $auto$simplemap.cc:126:simplemap_reduce$190669 $auto$simplemap.cc:75:simplemap_bitop$190616 $auto$simplemap.cc:126:simplemap_reduce$190673 $auto$simplemap.cc:75:simplemap_bitop$190617 $auto$simplemap.cc:126:simplemap_reduce$190677 $auto$simplemap.cc:75:simplemap_bitop$190618 $auto$simplemap.cc:126:simplemap_reduce$190681 $auto$simplemap.cc:75:simplemap_bitop$190619 $auto$simplemap.cc:126:simplemap_reduce$190685 $auto$simplemap.cc:75:simplemap_bitop$190620 $auto$simplemap.cc:126:simplemap_reduce$190689 $auto$simplemap.cc:75:simplemap_bitop$190621 $auto$simplemap.cc:126:simplemap_reduce$190693 $auto$simplemap.cc:75:simplemap_bitop$190622 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$auto$simplemap.cc:75:simplemap_bitop$316359 $auto$simplemap.cc:126:simplemap_reduce$315536 $auto$simplemap.cc:126:simplemap_reduce$315529 $auto$simplemap.cc:75:simplemap_bitop$316391 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41189 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41285 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41381 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41477 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$shr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:46$602.$auto$simplemap.cc:267:simplemap_mux$41045 $auto$simplemap.cc:126:simplemap_reduce$315542 $auto$simplemap.cc:126:simplemap_reduce$315540 $auto$simplemap.cc:126:simplemap_reduce$315532 $auto$simplemap.cc:75:simplemap_bitop$316167 $auto$simplemap.cc:75:simplemap_bitop$191127 $auto$simplemap.cc:126:simplemap_reduce$316001 $auto$simplemap.cc:126:simplemap_reduce$315995 $auto$simplemap.cc:75:simplemap_bitop$316264 $auto$simplemap.cc:126:simplemap_reduce$18635 $auto$simplemap.cc:38:simplemap_not$18640 $auto$simplemap.cc:75:simplemap_bitop$21064 $auto$simplemap.cc:126:simplemap_reduce$42725 $auto$simplemap.cc:126:simplemap_reduce$42720 $auto$simplemap.cc:126:simplemap_reduce$42711 $auto$simplemap.cc:126:simplemap_reduce$42694 $auto$simplemap.cc:267:simplemap_mux$316392 $auto$simplemap.cc:126:simplemap_reduce$316007 $auto$simplemap.cc:126:simplemap_reduce$316005 $auto$simplemap.cc:126:simplemap_reduce$316002 $auto$simplemap.cc:126:simplemap_reduce$315996 $auto$simplemap.cc:75:simplemap_bitop$316200 $auto$simplemap.cc:126:simplemap_reduce$21063 $auto$simplemap.cc:126:simplemap_reduce$21061 $auto$simplemap.cc:126:simplemap_reduce$21058 $auto$simplemap.cc:126:simplemap_reduce$21053 $auto$simplemap.cc:126:simplemap_reduce$21044 $auto$simplemap.cc:75:simplemap_bitop$315367 $auto$simplemap.cc:267:simplemap_mux$316423 $auto$simplemap.cc:267:simplemap_mux$190545 $auto$simplemap.cc:267:simplemap_mux$190383 $auto$simplemap.cc:126:simplemap_reduce$190351 $auto$simplemap.cc:126:simplemap_reduce$190349 $auto$simplemap.cc:196:simplemap_lognot$42674 $auto$simplemap.cc:126:simplemap_reduce$42672 $auto$opt_expr.cc:617:replace_const_cells$324741 $auto$simplemap.cc:225:simplemap_logbin$42529 $auto$simplemap.cc:225:simplemap_logbin$42531 $auto$simplemap.cc:196:simplemap_lognot$38593 $auto$ff.cc:266:slice$42837 $auto$ff.cc:479:convert_ce_over_srst$325773 $auto$simplemap.cc:126:simplemap_reduce$13042 $auto$simplemap.cc:126:simplemap_reduce$13040 $auto$simplemap.cc:126:simplemap_reduce$12983 $auto$opt_expr.cc:617:replace_const_cells$324627 $auto$simplemap.cc:75:simplemap_bitop$43653 $auto$simplemap.cc:225:simplemap_logbin$42731 $auto$simplemap.cc:225:simplemap_logbin$42734 $auto$simplemap.cc:126:simplemap_reduce$42739 $auto$simplemap.cc:267:simplemap_mux$40025 $auto$ff.cc:266:slice$42003 $auto$simplemap.cc:225:simplemap_logbin$42528 $auto$simplemap.cc:225:simplemap_logbin$42530 $auto$simplemap.cc:225:simplemap_logbin$42532 $auto$simplemap.cc:225:simplemap_logbin$38893 $auto$simplemap.cc:75:simplemap_bitop$38895 $auto$simplemap.cc:75:simplemap_bitop$38896 $auto$simplemap.cc:196:simplemap_lognot$45772 $auto$simplemap.cc:225:simplemap_logbin$42730 $auto$simplemap.cc:225:simplemap_logbin$40035 $auto$simplemap.cc:38:simplemap_not$40027 $auto$simplemap.cc:126:simplemap_reduce$42728 $auto$simplemap.cc:126:simplemap_reduce$42726 $auto$simplemap.cc:126:simplemap_reduce$42723 $auto$simplemap.cc:126:simplemap_reduce$42718 $auto$simplemap.cc:126:simplemap_reduce$42709 $auto$simplemap.cc:267:simplemap_mux$316422 $auto$simplemap.cc:126:simplemap_reduce$315557 $auto$simplemap.cc:126:simplemap_reduce$315555 $auto$simplemap.cc:126:simplemap_reduce$315551 $auto$simplemap.cc:126:simplemap_reduce$315544 $auto$simplemap.cc:75:simplemap_bitop$316390 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41188 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41284 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41380 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41476 $techmap$flatten\Processor.\N1.\Second_Stage.\Alu.$sshr$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/alu.sv:47$603.$auto$simplemap.cc:267:simplemap_mux$41572 $auto$simplemap.cc:267:simplemap_mux$190936 $auto$simplemap.cc:267:simplemap_mux$190774 $auto$simplemap.cc:126:simplemap_reduce$190645 $auto$simplemap.cc:75:simplemap_bitop$190610 $auto$simplemap.cc:267:simplemap_mux$22226 $auto$ff.cc:266:slice$43779 $auto$simplemap.cc:225:simplemap_logbin$44098 $auto$simplemap.cc:75:simplemap_bitop$43713 $auto$simplemap.cc:75:simplemap_bitop$43714 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$324123 $auto$ff.cc:266:slice$17300 $auto$simplemap.cc:126:simplemap_reduce$17490 $auto$simplemap.cc:126:simplemap_reduce$17475 $auto$ff.cc:266:slice$17301 $auto$ff.cc:266:slice$17302 $auto$simplemap.cc:75:simplemap_bitop$127171 $auto$simplemap.cc:196:simplemap_lognot$17495 $auto$simplemap.cc:126:simplemap_reduce$17493 $auto$simplemap.cc:126:simplemap_reduce$17491 $auto$opt_expr.cc:617:replace_const_cells$324063 $auto$opt_expr.cc:617:replace_const_cells$324065 $auto$simplemap.cc:267:simplemap_mux$127167 $auto$simplemap.cc:126:simplemap_reduce$127181 $auto$simplemap.cc:126:simplemap_reduce$127178 $auto$simplemap.cc:126:simplemap_reduce$127183 $auto$simplemap.cc:75:simplemap_bitop$127169 $auto$simplemap.cc:267:simplemap_mux$17462 $auto$simplemap.cc:225:simplemap_logbin$17465 $auto$simplemap.cc:196:simplemap_lognot$17480 $auto$simplemap.cc:126:simplemap_reduce$17478 $auto$simplemap.cc:126:simplemap_reduce$17476 $auto$ff.cc:266:slice$17303 $auto$simplemap.cc:126:simplemap_reduce$21303 $auto$simplemap.cc:126:simplemap_reduce$21301 $auto$simplemap.cc:225:simplemap_logbin$17421 $auto$simplemap.cc:196:simplemap_lognot$17431 $auto$simplemap.cc:126:simplemap_reduce$17429 $auto$opt_expr.cc:617:replace_const_cells$324061 $auto$simplemap.cc:267:simplemap_mux$127168 $auto$simplemap.cc:126:simplemap_reduce$127186 Found an SCC: $auto$ff.cc:266:slice$22212 $auto$simplemap.cc:126:simplemap_reduce$21320 $auto$simplemap.cc:225:simplemap_logbin$22035 Found an SCC: $auto$ff.cc:266:slice$21962 $auto$simplemap.cc:126:simplemap_reduce$21314 $auto$simplemap.cc:225:simplemap_logbin$21907 Found an SCC: $auto$simplemap.cc:38:simplemap_not$127223 $auto$ff.cc:266:slice$17153 $auto$simplemap.cc:126:simplemap_reduce$17285 $auto$opt_expr.cc:617:replace_const_cells$324151 $auto$simplemap.cc:126:simplemap_reduce$17258 $auto$ff.cc:266:slice$17154 $auto$ff.cc:266:slice$17155 $auto$simplemap.cc:38:simplemap_not$127217 $auto$ff.cc:266:slice$17147 $auto$simplemap.cc:126:simplemap_reduce$17282 $auto$simplemap.cc:126:simplemap_reduce$17255 $auto$ff.cc:266:slice$17148 $auto$ff.cc:266:slice$17149 $auto$simplemap.cc:126:simplemap_reduce$17287 $auto$simplemap.cc:126:simplemap_reduce$17283 $auto$simplemap.cc:38:simplemap_not$127220 $auto$ff.cc:266:slice$17150 $auto$simplemap.cc:38:simplemap_not$127221 $auto$ff.cc:266:slice$17151 $auto$simplemap.cc:196:simplemap_lognot$17294 $auto$simplemap.cc:126:simplemap_reduce$17292 $auto$simplemap.cc:126:simplemap_reduce$17290 $auto$simplemap.cc:126:simplemap_reduce$17288 $auto$simplemap.cc:126:simplemap_reduce$17284 $auto$simplemap.cc:126:simplemap_reduce$17261 $auto$simplemap.cc:126:simplemap_reduce$17257 $auto$simplemap.cc:38:simplemap_not$127222 $auto$ff.cc:266:slice$17152 $auto$simplemap.cc:167:logic_reduce$13010 $auto$simplemap.cc:225:simplemap_logbin$17239 $auto$simplemap.cc:225:simplemap_logbin$17240 $auto$simplemap.cc:196:simplemap_lognot$17267 $auto$simplemap.cc:126:simplemap_reduce$17265 $auto$simplemap.cc:126:simplemap_reduce$17263 $auto$simplemap.cc:126:simplemap_reduce$17260 $auto$simplemap.cc:126:simplemap_reduce$17256 $auto$simplemap.cc:38:simplemap_not$127219 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$20958 $auto$ff.cc:266:slice$18351 $auto$ff.cc:479:convert_ce_over_srst$325579 $auto$simplemap.cc:126:simplemap_reduce$18649 $auto$simplemap.cc:38:simplemap_not$319340 $auto$ff.cc:266:slice$18352 $auto$ff.cc:479:convert_ce_over_srst$325581 $auto$opt_expr.cc:617:replace_const_cells$325387 $auto$ff.cc:266:slice$18347 $auto$ff.cc:479:convert_ce_over_srst$325571 $auto$alumacc.cc:485:replace_alu$6769.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$18647 $auto$simplemap.cc:38:simplemap_not$319336 $auto$ff.cc:266:slice$18348 $auto$ff.cc:479:convert_ce_over_srst$325573 $auto$simplemap.cc:38:simplemap_not$21353 $auto$alumacc.cc:485:replace_alu$6769.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$6769.slice[2].ccu2c_i $auto$ff.cc:266:slice$18349 $auto$ff.cc:479:convert_ce_over_srst$325575 $auto$simplemap.cc:126:simplemap_reduce$21227 $auto$simplemap.cc:126:simplemap_reduce$20961 $auto$simplemap.cc:126:simplemap_reduce$20959 $auto$simplemap.cc:38:simplemap_not$13286 $auto$simplemap.cc:75:simplemap_bitop$18372 $auto$simplemap.cc:126:simplemap_reduce$18653 $auto$simplemap.cc:126:simplemap_reduce$18651 $auto$simplemap.cc:126:simplemap_reduce$18648 $auto$simplemap.cc:38:simplemap_not$319338 $auto$ff.cc:266:slice$18350 $auto$ff.cc:479:convert_ce_over_srst$325577 $auto$simplemap.cc:126:simplemap_reduce$12909 $auto$simplemap.cc:126:simplemap_reduce$12907 Found an SCC: $auto$ff.cc:266:slice$17305 $auto$ff.cc:266:slice$17306 $auto$simplemap.cc:126:simplemap_reduce$17511 $auto$simplemap.cc:38:simplemap_not$65058 $auto$ff.cc:266:slice$17307 $auto$simplemap.cc:38:simplemap_not$65059 $auto$ff.cc:266:slice$17308 $auto$simplemap.cc:126:simplemap_reduce$17512 $auto$ff.cc:266:slice$17309 $auto$ff.cc:266:slice$17310 $auto$simplemap.cc:38:simplemap_not$65062 $auto$ff.cc:266:slice$17311 $auto$ff.cc:266:slice$17312 $auto$simplemap.cc:126:simplemap_reduce$17515 $auto$simplemap.cc:126:simplemap_reduce$17510 $auto$opt_expr.cc:617:replace_const_cells$324137 $auto$ff.cc:266:slice$17304 $auto$simplemap.cc:126:simplemap_reduce$21293 $auto$simplemap.cc:196:simplemap_lognot$17522 $auto$simplemap.cc:126:simplemap_reduce$17520 $auto$simplemap.cc:126:simplemap_reduce$17518 $auto$simplemap.cc:126:simplemap_reduce$17516 $auto$simplemap.cc:126:simplemap_reduce$17513 $auto$simplemap.cc:38:simplemap_not$65061 Found 8 SCCs in module processorci_top. Found 8 SCCs. 34.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.6. Executing PROC pass (convert processes to netlists). 34.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 34.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 34.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 34.42.6.4. Executing PROC_INIT pass (extract init attributes). 34.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 34.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 34.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 34.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 34.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 34.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 34.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 34.42.6.12. Executing OPT_EXPR pass (perform const folding). 34.42.7. Executing TECHMAP pass (map to technology primitives). 34.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 34.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 34.42.8. Executing OPT pass (performing simple optimizations). 34.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 34.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 34.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 34.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 34.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 34.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 34.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 34.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 34.42.8.9. Finished OPT passes. (There is nothing left to do.) 34.42.9. Executing TECHMAP pass (map to technology primitives). 34.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 34.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1061 debug messages> 34.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 34.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 34.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 34.42.14. Executing TECHMAP pass (map to technology primitives). 34.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 34.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 34.42.15. Executing OPT pass (performing simple optimizations). 34.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 34.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 34.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 34.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 34.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 34.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 34.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 34.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 34.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 34.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 34.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 34.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 34.42.15.16. Finished OPT passes. (There is nothing left to do.) 34.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 34.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 38314 cells with 249236 new cells, skipped 14603 cells. replaced 4 cell types: 6238 $_OR_ 475 $_XOR_ 62 $_ORNOT_ 31539 $_MUX_ not replaced 10 cell types: 32 $scopeinfo 2814 $_NOT_ 4756 $_AND_ 4284 TRELLIS_FF 1 DP16KD 4 MULT18X18D 595 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1058 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 1058 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 34.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 34.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 107098 AND gates and 274465 wires from module `processorci_top' to a netlist network with 8691 inputs and 3737 outputs. 34.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 34.42.17.5. Executing ABC9. Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 8691/ 3737 and = 73767 lev = 59 (4.80) mem = 1.34 MB box = 1653 bb = 1058 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 8691/ 3737 and = 92022 lev = 63 (3.95) mem = 1.53 MB ch =11673 box = 1585 bb = 1058 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 92022. Ch = 9309. Total mem = 19.31 MB. Peak cut mem = 0.35 MB. ABC: P: Del = 8270.00. Ar = 79760.0. Edge = 91308. Cut = 1135882. T = 0.31 sec ABC: P: Del = 8223.00. Ar = 80303.0. Edge = 88987. Cut = 1067920. T = 0.32 sec ABC: P: Del = 8223.00. Ar = 23163.0. Edge = 70445. Cut = 2180115. T = 0.55 sec ABC: F: Del = 8223.00. Ar = 20337.0. Edge = 65512. Cut = 1921924. T = 0.50 sec ABC: A: Del = 8223.00. Ar = 18972.0. Edge = 61458. Cut = 1979846. T = 0.82 sec ABC: A: Del = 8223.00. Ar = 18888.0. Edge = 61305. Cut = 1980714. T = 0.82 sec ABC: Total time = 3.33 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 8691/ 3737 and = 53210 lev = 51 (4.50) mem = 1.09 MB box = 1584 bb = 1058 ABC: Mapping (K=7) : lut = 15667 edge = 59555 lev = 16 (1.89) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 51 mem = 0.67 MB ABC: LUT = 15667 : 2=1066 6.8 % 3=3472 22.2 % 4=9017 57.6 % 5=1854 11.8 % 6=137 0.9 % 7=121 0.8 % Ave = 3.80 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 32.10 seconds, total: 32.10 seconds 34.42.17.6. Executing AIGER frontend. <suppressed ~24937 debug messages> Removed 78838 unused cells and 116827 unused wires. 34.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 15685 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 526 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1058 ABC RESULTS: input signals: 1253 ABC RESULTS: output signals: 484 Removing temp directory. 34.42.18. Executing TECHMAP pass (map to technology primitives). 34.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 34.42.18.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001010 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~2662 debug messages> Removed 1650 unused cells and 288110 unused wires. 34.43. Executing TECHMAP pass (map to technology primitives). 34.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 34.43.2. Continuing TECHMAP pass. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut. Using template $paramod$05a6d306cd725e69f51b1165d55b035df9d5a665\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$2e37a29808ea9d028852cbc67bbcbc7bc127b77a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$158ffd8e6cb0924866d9bc35302735abacf679a0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$d345781bc5d014060901f9e4c645b8d136f2a9c6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$907f2d2c02ff149f00785eb99b3e2aa8a6a3fccd\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111110 for cells of type $lut. Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027\$lut for cells of type $lut. Using template $paramod$581d7e5f451b6b3ddd4ad06c99f094a0a6e88e05\$lut for cells of type $lut. Using template $paramod$4d6e761a7a62dc9cc597aef6e1d49cac6bdc495b\$lut for cells of type $lut. Using template $paramod$03a9885a61e46980831d2c64059eb66aa27bbfee\$lut for cells of type $lut. Using template $paramod$a2f201d984e8bd96c8e0db17337de5e27f0661cc\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$a41f1fef22a0928d27fdf5da763576d46c440d8e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut. Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$c3a482cad5eb82ca49cbd18451d00e4b87d30c76\$lut for cells of type $lut. Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$aabd7471e271b32a66521313541174fbb89658ea\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut. Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut. Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut. Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut. Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut. Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut. Using template $paramod$70e649cff31ac39ffa7544751d17e54df9788341\$lut for cells of type $lut. Using template $paramod$a4feb7db8ce913743fc9979ff52d0c0d3ddae42f\$lut for cells of type $lut. Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. Using template $paramod$18455d4fd1270af2266bf4bb1c44971b2eb6b37a\$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut. Using template $paramod$df23d368a6ae8908771963811f5ab56f622887ca\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut. Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut. Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$64f43dc318f4c77b4186c3ebcba0aa7863e84359\$lut for cells of type $lut. Using template $paramod$8c0aa4283e004d7e549a2fa42300002224408629\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$fc6feb7ca0813ec6f9a6e104d2344b22630ad56a\$lut for cells of type $lut. Using template $paramod$29fb0dcbea7e19908c494ce4a8a756b15e2a78b6\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$6902893557ea1f2d8c63b4b00c0a0a0dff5059d2\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut. Using template $paramod$fc31732417b7be9ad8ea4524b9939a4cc422dcee\$lut for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8\$lut for cells of type $lut. Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$f6dc5effae5c2b2fa74fb9734eb02ac8c26dc87d\$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$6a9b42dd2737c91073e6a695b8ac858c4a8587d7\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut. Using template $paramod$91e303dedaa4dcc5053a2b80ff2dab844bbf2f3d\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$75603a53edd9d843680604eb05439e6d8c37db07\$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$38446ff493f776d29ea4f3122b249720a55b03df\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$369624b024132c6d54ca5ca0dec0683515f4f203\$lut for cells of type $lut. Using template $paramod$098e58216a69950f0886b9f52f31a2a03d30183d\$lut for cells of type $lut. Using template $paramod$fe07503be663f9fa136093aa0dea361797ccf48d\$lut for cells of type $lut. Using template $paramod$5b5755730b9a53f6c50cca29ba2f99d7e0bc0fe6\$lut for cells of type $lut. Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut. Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut. Using template $paramod$6230360d3448cb863f2f259c28a1234ced7c698b\$lut for cells of type $lut. Using template $paramod$9c10e17a0a1ecd0e2664d222f0eb0cb2cf52c224\$lut for cells of type $lut. Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. Using template $paramod$a9f1133a3906e1a228933cdcaf464c776493a7e0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$4ada6623d37ec283eedde0892d02a9dd8dc291d9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$eec22efc31481e6a2706a92743e67f4f90bad45a\$lut for cells of type $lut. Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut. Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut. Using template $paramod$c064d9f267b09049d631f66733af1b91c12aa819\$lut for cells of type $lut. Using template $paramod$2ca5a8bf2a853a223fe0e0148e443d1b7e1e37b1\$lut for cells of type $lut. Using template $paramod$122a4c0b007fa7ed75dbda7c4d71a52e22ce1276\$lut for cells of type $lut. Using template $paramod$493190373199e5a39be045ba23abb29ecef89037\$lut for cells of type $lut. Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$0b63e97eced3280c448b19f071cf5590523c6c1a\$lut for cells of type $lut. Using template $paramod$bac9d46c0d1e778167fa8869abb1a0d9da802241\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. Using template $paramod$47d97c9c1137cd50ea0954fbfa78aa22b83c1cc8\$lut for cells of type $lut. Using template $paramod$a0219a10af5eeac70b87184a9a0bdd503910b00e\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$c6d3cc319ca2f8027789b2bb7c2750659532a5f1\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$9af38526a244bef6c70fcfecfe119d1271bcd555\$lut for cells of type $lut. Using template $paramod$277f0d9bdab7f45e246092781abc5cbfb7b01a64\$lut for cells of type $lut. Using template $paramod$4d9139502ecf2b1785d0a53cef98d39b2fe0ba77\$lut for cells of type $lut. Using template $paramod$cf26e78a72065d53ffb657752001dcb9a1b50b88\$lut for cells of type $lut. Using template $paramod$1acadcd0d69a88cee1dd4830ab691e17a73cdf0c\$lut for cells of type $lut. Using template $paramod$8dd42bf81ffad3d97e207e1565310c97cc60f1a7\$lut for cells of type $lut. Using template $paramod$1f1ba2a145b5e3b6c6fe8bf542f757e55b69a41b\$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod$764aa2707e52d53a3f85fd28b9d5e2b2c6ab22e7\$lut for cells of type $lut. Using template $paramod$ad62e2871ff01f5077eec3938b49b239cc9c554b\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$99b0ba94092ae0b544f25d7a7bfbffc967b1c1f1\$lut for cells of type $lut. Using template $paramod$99bea6b1a6bfc821c80186f7c0bda101c86a5f38\$lut for cells of type $lut. Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut. Using template $paramod$a467a30aa37262e29bd6192d319709c8ad34e383\$lut for cells of type $lut. Using template $paramod$b3f38a0a636c96d3f8b781090abb9b5a43dc828e\$lut for cells of type $lut. Using template $paramod$6410b45ea4d1e53d7fd209ee0400ef5c9579c44a\$lut for cells of type $lut. Using template $paramod$de3406006c16cf7256a0a2fdcbb1597ad8f6cb54\$lut for cells of type $lut. Using template $paramod$fa0c5e7506999a5f8a3edfffa56bd42b28c9d898\$lut for cells of type $lut. Using template $paramod$aa3626012a9f4c78fb3bfb5dc963eb482ad9f5f8\$lut for cells of type $lut. Using template $paramod$d29bfac7b6ca1d1ec3af3f8b1f14a2822f64783e\$lut for cells of type $lut. Using template $paramod$f096cbf7810c657d1faa5ebcdd247974deedeea6\$lut for cells of type $lut. Using template $paramod$4452c60ce8cd6b4d0654835cdeed43560a848e56\$lut for cells of type $lut. Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$fa90e6b4ff54c9a3f6bea754646eebea90c24aad\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$c1f2e2db7622d85b54877319ab1b67005e8c2085\$lut for cells of type $lut. Using template $paramod$f06e87d93a0e58dc1cb371d4735a616eaa04d16b\$lut for cells of type $lut. Using template $paramod$fcb30a1ef590387064e2bb0c918db1df4b073e24\$lut for cells of type $lut. Using template $paramod$2aa2b14505c268b07d4736df6958c7b2acff3fca\$lut for cells of type $lut. Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut. Using template $paramod$542e2fdf39f66ee0d9684372297ec1f9c72087d5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut. Using template $paramod$979de479a84a5439cfb7d3e24973c47c411ea979\$lut for cells of type $lut. Using template $paramod$2e7736c00bfc547a37d9469f1a50c96017c3619d\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$a88cbe275ca0f24a28b776a3819125328c2b6eb0\$lut for cells of type $lut. Using template $paramod$505f25bbde9c8a7211011d75c0558a943fa7ece6\$lut for cells of type $lut. Using template $paramod$4fe5cdb13da5e1298983f8531c96681a078669af\$lut for cells of type $lut. Using template $paramod$4f6c427e450051dd453e2b575a990eaeb1ee78dc\$lut for cells of type $lut. Using template $paramod$710f5f640381dad6f2f07ee612f05bdc36c5e919\$lut for cells of type $lut. Using template $paramod$36fb954fd1469be7711f3f35d1cf4254787dc9a4\$lut for cells of type $lut. Using template $paramod$a68913828bbb58e0b0500c3b3f04848e27088118\$lut for cells of type $lut. Using template $paramod$98a063e32ea3bf8a7916138f941d6de3fdd19d1f\$lut for cells of type $lut. Using template $paramod$57591f6a7e5caddbe11118347014ed2c69918857\$lut for cells of type $lut. Using template $paramod$38d9b52218f09f92dca3c16c4c8aa4775b609233\$lut for cells of type $lut. Using template $paramod$217e3704ee00674df3f9b3e3e62ef04be6d886a1\$lut for cells of type $lut. Using template $paramod$479ea6fe838844a478715882cf7334706d3120a7\$lut for cells of type $lut. Using template $paramod$f34a48e0d7a365b4e442b47061dc056123591986\$lut for cells of type $lut. Using template $paramod$44f6f0c0bfe5b6d2a869195ab8d9a5463325cd31\$lut for cells of type $lut. Using template $paramod$fd16523b66efc91890bfb23f6b1dcc83fa36d799\$lut for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$47ae8a7a32d39025bbfa5b812ca0d416fc9a139e\$lut for cells of type $lut. Using template $paramod$ae9b8688208bc968e066759f867620e9ddf86c4d\$lut for cells of type $lut. Using template $paramod$e6b9780adb26c754c7bef7481c96a6e42a99f4e1\$lut for cells of type $lut. Using template $paramod$286ed3273cbe066b6afe10d043ec3b66405aa78e\$lut for cells of type $lut. Using template $paramod$c30fb612eee74cbf3329ebe1f063d70178a932e3\$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut. Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$1b9eda9029cce84a5ef2677028d91731bb8d62a7\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut. Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut. Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut. Using template $paramod$d8aacfe44f73067ae624820f2e713299b336a863\$lut for cells of type $lut. Using template $paramod$eac27cae3d6afbfd3b980a38baea6514f8888398\$lut for cells of type $lut. Using template $paramod$cdfb4ce36e9b97ab980954e4bd7262833a7086a8\$lut for cells of type $lut. Using template $paramod$9326b9860a66e3520d341f9f884332833f6e2e93\$lut for cells of type $lut. Using template $paramod$cc173bb48f638125313eee2d9b59be0a55452992\$lut for cells of type $lut. Using template $paramod$209427cf130f11be73f72b84b9476f792346f8fb\$lut for cells of type $lut. Using template $paramod$dd5f0effcc626097813478610efa1358d0ec4613\$lut for cells of type $lut. Using template $paramod$a24afe75f337e4c896a41549f32c9f3bd1699100\$lut for cells of type $lut. Using template $paramod$52a4e3305e4f38db14bbeea0630a5b2fde891140\$lut for cells of type $lut. Using template $paramod$4bbf9b1cdb52533258f0dd3190b5b8ca2171505b\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$943d8317b095493c0e0e37a924459f289b3162cf\$lut for cells of type $lut. Using template $paramod$841e3e784fbecd69498a8a70417426a0e21583ce\$lut for cells of type $lut. Using template $paramod$99395cb35e468d81573486ac9ad4942686120338\$lut for cells of type $lut. Using template $paramod$d3e8bb6d235f74996a6dc91d192fba44c919e86d\$lut for cells of type $lut. Using template $paramod$d99fe901f2b9255ca1d28963d986a4221cce8178\$lut for cells of type $lut. Using template $paramod$d8c15619e14e23259772acc1552b8b29afbd81c5\$lut for cells of type $lut. Using template $paramod$4c1defcc9d750b26fe1af724abf4ac05b5c83b61\$lut for cells of type $lut. Using template $paramod$ad5cf08aeb66e17243b8b319f939f1804a0e2d64\$lut for cells of type $lut. Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$162a17aa64d8bee90cb0e5a5a7df2d91c7b6e663\$lut for cells of type $lut. Using template $paramod$b601c6e1cec7f31fe79ae37853752c12c15b59c0\$lut for cells of type $lut. Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut. Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut. Using template $paramod$e2dcb3e2e15ddf17b70cdd5f17aa4d4ac1778266\$lut for cells of type $lut. Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut. Using template $paramod$fdf66ab4b4b9acc27eb403bb38c9427ff18140b7\$lut for cells of type $lut. Using template $paramod$738f898c0e5cc0e1c606c9b722f51c9eb3d21574\$lut for cells of type $lut. Using template $paramod$e93bb82786aeb528dac327680f34322e5dc5ba4a\$lut for cells of type $lut. Using template $paramod$c4db105ea159088a3bf17cc7822e67a3ce1e1403\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$05dd5d01546eff9da45f32c923ffbe0f9afdb118\$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut. Using template $paramod$b7e1f0e44e1823882f3ed6063906649af1d55c48\$lut for cells of type $lut. Using template $paramod$1f480e48cb25f29ab31c086d24c3ac0e27503b53\$lut for cells of type $lut. Using template $paramod$19f2b84e1bb450406316029ebd8ee7e8597f5772\$lut for cells of type $lut. Using template $paramod$e47b6a8c5de30155657a953d595534096c163fe6\$lut for cells of type $lut. Using template $paramod$16cd595f3784d7799243a25e45643a3229ed4a67\$lut for cells of type $lut. Using template $paramod$9a9da924fa89fa54bee2d18ee8db0949ceae4c41\$lut for cells of type $lut. Using template $paramod$c581f6382c881129fac55eec32fe31b4c289a2e5\$lut for cells of type $lut. Using template $paramod$e0bfc0bfd924d0e71e8a017991ea57225d9b0fe1\$lut for cells of type $lut. Using template $paramod$9442b9c02ab35bdd35bf679d937a119610b4dd50\$lut for cells of type $lut. Using template $paramod$925f7d61ce09a74d912d3fd935c6246df794b032\$lut for cells of type $lut. Using template $paramod$69c487457c4a44540bb337fc36d6e5979b67bec2\$lut for cells of type $lut. Using template $paramod$24d5a2ee14a11bf314bac89096953d27e14c42f6\$lut for cells of type $lut. Using template $paramod$b20b44b7ecee5be956e2b152bbe403b0db4146a7\$lut for cells of type $lut. Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut. Using template $paramod$a2f01eec25eb92d08608e73046bdb01195b11a42\$lut for cells of type $lut. Using template $paramod$34c46304afb05a32ee429b600dba052c958e2ef2\$lut for cells of type $lut. Using template $paramod$d28c007f5f10b98689681fa7da5208c9de5b5cca\$lut for cells of type $lut. Using template $paramod$7ab9990e447a92f0817942e45bfb8b646848e027\$lut for cells of type $lut. Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut. Using template $paramod$4aa991d9efaf1e982d67301272dd490523f55123\$lut for cells of type $lut. Using template $paramod$0126c2016cf7cb8d590c6bc51b50e6a17147623c\$lut for cells of type $lut. Using template $paramod$4127e3976804cc3e2776f400bd237bcbcbc6c10f\$lut for cells of type $lut. Using template $paramod$c4af7f2c88559dab5f19c52110f1d82cb05f465f\$lut for cells of type $lut. Using template $paramod$bf58e52cf1673fd938f656d7468b5e18a1334297\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod$36e89dcccecf8b7e9d7a04896071ba5c013fd52a\$lut for cells of type $lut. Using template $paramod$a98d28a2067e6dd205be49645f834c77358190be\$lut for cells of type $lut. Using template $paramod$de49ec48fb9fb34795223691593c9be7bba71de0\$lut for cells of type $lut. Using template $paramod$84bfd279c420105d0e22d3561c5a7327ecc11a36\$lut for cells of type $lut. Using template $paramod$54b7ce7904fd9d071f751a577d06ddccfb38a6fe\$lut for cells of type $lut. Using template $paramod$18f5ec715c75305313723b2241c5943a1bb6d4c6\$lut for cells of type $lut. Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut. Using template $paramod$006d3fd948daa4da193f5f3c3e4477a20c832093\$lut for cells of type $lut. Using template $paramod$f66ecd8f85756553bcd76894ae42ed979fcaf28a\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$8ad866bbc4c3a0596701b99858a2da014a3cc9cc\$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$b6d1f9625ec06bc9dd09e13eb65e3ca174d43b6b\$lut for cells of type $lut. Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut. Using template $paramod$c7754eeb17b54dfe53ea4a973db3714d78ced2f9\$lut for cells of type $lut. Using template $paramod$ba292da9aae9dd9f76bc59644ee5ef3d51d40898\$lut for cells of type $lut. Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut. Using template $paramod$d48fb68458f3609c8be80460088ff896c00e444a\$lut for cells of type $lut. Using template $paramod$384debcf9fa043e8bb1ee2ee1902bb339a5b697d\$lut for cells of type $lut. Using template $paramod$410654a338494d4983a424035c9c9af4ae257a26\$lut for cells of type $lut. Using template $paramod$e40b2ba49169b1445783c950cb43cc9ffbe76ded\$lut for cells of type $lut. Using template $paramod$6947968f931c2f125c52655bb46651776102aef5\$lut for cells of type $lut. Using template $paramod$1eec9029503e60e145acf839376853a98897d59d\$lut for cells of type $lut. Using template $paramod$037e5c75431b2a5d332077e65b15ab881054b4f9\$lut for cells of type $lut. Using template $paramod$9f12969f7788d83c0badf6cb5ca4e6b2e111849e\$lut for cells of type $lut. Using template $paramod$f2173573d28df9e83416399b4aad8587656b198d\$lut for cells of type $lut. Using template $paramod$54b128ac3c41e253b64b8f6ecaed75d060043449\$lut for cells of type $lut. Using template $paramod$be80b32a1a41df3594c2240cee4d1aae5002aa55\$lut for cells of type $lut. Using template $paramod$862635d0958c52e0798deb5dc6ad81cd865a0974\$lut for cells of type $lut. Using template $paramod$d6000d96f7daae023aea1d235aa57406d3b9e9d2\$lut for cells of type $lut. Using template $paramod$f393a4079a98d6a46ef85bf2daf70f7d71abe006\$lut for cells of type $lut. Using template $paramod$610ed033917b10905ea451216c42151463ffb758\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut. Using template $paramod$f263a3e69b6adf9dd28ede51609e61c2362bf701\$lut for cells of type $lut. Using template $paramod$c5c8a027a324eac9484ec2647e99f2806d914bed\$lut for cells of type $lut. Using template $paramod$57db67c9b4c7c49765c11cfa5912d38cd9a5ad67\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$c685a6e5e211287be351ac5f1078c1501564ce89\$lut for cells of type $lut. Using template $paramod$15b36bd2f0d7cfb31f0bf2e4ce4d1a1f9d5f6c96\$lut for cells of type $lut. Using template $paramod$b1edec1b752b1b025ec2a69f24c8023c8be1c212\$lut for cells of type $lut. Using template $paramod$f5c118b1371bfc24986fe89a9f3e936c05edfbc3\$lut for cells of type $lut. Using template $paramod$565e62432683cf712bfdef4a0b6dca8eb8dca433\$lut for cells of type $lut. Using template $paramod$7f7120086b74d2ad6501bbaa30925c183268a1c2\$lut for cells of type $lut. Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut. Using template $paramod$68cb09a5d00037369a2af39e1778bf17484c020a\$lut for cells of type $lut. Using template $paramod$b09985e8858c91a37082b9e96d646971d16d54ab\$lut for cells of type $lut. Using template $paramod$fb35c135fe8aec7ccb9ed7de3fef9d7432487667\$lut for cells of type $lut. Using template $paramod$5f2c9a2f2a8609af550050e98d18f223d31572df\$lut for cells of type $lut. Using template $paramod$f1a272bbca4e6bc81f625b6ea3e19a5077916a0e\$lut for cells of type $lut. Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059\$lut for cells of type $lut. Using template $paramod$eeed37ce45abdda29d3e180f2d1dfc0c4c376530\$lut for cells of type $lut. Using template $paramod$949305f8eb1aa3e83fdd363bf0793929b99bba33\$lut for cells of type $lut. Using template $paramod$8f8a0b36136f4b4ebb1a771881ec4db342c0e21b\$lut for cells of type $lut. Using template $paramod$1732c9918f745d8a61fc13a2b8173909c0a5d13a\$lut for cells of type $lut. Using template $paramod$68e3d3f27e6a41c3bf8782ac6aac602773fca3a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$896ed47860542f5b317e8ecb6db17e90c36ffa18\$lut for cells of type $lut. Using template $paramod$c7b80ba430fcbff15d6bf260d454531db01b4698\$lut for cells of type $lut. Using template $paramod$99f282532c29942fbb2a9e103b50d87f80a6f0ac\$lut for cells of type $lut. Using template $paramod$97472f517efe00e2e4bbd270b2ef0f8e6d9a1199\$lut for cells of type $lut. Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$b18e22193cd4b94c8356eb257d652cb5586aba6d\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$de5074a80e0a92a065a2ccd0d26c618282111f8c\$lut for cells of type $lut. Using template $paramod$8afc150f86856908872b651f9f3ef5e32d74a51a\$lut for cells of type $lut. Using template $paramod$168aeef333136ff4f1f2ce3a62c8b6d1ffc7dc28\$lut for cells of type $lut. Using template $paramod$a9011ee24d52971e6ba0f7d694c587084c60e911\$lut for cells of type $lut. Using template $paramod$c39bbcce81dae514aefd17dbc9fef8e011d41497\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut. Using template $paramod$b053538fb4536514881298fa3d5e86574e44ce4e\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$9c9c977d4ef412c658600f27af104e72c77928d0\$lut for cells of type $lut. Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut. Using template $paramod$9049397e8df8108adcf55f7aeecd1b2fb9b498f6\$lut for cells of type $lut. Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut. Using template $paramod$e53493f89400484e4e19015869a8a6f7d3804aa9\$lut for cells of type $lut. Using template $paramod$b5d2ddcf66f5237fb7b81882f14baf21a2e8ebb7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$a466678992feb44cf6749703c13a9fa3f3b5c308\$lut for cells of type $lut. Using template $paramod$d497222f59d990d3f689ed9c6ac453ecc8a2f4b4\$lut for cells of type $lut. Using template $paramod$37cbd66b1bb96fdf033ea86280ae98f0988c69d1\$lut for cells of type $lut. Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut. Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut. Using template $paramod$629e516b94e0a0974ae9cbdf787cc1ef4d36489b\$lut for cells of type $lut. Using template $paramod$6dc05f9f044ab30f5362b0c302f3cf6295cf2d76\$lut for cells of type $lut. Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578\$lut for cells of type $lut. Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut. Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut. Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. Using template $paramod$dde5a9ef7dd688dfe6598c87be62bbece830ebb4\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$4efada11a78f36553c4a0315ee8e0b6fb68fc1f7\$lut for cells of type $lut. Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991\$lut for cells of type $lut. Using template $paramod$af0c0e3aea5daa768aac0697b02a2a49301800b1\$lut for cells of type $lut. Using template $paramod$d0f8e9e00b83cb69742e69fe894a4d457c015e6a\$lut for cells of type $lut. Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$d96af730adf02974ec3298258a511f8b9b1fc45c\$lut for cells of type $lut. Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut. Using template $paramod$9fd469f9fe753e57cb367d7184c354b9590c6906\$lut for cells of type $lut. Using template $paramod$0ae7705354ab4bfd071e2551e0df024a40a698f7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut. Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut. Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut. Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$79bcd9c929188a31ac5b4e32ffab9d7e442329a0\$lut for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$e811f181f79540ebc885b643c8dca6910da535f8\$lut for cells of type $lut. Using template $paramod$77268019239d7d46332da9cb6aa01cbf3ba29ee3\$lut for cells of type $lut. Using template $paramod$5e906f48ad24af4729130819a225de2d9941ea3f\$lut for cells of type $lut. Using template $paramod$34c8638ead02b5b5f9320c99bb886f461cbdcdad\$lut for cells of type $lut. Using template $paramod$3427de03640437352391c1e3a751e193e8ef5801\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod$9fb70d15ea1df6d097a7b525f3a7580f7a8425e1\$lut for cells of type $lut. Using template $paramod$0b4ee59a409d29a290efc6bccf2e405f2e6de190\$lut for cells of type $lut. Using template $paramod$e4347672e645a3525f873265f43a44c5703bc7d2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$a467e3aee4b54a60cdec89714694957109e0405d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$e91b01f9349714d55057bc22c604be26aa38a50d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633\$lut for cells of type $lut. Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a\$lut for cells of type $lut. Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$3eb61a9b4835399f9e41942bc9767d04b8dcbe31\$lut for cells of type $lut. Using template $paramod$138de7e0099c319c71b087ce70b42c2a60968d57\$lut for cells of type $lut. Using template $paramod$b624d3f875e7f2cae34aca9d270aa11d8c307ee7\$lut for cells of type $lut. Using template $paramod$cde8c7701f781a3a761fd85082ff594ff69a3ab0\$lut for cells of type $lut. Using template $paramod$4793770fd1612faf807b0d872481616498932ecd\$lut for cells of type $lut. Using template $paramod$adba359a8eaae620067ce67a434371ed510c6fd5\$lut for cells of type $lut. Using template $paramod$a5294f427f829374ed09afd70d020db1e3174eb4\$lut for cells of type $lut. Using template $paramod$af41c0b82981dd48cc2c8945d6a90da24c37455f\$lut for cells of type $lut. Using template $paramod$4772c1fa00675f71dd31117457abbc4d5cb28e75\$lut for cells of type $lut. Using template $paramod$8932c2e7042c44db7fb6379063062cae7cad5ea9\$lut for cells of type $lut. Using template $paramod$808a8c315a1957b4460f000e0c9f0b0526fc8e83\$lut for cells of type $lut. Using template $paramod$a52ffd791c6dea036d629826af111fab8a2d8565\$lut for cells of type $lut. Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3\$lut for cells of type $lut. Using template $paramod$f2dc00443d763a467114b3b226384f4116750680\$lut for cells of type $lut. Using template $paramod$862be0802b6435b9deaac6d4944c9cec053ecbf1\$lut for cells of type $lut. Using template $paramod$35bf242b24a74521da559d972be66bb13acaaff8\$lut for cells of type $lut. Using template $paramod$da40f3cf36180f3ad492a06912d4ccf50645590b\$lut for cells of type $lut. Using template $paramod$e004aed0e5cad59e4f5a06e378eb3cc5e3d94084\$lut for cells of type $lut. Using template $paramod$b1792bce2a794ce7d3f7aac0d1fb4b841b187447\$lut for cells of type $lut. Using template $paramod$2e899de1a9b790497783734d32290d9194873358\$lut for cells of type $lut. Using template $paramod$e3eba4034177489266ad2d2914a684b2cbb11d17\$lut for cells of type $lut. Using template $paramod$f2373e49d7a28dfe0f70f4ec25ecc6a3d674919c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$f0169807cabb208126f94e3f71552cc012e8013f\$lut for cells of type $lut. Using template $paramod$16ff5f5c4b0b4c036b20658c0f6a70fada0f7901\$lut for cells of type $lut. Using template $paramod$3d2995edc4e3916756d41d51836ee483b05874fb\$lut for cells of type $lut. Using template $paramod$968bbcc64da0b510b4577f17a4a470793a3617e9\$lut for cells of type $lut. Using template $paramod$ec95c9b21ec0925c80988ff02b89cb4ae04739a3\$lut for cells of type $lut. Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$91bdb23d9b60d1f7254461792a6db3468fa5ace0\$lut for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$2fa16d4c3d345074954635de91dde258ad9795ea\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$a1cfe99817bd6d57a83efd5e1c3fc26a743b692f\$lut for cells of type $lut. Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut. Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$d40cc697e4bab284c55239c1af544a9890ffd43c\$lut for cells of type $lut. Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut. Using template $paramod$67be80acf92b4861aed3d8085a5bb296f128f875\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$4bd488bb9e7b92f6843c86d97a879ddbc9bac2f8\$lut for cells of type $lut. Using template $paramod$e4ce17fcded6e264148ce0a4c0df3ed1b1b269a4\$lut for cells of type $lut. Using template $paramod$9c2d333541bc836d4d6b78e102bdc07b3b85da08\$lut for cells of type $lut. Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut. Using template $paramod$d0a46f8637b2b026d480bf9e8554ef5d086fd1d1\$lut for cells of type $lut. Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut. Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. Using template $paramod$810e0f22d547104f8208898922f6ac2444aeece7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$a88d6a8ce8fd5d33cd3a669ac5bea735659071b9\$lut for cells of type $lut. Using template $paramod$247cb0cf40b3b63b2ea4a21b15240b4831ffbf4d\$lut for cells of type $lut. Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0\$lut for cells of type $lut. Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$0179900ce7810982cc4aa4215246fc34bf4c070d\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$2ae22ed255cc0f3746c71b5da2407ee38a2a66e6\$lut for cells of type $lut. Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111100 for cells of type $lut. Using template $paramod$aa79b66d99645f2c6597509fe375a3cb97da6e36\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut. Using template $paramod$ba07846b1e706d3eb2010a528b0f0417e3645924\$lut for cells of type $lut. Using template $paramod$60096d1cdb5f7f55fdf4ed3aab322b5c7375f61e\$lut for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$efce95869eacbcb4d48548e73d703e4fbe2b3843\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100110 for cells of type $lut. Using template $paramod$a89aba8af1491ba21b57c9687d2e76330038ca23\$lut for cells of type $lut. Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut. Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod$4c8de682f2508054a5f7f13444038e3331866a9d\$lut for cells of type $lut. Using template $paramod$46e0c58da989560e0dc35528a00016369495a2aa\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$73d07df06bdcebf8bcc513075902f140fba061ec\$lut for cells of type $lut. Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut. Using template $paramod$ee82f1504b2c48e70160208feb4e1f2a1b612b8d\$lut for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod$93f74d366819d1f86e5e8b91d159aa6b1cd7e9fb\$lut for cells of type $lut. Using template $paramod$ee454ad2383885733a4273245816698f8443c10b\$lut for cells of type $lut. Using template $paramod$c471af5667a682bd131a5b479e58e470d1b2b7cd\$lut for cells of type $lut. Using template $paramod$3fd6fba810ce8a50a4b7da25e41badc3b8f92e9c\$lut for cells of type $lut. Using template $paramod$2a4c70bb130c3c1c9358eb8cf9e3e31d26e4ee19\$lut for cells of type $lut. Using template $paramod$71bb37e52ab07853763feaa9c5193910953bf062\$lut for cells of type $lut. Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821\$lut for cells of type $lut. Using template $paramod$2bf796e0fd6e6f7f76aac424a34e617ed5d61822\$lut for cells of type $lut. Using template $paramod$bcc5b9fc09d0cdc8bad6b96e9e7cf91abb8e99bf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$7a09c632ebd39a203628a04507a2df81de3ade57\$lut for cells of type $lut. Using template $paramod$34ccb0403abd26609d9a7a8ea9a44b40cc4b3caf\$lut for cells of type $lut. Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut. Using template $paramod$9c8948120cf9187a89327db79d1edbf7498d180e\$lut for cells of type $lut. Using template $paramod$53d1295e92eea38a512b9ce693445c7190afdb5d\$lut for cells of type $lut. Using template $paramod$acd2aac62f6cac8eccb6441cdd9fcd1a9733ebff\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. Using template $paramod$27331a24b2c1dcbe1b3eefac456a3f892f3b23d2\$lut for cells of type $lut. Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. Using template $paramod$2e07632c5a3e6a4cc186187735a3f83418a7be82\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut. Using template $paramod$3538781ccdac1cfa3ad11d05d3d609f1cfa2d6b0\$lut for cells of type $lut. Using template $paramod$eaaa84c47ca82faae87b70180fc2d10219fbec83\$lut for cells of type $lut. Using template $paramod$10b7b810a6a6f18bc62789393bbe16e6a166c87b\$lut for cells of type $lut. Using template $paramod$d48f8ceec054281b578490d77dd0f15af6b6059a\$lut for cells of type $lut. Using template $paramod$fa874836ac64420bb7d9c67e99a0912e16a50ef2\$lut for cells of type $lut. Using template $paramod$20aa1a2066ab3c0f99d3cdf831d4a4a80ce82e48\$lut for cells of type $lut. Using template $paramod$bb30b1a7babe3b9233abcb75d43d2653a9294bb7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$a87662230f14ba9dfff5245dcac6285924ced66e\$lut for cells of type $lut. Using template $paramod$84f4f1db72921f11c5ff5a4dc511dfd4d3da404b\$lut for cells of type $lut. Using template $paramod$8a10a67809a4c226e7b6ed397585f1b2ade29b11\$lut for cells of type $lut. Using template $paramod$555b6355e2cc751ac120ccebbd6efcfbc305670e\$lut for cells of type $lut. Using template $paramod$d1811e0583d804ea16898fbc4fbb7d65fdabce34\$lut for cells of type $lut. Using template $paramod$92c896c64d97f7c2befd3e8605eaa23394b19eb3\$lut for cells of type $lut. Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$a9cb9dd2ae53f9f653d897b4deb64cf4578be21a\$lut for cells of type $lut. Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut. Using template $paramod$8670261af8d77851d2850ba537e3a1d0e2415376\$lut for cells of type $lut. Using template $paramod$c5fc75a3c76ca4b62ba5ce67ff8eaffd884835f1\$lut for cells of type $lut. Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f\$lut for cells of type $lut. Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut. Using template $paramod$d9fc5fb4745e58600f67710293bac14c7b88c4ae\$lut for cells of type $lut. Using template $paramod$e7637f1be1949574070814253bcbf9f2ae67848b\$lut for cells of type $lut. Using template $paramod$db6b7476922213a65b6e3c3c166d39eadf7a7fdc\$lut for cells of type $lut. Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod$3fb4a429a639413454e34f7173da8b9aaf03d0ea\$lut for cells of type $lut. Using template $paramod$498cbe6cad8fd07d22bab7a00c255df47a3db1c6\$lut for cells of type $lut. Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut. Using template $paramod$06e1b49bb860dd46d7e5fdcbc52d5c30182f8b56\$lut for cells of type $lut. Using template $paramod$ba38eeec612c623fb7e710aa4d96a3562d261f4e\$lut for cells of type $lut. Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$6d12474009748d01d8ed1612a4ef5c95b9566511\$lut for cells of type $lut. Using template $paramod$f8000fe33260f18f98877185a6d2e12a6429deaa\$lut for cells of type $lut. Using template $paramod$8da02996bc6ce025fcc2ce1dafd66f4b38a423f1\$lut for cells of type $lut. Using template $paramod$a2024abf1a6d35bcb62c7cb6f3ec4a9a4c877d1d\$lut for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut. Using template $paramod$8007890b7c312b28a93dc29414cc6c549d0ba2e4\$lut for cells of type $lut. Using template $paramod$cc88270836ca29009a83d7e3eaf54afc4b29bf0a\$lut for cells of type $lut. Using template $paramod$f9df0bb8fc3cbb332d575e165ec04d3cfd4c90ca\$lut for cells of type $lut. Using template $paramod$afdefd64f115cbb578c1cd4bf8426ecfef85ae91\$lut for cells of type $lut. Using template $paramod$a6118d686571c20cb41a5d362c37fb3352298664\$lut for cells of type $lut. Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut. Using template $paramod$9efcd5bca10c86c8062ffedbdefc9bd8ce8b131b\$lut for cells of type $lut. Using template $paramod$c293d662ac6569c9d75885e3ce9682757668dc1c\$lut for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut. Using template $paramod$438733590234373c3154a23071e2096f0320cb50\$lut for cells of type $lut. Using template $paramod$2d73cf21e7a3b53006ebbae47ecc48e73975ec46\$lut for cells of type $lut. Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$b24a6949de0206a709376780390ad806ea9da7a8\$lut for cells of type $lut. Using template $paramod$985ba471fd4b0b2ea1527559f9e896c6a26de3e2\$lut for cells of type $lut. Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut. Using template $paramod$cbea2d4d520f64cae694e02ff7f67ddafd2047d5\$lut for cells of type $lut. Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut. Using template $paramod$e5758a88c2c156ccb3037f71a73d1b15af5b310d\$lut for cells of type $lut. Using template $paramod$577f6b33df787137f4b90a9e4e5b34ba8a5accc0\$lut for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. Using template $paramod$b83f18039e7868b0127a3335c948aa4a647a8441\$lut for cells of type $lut. Using template $paramod$4045162732ff1ef3063f7c74bcf446c45645f6c6\$lut for cells of type $lut. Using template $paramod$c35492cebda5b908d10e5976bd14d50fda8ce5fd\$lut for cells of type $lut. Using template $paramod$b04f0510561c4bbb703d2e39c6eca682b920366b\$lut for cells of type $lut. Using template $paramod$281d7d2f622df4f002cd717126ffd4e322f859a2\$lut for cells of type $lut. Using template $paramod$68ec41789854bcc451d816d82c985c979e331641\$lut for cells of type $lut. Using template $paramod$96f6b4094ea1411d7c9aea8d540e6f5abc44a64f\$lut for cells of type $lut. Using template $paramod$509061f88e1db7dfaf19873d4cc611e2870d15d9\$lut for cells of type $lut. Using template $paramod$40e5a5bffee68d424d8b966d83c16c547cdeb8ab\$lut for cells of type $lut. Using template $paramod$9411ab5f327581bfd24ad527703788c82debb01f\$lut for cells of type $lut. Using template $paramod$f0773b2e1ec54f4b5730a332b99958a07b433091\$lut for cells of type $lut. Using template $paramod$411456c818123bb6bf92dc678013eaca36b016e1\$lut for cells of type $lut. Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut. Using template $paramod$1c7d8014a4d7918ee35a20538945662d20569ae6\$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod$f65cf6380214e831938c4f25f730307ae86218f7\$lut for cells of type $lut. Using template $paramod$f1f436aa4c139cc1446adac5bbebcc59a5d0436e\$lut for cells of type $lut. Using template $paramod$1780bd352ec1af971e2f8a4e64b861091a94595b\$lut for cells of type $lut. Using template $paramod$515ef3a9b5e42bd5d7533bdf444ebd44fa8b3ff0\$lut for cells of type $lut. Using template $paramod$0c0ecd52ddc4062e855792f313b58212abf7867f\$lut for cells of type $lut. Using template $paramod$3ec83cc0e0ec241030d7c40596e80d62c44c0f57\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$6a0bf72c1f04717323c96453558aebc0fd3dc134\$lut for cells of type $lut. Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut. Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut. Using template $paramod$f1a1d9f676e9a8dfefb9d549b9b2c26a026e27e6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. Using template $paramod$a811a92df9946b538101ce2dd22e23feb6aa6fd8\$lut for cells of type $lut. Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut. Using template $paramod$e343406e5e7142fc2d1b3b4b19848be7fa882f02\$lut for cells of type $lut. Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. Using template $paramod$01e96e53d77f79e0721c00741bd5ab06a9e25a93\$lut for cells of type $lut. Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut. Using template $paramod$28e2a479987a035f608a836ed0e0d93dcabf5445\$lut for cells of type $lut. Using template $paramod$ddce54e04aa2e21dc36c3f216625e49798f2ceb0\$lut for cells of type $lut. Using template $paramod$02904265621ae79a27c13b089e66a2817bd924bf\$lut for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut. Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut. Using template $paramod$c75656bc8af73b1fd37fc2f9580b970bd545f476\$lut for cells of type $lut. Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. Using template $paramod$ee04a7397c7e60ad1a187fa314ed449c24407f97\$lut for cells of type $lut. Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut. Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. Using template $paramod$d8325753180ccd86c828757d9dbb16c299287a89\$lut for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut. Using template $paramod$3b4ad1562035d92f4c44be215e35c57d0fbd2dc9\$lut for cells of type $lut. Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$4f885685dad0f4b3e324e9c13364f17ead36f4ec\$lut for cells of type $lut. Using template $paramod$2fb03879aa352413f26c730779a4de43e1f1b847\$lut for cells of type $lut. Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod$93de6ac482faaaffc2aba3d9054f1d8bd21cc047\$lut for cells of type $lut. Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. Using template $paramod$849eede967b3c8935808391f1a9ce50503aa897a\$lut for cells of type $lut. Using template $paramod$2b81c22187dcd49311a976bb63273aa43c4d3b68\$lut for cells of type $lut. Using template $paramod$09aa8a3143d50cc59564172c2564d6271fb3a300\$lut for cells of type $lut. Using template $paramod$4f750cb34540bad7e8d277dd5bc5ea63e403d272\$lut for cells of type $lut. Using template $paramod$64ed40f74e19bff7f50592ea328f713c3f8b3f50\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$c8e56946d7b33b4de9359965a8ef2b5e8c6d31ec\$lut for cells of type $lut. Using template $paramod$6aa123f49eb0ae3739d6708812cedabc589076b1\$lut for cells of type $lut. Using template $paramod$b9305c669fd883d24574655b402c7ff9f28efb1a\$lut for cells of type $lut. Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut. Using template $paramod$3357e04690749b6c89de0fcd28f53cd216bd2047\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$31f0a66a4b242b524303bfb4ac95c05ad74158f8\$lut for cells of type $lut. Using template $paramod$8f0687b3b1e843d1af48a2820ee1e560d6b66240\$lut for cells of type $lut. Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut. Using template $paramod$b7d5a1d13a95755f80d49e78f7fe57dd63a6cfbe\$lut for cells of type $lut. Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut. Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut. Using template $paramod$32f7007f246774394e67bc390776b559866f0172\$lut for cells of type $lut. Using template $paramod$ff58554493773336c4e06dc62f25c37448f98c7b\$lut for cells of type $lut. Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut. Using template $paramod$05c363abf9bf41737697db9a75c379869832d91c\$lut for cells of type $lut. Using template $paramod$8fcabb9d15de2b8ca455eb21a1766dd26053da49\$lut for cells of type $lut. Using template $paramod$f5c190b70f0b3d9eed9bfab22c6be8c729d88264\$lut for cells of type $lut. Using template $paramod$accf50a247cd8bba7db1ad1f71c658b6b8d28bae\$lut for cells of type $lut. Using template $paramod$7cee57d9dcc55a6563a352ca875ce6c911ea716c\$lut for cells of type $lut. Using template $paramod$a511f425a16be7369933baa8c17a62ec61a7d7bf\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$323795ee8810c4cbd4fca610cde089564d3ee6ab\$lut for cells of type $lut. Using template $paramod$6f20c26c0721e8b3757ca7b9a77b6e1d35f0f91c\$lut for cells of type $lut. Using template $paramod$21eec977c2ba62e532de58d602e74bf0a3c778ba\$lut for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. Using template $paramod$37203517188e0e81c6d1574dd1c274ed56646adf\$lut for cells of type $lut. Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut. Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut. Using template $paramod$5b522c549bf568db4969be109aabdbdd1b5ea20b\$lut for cells of type $lut. Using template $paramod$718179c4766b4ea66e8ece9b944be5b997b67ba5\$lut for cells of type $lut. Using template $paramod$782961deb8dc512aef835b73aa3765da3ab3c15c\$lut for cells of type $lut. Using template $paramod$72ec34f0d3574fd4a61ad277dc680da7ce75f22e\$lut for cells of type $lut. Using template $paramod$e5e0b3ddfad741c9efef28018ea9d09c68de87c3\$lut for cells of type $lut. Using template $paramod$6423d726e9a2aeb860255b5262559102a32c1449\$lut for cells of type $lut. Using template $paramod$24c1f285a7007833594bc4fc8c3ab552b1afa454\$lut for cells of type $lut. Using template $paramod$0aae27145afd1348566af63c85046495acb0e0d8\$lut for cells of type $lut. Using template $paramod$2a87bbdfb768402a9654f9f52ad31004d563a8ea\$lut for cells of type $lut. Using template $paramod$c4a4cf1f67c598049dd5cb5cdb183838e000e772\$lut for cells of type $lut. Using template $paramod$ee3aee51512c440156b3fdfdf887fb8c17d950f3\$lut for cells of type $lut. Using template $paramod$dc80e74b9623b8a802ef4b5162559616e5ac1cef\$lut for cells of type $lut. Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut. Using template $paramod$73fc99f0476d5b99ebe5ad1e9b585f498ed61c67\$lut for cells of type $lut. Using template $paramod$e5761adfcc530461835be17350166b9d43dfadee\$lut for cells of type $lut. Using template $paramod$58be4e12578fd01a63b5512aa5e6a001c3ac42a2\$lut for cells of type $lut. Using template $paramod$e942ff15257dd44eb70ae034d1b665e0116c7a3e\$lut for cells of type $lut. Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut. Using template $paramod$1ca23e17bf41dc1e9eab64b373f9322defa25a58\$lut for cells of type $lut. Using template $paramod$eeea089431e54644147af2c573dc3d2eca0e3b09\$lut for cells of type $lut. Using template $paramod$d883e135b7bd8ae4385e869b4ab8d5786e0934a2\$lut for cells of type $lut. Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut. Using template $paramod$9e45b1a8f5d89c07bcbb75a2bb1c598231b04feb\$lut for cells of type $lut. Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut. Using template $paramod$ee553c574ab2f916d3d8d85eaa3629c01709dc3a\$lut for cells of type $lut. Using template $paramod$be279b3a95441f5ed77959a762fd1c3c8028198d\$lut for cells of type $lut. Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$b841ccd1766b01569d845c10e311fed95a228c35\$lut for cells of type $lut. Using template $paramod$77ed94d25522a46d367009dcebfa94565acb988b\$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod$9a0a4ac3a18cad01c0b8afa834643d9a4aa4ee38\$lut for cells of type $lut. Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut. Using template $paramod$6c22e4c9acd607e1249c5e3017b6703f378da140\$lut for cells of type $lut. Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c\$lut for cells of type $lut. Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut. Using template $paramod$c97e738df958f490eb8461efe944668c310ecac5\$lut for cells of type $lut. Using template $paramod$b009a26b33c3ca109c016cf968a774c0d66687bb\$lut for cells of type $lut. Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$47fa2f84639cacb9dd6b3d20220476702f4e2512\$lut for cells of type $lut. Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut. Using template $paramod$d1f4d3b01d6c5239c86e099ce5737b85dacd1ead\$lut for cells of type $lut. Using template $paramod$f7cbd8f5974233f70d25c33ef6a692898e4f6377\$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376\$lut for cells of type $lut. Using template $paramod$7c6931fb6ae8373449e3a500171e63118fc1cfe9\$lut for cells of type $lut. Using template $paramod$2ae580aa7529a928cd91377c6f024790bebcdf88\$lut for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut. Using template $paramod$df929792afd0bebf101a124ee890c12e0fed6a8d\$lut for cells of type $lut. Using template $paramod$1194b3a751797ffd33921d63424430e7f1ad2a46\$lut for cells of type $lut. Using template $paramod$5cd6342b8b1615f2ee34e81b2e8af9c6ecb251a6\$lut for cells of type $lut. Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. Using template $paramod$55ac124d6496496a64c6f2c29f5ac412a62ef57d\$lut for cells of type $lut. Using template $paramod$de273d25f15c0e35d4108e94f7e3bd92c2e83118\$lut for cells of type $lut. Using template $paramod$eaacf9809ed87d6f801a5466f6f5f3d660730e88\$lut for cells of type $lut. Using template $paramod$cbb05871f4afe56f5e8cac75dcb47d9aef2c28af\$lut for cells of type $lut. Using template $paramod$40f504af2bc5239b38b7cba52aa63a585f9e751d\$lut for cells of type $lut. Using template $paramod$4e09fb85ad5980549134c5674f63e37de31e60bc\$lut for cells of type $lut. Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca\$lut for cells of type $lut. Using template $paramod$115b33a94acd0d35393b7ffd17f6f80c031f9c76\$lut for cells of type $lut. Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$bfeabb867bd04e7effc04f34074b9c8e66901d92\$lut for cells of type $lut. Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut. Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5\$lut for cells of type $lut. No more expansions possible. <suppressed ~26598 debug messages> 34.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830770.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830382.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4570_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$32663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$30877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$auto$rtlil.cc:2771:And$8237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$29010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$24649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831840.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$27006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14841.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15820.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$15838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$15924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$15934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$16455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$17764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$17990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$17997.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$18025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$18109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$18516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$19375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$19924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$20771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$20908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$21268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$21968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$22901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23257.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$23806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4621_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$auto$rtlil.cc:2771:And$8237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$24710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$24962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$24966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$24984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$25579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$25835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$26348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$26674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$26734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$26768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$27172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$27388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$27724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$27962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$auto$opt_dff.cc:219:make_patterns_logic$6636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$24859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$29010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$29169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$29372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$29755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$auto$fsm_map.cc:170:map_fsm$5595[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831733.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$30631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$30818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$30959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$30994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$31248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$31323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$31366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$31526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$31712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$31733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$31857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$32312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$32444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$32615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$32615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$32816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$32970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$33100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$33462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$33660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$33692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$33977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$33993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$34730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$35269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$35470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$35583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$35672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$35865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$35981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$36366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$36519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$36827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$36901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$37035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$37138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$37427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$37607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$37803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$37932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$37969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$38008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$38265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$38298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$38685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$38685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$38796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$38815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$38942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$39045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$39173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$39173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$39519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$39526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$39950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$39984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$40158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$40310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$40414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$40676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$40975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$41093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$41502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$41967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$42047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$42360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$42360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$42573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$42737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$42737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$18472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$42992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$43473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$43752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$43937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$44823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$44851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$44977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$45110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$45406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$45539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$45828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$46264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$46301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$46324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46583.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$46697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$46864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$46975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$47254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$47485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$47490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$47646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$47811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$48174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$48441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$48989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$49066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$49140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$49413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$49413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$49784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$49971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$49997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$50174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$50418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$50432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$50523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$50550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$59335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$auto$fsm_map.cc:170:map_fsm$5595[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$auto$fsm_map.cc:170:map_fsm$5595[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$47646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$48989.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$14773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$auto$opt_dff.cc:219:make_patterns_logic$6476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$auto$rtlil.cc:2771:And$8237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$29057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$28926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$auto$opt_dff.cc:219:make_patterns_logic$5909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$25599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$28184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$aiger830346$30671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$31182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$34181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\First_Stage.$procmux$4263_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Fourth_Stage.$ternary$/var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/rtl/core/MEMWB.sv:47$557_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$0\take_jalr_o[0:0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$48459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831947.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$33710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4524_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3528_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.\Mdu.$procmux$4570_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.address[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$50336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Third_Stage.$procmux$4695_Y[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$flatten\Processor.\N1.\Second_Stage.$procmux$3522_Y[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$auto$opt_dff.cc:219:make_patterns_logic$5925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.address[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut\Controller.Memory.write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$14877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830710.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831158.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830374.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$830978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$46207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$45539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$44334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$43063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$42262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$41461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$40326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$39306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$830347$lut$aiger830346$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$37745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$36306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$35367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$34730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$31370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831782.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$28645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$28712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$16051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$830347$lut$aiger830346$16020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831912.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$830347$lut$aiger830346$15828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831935.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$831999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 40216 unused wires. 34.45. Executing AUTONAME pass. Renamed 3843499 objects in module processorci_top (529 iterations). <suppressed ~43024 debug messages> 34.46. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `processorci_top'. Setting top module to processorci_top. 34.46.1. Analyzing design hierarchy.. Top module: \processorci_top 34.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 34.47. Printing statistics. === processorci_top === Number of wires: 16817 Number of wire bits: 54981 Number of public wires: 16817 Number of public wire bits: 54981 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 27870 $scopeinfo 32 CCU2C 526 DP16KD 1 L6MUX21 506 LUT4 18831 MULT18X18D 4 PFUMX 2628 TRELLIS_DPR16X4 1058 TRELLIS_FF 4284 34.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 34.49. Executing JSON backend. Warnings: 69 unique messages, 69 total End of script. Logfile hash: ae57b83796, CPU: user 92.13s system 0.57s, MEM: 1078.88 MB peak Time spent: 34% 1x abc9_exe (32 sec), 14% 1x autoname (13 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Grande-Risco-5 -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [=== ] 5.03% Loading: [====== ] 10.06% Loading: [======== ] 15.09% Loading: [=========== ] 20.12% Loading: [============= ] 25.14% Loading: [================ ] 30.17% Loading: [================== ] 35.20% Loading: [===================== ] 40.23% Loading: [======================= ] 45.26% Loading: [========================== ] 50.29% Loading: [============================ ] 55.32% Loading: [=============================== ] 60.35% Loading: [================================= ] 65.37% Loading: [==================================== ] 70.40% Loading: [====================================== ] 75.43% Loading: [========================================= ] 80.46% Loading: [=========================================== ] 85.49% Loading: [============================================== ] 90.52% Loading: [================================================ ] 95.55% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/Grande-Risco-5/Grande-Risco-5 [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 9f408ee2-3fb2-4849-83c9-6c7ae7fcd6a6 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: No test report files were found. Configuration error? Finished: FAILURE