#! /eda/oss-cad-suite/bin/vvp :ivl_version "13.0 (devel)" "(s20250103-25-g99580cd05)"; :ivl_delay_selection "TYPICAL"; :vpi_time_precision - 12; :vpi_module "/eda/oss-cad-suite/lib/ivl/system.vpi"; :vpi_module "/eda/oss-cad-suite/lib/ivl/vhdl_sys.vpi"; :vpi_module "/eda/oss-cad-suite/lib/ivl/vhdl_textio.vpi"; :vpi_module "/eda/oss-cad-suite/lib/ivl/v2005_math.vpi"; :vpi_module "/eda/oss-cad-suite/lib/ivl/va_math.vpi"; S_0x55556fbc8600 .scope module, "rv_core" "rv_core" 2 17; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rstn"; L_0x55556fbae8f0 .functor AND 1, L_0x55556fbe66d0, L_0x55556fbf9400, C4<1>, C4<1>; L_0x55556fbae0f0 .functor AND 1, L_0x55556fbae8f0, L_0x55556fbe69a0, C4<1>, C4<1>; L_0x55556fbad8f0 .functor AND 1, L_0x55556fbe6cd0, L_0x55556fbf9400, C4<1>, C4<1>; L_0x55556fa9eb70 .functor AND 1, L_0x55556fbad8f0, L_0x55556fbe6fe0, C4<1>, C4<1>; v0x55556fbe1370_0 .var "EX_MEM_ctrl_reg", 4 0; v0x55556fbe1470_0 .var "EX_MEM_reg", 159 0; v0x55556fbe1550_0 .var "EX_PC_src", 0 0; v0x55556fbe15f0_0 .net "EX_PC_target", 63 0, L_0x55556fbe7790; 1 drivers v0x55556fbe16d0_0 .net "EX_alu1_src", 1 0, L_0x55556fbe7d00; 1 drivers v0x55556fbe17b0_0 .net "EX_alu2_src", 0 0, L_0x55556fbe7c30; 1 drivers v0x55556fbe1870_0 .net "EX_alu_op1", 63 0, L_0x55556fbf85e0; 1 drivers v0x55556fbe1930_0 .var "EX_alu_op1_fw", 63 0; v0x55556fbe19f0_0 .net "EX_alu_op2", 63 0, L_0x55556fbf87c0; 1 drivers v0x55556fbe1ab0_0 .var "EX_alu_op2_fw", 63 0; v0x55556fbe1b70_0 .net "EX_alu_op_32b", 0 0, v0x55556fb05c00_0; 1 drivers v0x55556fbe1c10_0 .net "EX_alu_op_sel", 3 0, v0x55556fb05cc0_0; 1 drivers v0x55556fbe1d20_0 .net "EX_alu_result", 63 0, L_0x55556fbfcf40; 1 drivers v0x55556fbe1e30_0 .net "EX_branch", 0 0, L_0x55556fbe7ac0; 1 drivers v0x55556fbe1f20_0 .net "EX_branch_taken", 0 0, v0x55556fbd48e0_0; 1 drivers v0x55556fbe2010_0 .net "EX_forward_A", 1 0, v0x55556fbd9b10_0; 1 drivers v0x55556fbe20d0_0 .net "EX_forward_B", 1 0, v0x55556fbd9bf0_0; 1 drivers v0x55556fbe2170_0 .net "EX_imm_expand", 63 0, L_0x55556fbe8000; 1 drivers v0x55556fbe2230_0 .net "EX_instr_part", 3 0, L_0x55556fbf8cd0; 1 drivers v0x55556fbe22f0_0 .net "EX_jal", 0 0, L_0x55556fbe7b90; 1 drivers v0x55556fbe2390_0 .net "EX_jalr", 0 0, L_0x55556fbe7ea0; 1 drivers v0x55556fbe2430_0 .net "EX_rf_rd_data1", 63 0, L_0x55556fbe7830; 1 drivers v0x55556fbe24d0_0 .net "EX_rf_rd_data2", 63 0, L_0x55556fbe79f0; 1 drivers v0x55556fbe2590_0 .var "ID_EX_ctrl_reg", 9 0; v0x55556fbe2670_0 .var "ID_EX_reg", 351 0; v0x55556fbe2750_0 .var "ID_PC_target", 63 0; v0x55556fbe2830_0 .var "ID_alu1_src", 1 0; v0x55556fbe2910_0 .net "ID_alu1_src_b", 1 0, v0x55556fbd4f40_0; 1 drivers v0x55556fbe29d0_0 .var "ID_alu2_src", 0 0; v0x55556fbe2a70_0 .net "ID_alu2_src_b", 0 0, v0x55556fbd5040_0; 1 drivers v0x55556fbe2b40_0 .var "ID_branch", 0 0; v0x55556fbe2be0_0 .net "ID_branch_b", 0 0, v0x55556fbd5100_0; 1 drivers v0x55556fbe2cd0_0 .net "ID_ctrl_write", 0 0, v0x55556fbda880_0; 1 drivers v0x55556fbe2d70_0 .net "ID_imm_expand", 63 0, v0x55556fbdaf80_0; 1 drivers v0x55556fbe2e40_0 .var "ID_jal", 0 0; v0x55556fbe2ee0_0 .net "ID_jal_b", 0 0, v0x55556fbd51a0_0; 1 drivers v0x55556fbe2fb0_0 .var "ID_jalr", 0 0; v0x55556fbe3050_0 .net "ID_jalr_b", 0 0, v0x55556fbd5240_0; 1 drivers v0x55556fbe3120_0 .var "ID_mem_read", 0 0; v0x55556fbe31c0_0 .net "ID_mem_read_b", 0 0, v0x55556fbd5330_0; 1 drivers v0x55556fbe3290_0 .var "ID_mem_to_reg", 0 0; v0x55556fbe3330_0 .net "ID_mem_to_reg_b", 0 0, v0x55556fbd53f0_0; 1 drivers v0x55556fbe3400_0 .var "ID_mem_write", 0 0; v0x55556fbe34a0_0 .net "ID_mem_write_b", 0 0, v0x55556fbd54b0_0; 1 drivers v0x55556fbe3570_0 .net "ID_reg_read_b", 1 0, v0x55556fbd56e0_0; 1 drivers v0x55556fbe3640_0 .var "ID_reg_write", 0 0; v0x55556fbe36e0_0 .net "ID_reg_write_b", 0 0, v0x55556fbd57c0_0; 1 drivers v0x55556fbe37b0_0 .net "ID_rf_forward", 1 0, L_0x55556fbe6be0; 1 drivers v0x55556fbe3870_0 .net "ID_rf_rd_data1", 63 0, v0x55556fbde810_0; 1 drivers v0x55556fbe3960_0 .net "ID_rf_rd_data2", 63 0, v0x55556fbde8d0_0; 1 drivers v0x55556fbe3a30_0 .var "IF_ID_reg", 95 0; v0x55556fbe3af0_0 .net "IF_ID_write", 0 0, v0x55556fbda660_0; 1 drivers v0x55556fbe3bc0_0 .net "IF_PC_write", 0 0, v0x55556fbda720_0; 1 drivers v0x55556fbe3c90_0 .net "IF_flush", 0 0, v0x55556fb4b560_0; 1 drivers v0x55556fbe3d60_0 .net "IF_predict", 0 0, v0x55556fb4b620_0; 1 drivers v0x55556fbe3e30_0 .var "IF_predict_r", 0 0; v0x55556fbe3ed0_0 .var "MEM_WB_ctrl_reg", 1 0; v0x55556fbe3f70_0 .var "MEM_WB_reg", 159 0; v0x55556fbe4030_0 .net "MEM_addr_map", 63 0, L_0x55556fbff4f0; 1 drivers v0x55556fbe4140_0 .net "MEM_alu_result", 63 0, L_0x55556fbf9100; 1 drivers v0x55556fbe4200_0 .net "MEM_mem_dout", 63 0, L_0x55556fbfd7e0; 1 drivers v0x55556fbe42a0_0 .net "MEM_mem_dout_map", 63 0, v0x55556fbde010_0; 1 drivers v0x55556fbe4390_0 .net "MEM_mem_read", 0 0, L_0x55556fbf8e60; 1 drivers v0x55556fbe4480_0 .net "MEM_mem_write", 0 0, L_0x55556fbf9010; 1 drivers v0x55556fbe4570_0 .net "MEM_strobe", 7 0, v0x55556fbde0f0_0; 1 drivers v0x55556fbe4a20_0 .var "PC", 63 0; v0x55556fbe4ae0_0 .net "PC_EX", 63 0, L_0x55556fbe7620; 1 drivers v0x55556fbe4ba0_0 .net "PC_ID", 63 0, L_0x55556fbe7240; 1 drivers v0x55556fbe4c80_0 .net "WB_alu_result", 63 0, L_0x55556fbf98e0; 1 drivers v0x55556fbe4d60_0 .net "WB_mem_dout", 63 0, L_0x55556fbf9700; 1 drivers v0x55556fbe4e40_0 .net "WB_mem_to_reg", 0 0, L_0x55556fbf9660; 1 drivers v0x55556fbe4f00_0 .net "WB_reg_write", 0 0, L_0x55556fbf9400; 1 drivers v0x55556fbe4fa0_0 .net "WB_rf_wr_data", 63 0, L_0x55556fbf99d0; 1 drivers v0x55556fbe5070_0 .net *"_ivl_10", 0 0, L_0x55556fbe69a0; 1 drivers v0x55556fbe5110_0 .net *"_ivl_12", 0 0, L_0x55556fbae0f0; 1 drivers v0x55556fbe51f0_0 .net *"_ivl_18", 0 0, L_0x55556fbe6cd0; 1 drivers v0x55556fbe52d0_0 .net *"_ivl_19", 0 0, L_0x55556fbad8f0; 1 drivers v0x55556fbe53b0_0 .net *"_ivl_22", 4 0, L_0x55556fbe6e00; 1 drivers v0x55556fbe5490_0 .net *"_ivl_24", 4 0, L_0x55556fbe6ea0; 1 drivers v0x55556fbe5570_0 .net *"_ivl_25", 0 0, L_0x55556fbe6fe0; 1 drivers v0x55556fbe5630_0 .net *"_ivl_27", 0 0, L_0x55556fa9eb70; 1 drivers v0x55556fbe5710_0 .net *"_ivl_3", 0 0, L_0x55556fbe66d0; 1 drivers v0x55556fbe57f0_0 .net *"_ivl_34", 32 0, L_0x55556fbe7470; 1 drivers v0x55556fbe58d0_0 .net *"_ivl_4", 0 0, L_0x55556fbae8f0; 1 drivers v0x55556fbe59b0_0 .net *"_ivl_58", 0 0, L_0x55556fbe80a0; 1 drivers v0x55556fbe5a90_0 .net *"_ivl_60", 0 0, L_0x55556fbe8260; 1 drivers L_0x7f6f44a7d018 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; v0x55556fbe5b70_0 .net/2u *"_ivl_61", 63 0, L_0x7f6f44a7d018; 1 drivers v0x55556fbe5c50_0 .net *"_ivl_63", 63 0, L_0x55556fbf8390; 1 drivers v0x55556fbe5d30_0 .net *"_ivl_7", 4 0, L_0x55556fbe6810; 1 drivers v0x55556fbe5e10_0 .net *"_ivl_70", 0 0, L_0x55556fbf8a40; 1 drivers v0x55556fbe5ef0_0 .net *"_ivl_72", 2 0, L_0x55556fbf8b30; 1 drivers v0x55556fbe5fd0_0 .net *"_ivl_9", 4 0, L_0x55556fbe6900; 1 drivers o0x7f6f44ac68b8 .functor BUFZ 1, c4; HiZ drive v0x55556fbe60b0_0 .net "clk", 0 0, o0x7f6f44ac68b8; 0 drivers v0x55556fbe6150_0 .net "instr_EX", 31 0, L_0x55556fbe7580; 1 drivers v0x55556fbe6230_0 .net "instr_ID", 31 0, L_0x55556fbe7340; 1 drivers v0x55556fbe6320_0 .net "instr_IF", 31 0, L_0x55556fbff6d0; 1 drivers v0x55556fbe6410_0 .net "instr_MEM", 31 0, L_0x55556fbf9310; 1 drivers v0x55556fbe64f0_0 .net "instr_WB", 31 0, L_0x55556fbf9d00; 1 drivers o0x7f6f44ac6918 .functor BUFZ 1, c4; HiZ drive v0x55556fbe65d0_0 .net "rstn", 0 0, o0x7f6f44ac6918; 0 drivers E_0x55556fb41860 .event anyedge, v0x55556fb18400_0, v0x55556fb184a0_0, v0x55556fb18340_0, v0x55556fb18560_0; E_0x55556fb416d0 .event anyedge, v0x55556fbd9bf0_0, v0x55556fbe24d0_0, v0x55556fbddc60_0, v0x55556fbdf230_0; E_0x55556fb41c60 .event anyedge, v0x55556fbd9b10_0, v0x55556fbe2430_0, v0x55556fbddc60_0, v0x55556fbdf230_0; E_0x55556fa38ca0/0 .event anyedge, v0x55556fbe2e40_0, v0x55556fbe4ba0_0, v0x55556fbdaf80_0, v0x55556fbe2fb0_0; E_0x55556fa38ca0/1 .event anyedge, v0x55556fbde810_0; E_0x55556fa38ca0 .event/or E_0x55556fa38ca0/0, E_0x55556fa38ca0/1; E_0x55556fbd3680/0 .event anyedge, v0x55556fbda880_0, v0x55556fb4b4a0_0, v0x55556fbd5330_0, v0x55556fbd53f0_0; E_0x55556fbd3680/1 .event anyedge, v0x55556fbd54b0_0, v0x55556fbd4f40_0, v0x55556fbd5040_0, v0x55556fbd57c0_0; E_0x55556fbd3680/2 .event anyedge, v0x55556fbd51a0_0, v0x55556fbd5240_0; E_0x55556fbd3680 .event/or E_0x55556fbd3680/0, E_0x55556fbd3680/1, E_0x55556fbd3680/2; L_0x55556fbe66d0 .part v0x55556fbd56e0_0, 0, 1; L_0x55556fbe6810 .part L_0x55556fbe7340, 15, 5; L_0x55556fbe6900 .part L_0x55556fbf9d00, 7, 5; L_0x55556fbe69a0 .cmp/eq 5, L_0x55556fbe6810, L_0x55556fbe6900; L_0x55556fbe6be0 .concat8 [ 1 1 0 0], L_0x55556fbae0f0, L_0x55556fa9eb70; L_0x55556fbe6cd0 .part v0x55556fbd56e0_0, 1, 1; L_0x55556fbe6e00 .part L_0x55556fbe7340, 20, 5; L_0x55556fbe6ea0 .part L_0x55556fbf9d00, 7, 5; L_0x55556fbe6fe0 .cmp/eq 5, L_0x55556fbe6e00, L_0x55556fbe6ea0; L_0x55556fbe7240 .part v0x55556fbe3a30_0, 32, 64; L_0x55556fbe7340 .part v0x55556fbe3a30_0, 0, 32; L_0x55556fbe7470 .part v0x55556fbe2670_0, 64, 33; L_0x55556fbe7580 .part L_0x55556fbe7470, 0, 32; L_0x55556fbe7620 .part v0x55556fbe2670_0, 224, 64; L_0x55556fbe7790 .part v0x55556fbe2670_0, 288, 64; L_0x55556fbe7830 .part v0x55556fbe2670_0, 96, 64; L_0x55556fbe79f0 .part v0x55556fbe2670_0, 160, 64; L_0x55556fbe7ac0 .part v0x55556fbe2590_0, 2, 1; L_0x55556fbe7c30 .part v0x55556fbe2590_0, 5, 1; L_0x55556fbe7d00 .part v0x55556fbe2590_0, 6, 2; L_0x55556fbe7b90 .part v0x55556fbe2590_0, 8, 1; L_0x55556fbe7ea0 .part v0x55556fbe2590_0, 9, 1; L_0x55556fbe8000 .part v0x55556fbe2670_0, 0, 64; L_0x55556fbe80a0 .part L_0x55556fbe7d00, 1, 1; L_0x55556fbe8260 .part L_0x55556fbe7d00, 0, 1; L_0x55556fbf8390 .functor MUXZ 64, v0x55556fbe1930_0, L_0x7f6f44a7d018, L_0x55556fbe8260, C4<>; L_0x55556fbf85e0 .functor MUXZ 64, L_0x55556fbf8390, L_0x55556fbe7620, L_0x55556fbe80a0, C4<>; L_0x55556fbf87c0 .functor MUXZ 64, v0x55556fbe1ab0_0, L_0x55556fbe8000, L_0x55556fbe7c30, C4<>; L_0x55556fbf8a40 .part L_0x55556fbe7580, 30, 1; L_0x55556fbf8b30 .part L_0x55556fbe7580, 12, 3; L_0x55556fbf8cd0 .concat [ 3 1 0 0], L_0x55556fbf8b30, L_0x55556fbf8a40; L_0x55556fbf8e60 .part v0x55556fbe1370_0, 3, 1; L_0x55556fbf9010 .part v0x55556fbe1370_0, 4, 1; L_0x55556fbf9100 .part v0x55556fbe1470_0, 0, 64; L_0x55556fbf9310 .part v0x55556fbe1470_0, 128, 32; L_0x55556fbf9400 .part v0x55556fbe3ed0_0, 0, 1; L_0x55556fbf9660 .part v0x55556fbe3ed0_0, 1, 1; L_0x55556fbf9700 .part v0x55556fbe3f70_0, 0, 64; L_0x55556fbf98e0 .part v0x55556fbe3f70_0, 64, 64; L_0x55556fbf99d0 .functor MUXZ 64, L_0x55556fbf98e0, L_0x55556fbf9700, L_0x55556fbf9660, C4<>; L_0x55556fbf9d00 .part v0x55556fbe3f70_0, 128, 32; L_0x55556fbfa110 .part v0x55556fbe3a30_0, 0, 7; L_0x55556fbfb280 .part v0x55556fbe3a30_0, 15, 5; L_0x55556fbfc4d0 .part v0x55556fbe3a30_0, 20, 5; L_0x55556fbfc710 .part L_0x55556fbf9d00, 7, 5; L_0x55556fbfc970 .part v0x55556fbe3a30_0, 0, 32; L_0x55556fbfd1d0 .part L_0x55556fbe7580, 12, 3; L_0x55556fbfd300 .part L_0x55556fbe7580, 0, 7; L_0x55556fbfdb70 .part v0x55556fbe1470_0, 64, 64; L_0x55556fbfdf80 .part L_0x55556fbe7580, 0, 7; L_0x55556fbfe1c0 .part L_0x55556fbe7580, 15, 5; L_0x55556fbfe260 .part L_0x55556fbe7580, 20, 5; L_0x55556fbfe4b0 .part v0x55556fbe1370_0, 0, 1; L_0x55556fbfe550 .part L_0x55556fbf9310, 7, 5; L_0x55556fbfe830 .part v0x55556fbe3ed0_0, 0, 1; L_0x55556fbfe8d0 .part L_0x55556fbf9d00, 7, 5; L_0x55556fbfed10 .part v0x55556fbe2590_0, 3, 1; L_0x55556fbfede0 .part L_0x55556fbe7580, 7, 5; L_0x55556fbff090 .part L_0x55556fbe7580, 8, 4; L_0x55556fbff160 .part L_0x55556fbe7340, 8, 4; L_0x55556fbff630 .part L_0x55556fbf9310, 12, 3; S_0x55556fbb5ee0 .scope module, "u_alu" "rv_alu" 2 358, 3 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 64 "op1_i"; .port_info 1 /INPUT 64 "op2_i"; .port_info 2 /INPUT 4 "op_sel_i"; .port_info 3 /INPUT 1 "op_32b_i"; .port_info 4 /OUTPUT 64 "result_o"; v0x55556fbaf9d0_0 .net *"_ivl_1", 0 0, L_0x55556fbfcb90; 1 drivers v0x55556fbaf1b0_0 .net *"_ivl_3", 31 0, L_0x55556fbfcc60; 1 drivers v0x55556fbae9c0_0 .net *"_ivl_5", 31 0, L_0x55556fbfcd30; 1 drivers v0x55556fbae1c0_0 .net *"_ivl_6", 63 0, L_0x55556fbfcdd0; 1 drivers v0x55556fbad9c0_0 .net "op1_i", 63 0, L_0x55556fbf85e0; alias, 1 drivers v0x55556fb80190_0 .net "op2_i", 63 0, L_0x55556fbf87c0; alias, 1 drivers v0x55556fb804c0_0 .net "op_32b_i", 0 0, v0x55556fb05c00_0; alias, 1 drivers v0x55556fafe1c0_0 .net "op_sel_i", 3 0, v0x55556fb05cc0_0; alias, 1 drivers v0x55556fafe2a0_0 .var "result", 63 0; v0x55556fafe380_0 .net "result_o", 63 0, L_0x55556fbfcf40; alias, 1 drivers E_0x55556fbd3b00 .event anyedge, v0x55556fb80190_0, v0x55556fbad9c0_0, v0x55556fafe1c0_0; L_0x55556fbfcb90 .part v0x55556fafe2a0_0, 31, 1; L_0x55556fbfcc60 .repeat 32, 32, L_0x55556fbfcb90; L_0x55556fbfcd30 .part v0x55556fafe2a0_0, 0, 32; L_0x55556fbfcdd0 .concat [ 32 32 0 0], L_0x55556fbfcd30, L_0x55556fbfcc60; L_0x55556fbfcf40 .functor MUXZ 64, v0x55556fafe2a0_0, L_0x55556fbfcdd0, v0x55556fb05c00_0, C4<>; S_0x55556fb059f0 .scope module, "u_alu_ctrl" "rv_alu_ctrl" 2 372, 4 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 7 "opcode_i"; .port_info 1 /INPUT 4 "instr_part_i"; .port_info 2 /OUTPUT 4 "alu_op_sel_o"; .port_info 3 /OUTPUT 1 "alu_op_32b_o"; v0x55556fb05c00_0 .var "alu_op_32b_o", 0 0; v0x55556fb05cc0_0 .var "alu_op_sel_o", 3 0; v0x55556fb05d60_0 .net "instr_part_i", 3 0, L_0x55556fbf8cd0; alias, 1 drivers v0x55556fb05e00_0 .net "opcode_i", 6 0, L_0x55556fbfd300; 1 drivers E_0x55556fb05ba0 .event anyedge, v0x55556fb05d60_0, v0x55556fb05e00_0; S_0x55556fb079e0 .scope module, "u_branch_predict" "rv_branch_predict" 2 413, 5 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rstn"; .port_info 2 /INPUT 1 "ID_branch_i"; .port_info 3 /INPUT 1 "EX_branch_i"; .port_info 4 /INPUT 1 "EX_taken_i"; .port_info 5 /INPUT 1 "EX_jal_i"; .port_info 6 /INPUT 1 "EX_jalr_i"; .port_info 7 /INPUT 4 "EX_addr_i"; .port_info 8 /INPUT 4 "ID_addr_i"; .port_info 9 /OUTPUT 1 "IF_flush_o"; .port_info 10 /OUTPUT 1 "IF_predict_o"; v0x55556fb18240_0 .net "EX_addr_i", 3 0, L_0x55556fbff090; 1 drivers v0x55556fb18340_0 .net "EX_branch_i", 0 0, L_0x55556fbe7ac0; alias, 1 drivers v0x55556fb18400_0 .net "EX_jal_i", 0 0, L_0x55556fbe7b90; alias, 1 drivers v0x55556fb184a0_0 .net "EX_jalr_i", 0 0, L_0x55556fbe7ea0; alias, 1 drivers v0x55556fb18560_0 .net "EX_taken_i", 0 0, v0x55556fbd48e0_0; alias, 1 drivers v0x55556fb18620_0 .net "ID_addr_i", 3 0, L_0x55556fbff160; 1 drivers v0x55556fb4b4a0_0 .net "ID_branch_i", 0 0, v0x55556fbd5100_0; alias, 1 drivers v0x55556fb4b560_0 .var "IF_flush_o", 0 0; v0x55556fb4b620_0 .var "IF_predict_o", 0 0; v0x55556fb4b6e0 .array "bpb", 0 15, 1 0; v0x55556fb401c0_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fb40280_0 .var/i "i", 31 0; v0x55556fb40360_0 .net "rstn", 0 0, o0x7f6f44ac6918; alias, 0 drivers v0x55556fb4b6e0_0 .array/port v0x55556fb4b6e0, 0; v0x55556fb4b6e0_1 .array/port v0x55556fb4b6e0, 1; E_0x55556fb07ce0/0 .event anyedge, v0x55556fb4b4a0_0, v0x55556fb18620_0, v0x55556fb4b6e0_0, v0x55556fb4b6e0_1; v0x55556fb4b6e0_2 .array/port v0x55556fb4b6e0, 2; v0x55556fb4b6e0_3 .array/port v0x55556fb4b6e0, 3; v0x55556fb4b6e0_4 .array/port v0x55556fb4b6e0, 4; v0x55556fb4b6e0_5 .array/port v0x55556fb4b6e0, 5; E_0x55556fb07ce0/1 .event anyedge, v0x55556fb4b6e0_2, v0x55556fb4b6e0_3, v0x55556fb4b6e0_4, v0x55556fb4b6e0_5; v0x55556fb4b6e0_6 .array/port v0x55556fb4b6e0, 6; v0x55556fb4b6e0_7 .array/port v0x55556fb4b6e0, 7; v0x55556fb4b6e0_8 .array/port v0x55556fb4b6e0, 8; v0x55556fb4b6e0_9 .array/port v0x55556fb4b6e0, 9; E_0x55556fb07ce0/2 .event anyedge, v0x55556fb4b6e0_6, v0x55556fb4b6e0_7, v0x55556fb4b6e0_8, v0x55556fb4b6e0_9; v0x55556fb4b6e0_10 .array/port v0x55556fb4b6e0, 10; v0x55556fb4b6e0_11 .array/port v0x55556fb4b6e0, 11; v0x55556fb4b6e0_12 .array/port v0x55556fb4b6e0, 12; v0x55556fb4b6e0_13 .array/port v0x55556fb4b6e0, 13; E_0x55556fb07ce0/3 .event anyedge, v0x55556fb4b6e0_10, v0x55556fb4b6e0_11, v0x55556fb4b6e0_12, v0x55556fb4b6e0_13; v0x55556fb4b6e0_14 .array/port v0x55556fb4b6e0, 14; v0x55556fb4b6e0_15 .array/port v0x55556fb4b6e0, 15; E_0x55556fb07ce0/4 .event anyedge, v0x55556fb4b6e0_14, v0x55556fb4b6e0_15; E_0x55556fb07ce0 .event/or E_0x55556fb07ce0/0, E_0x55556fb07ce0/1, E_0x55556fb07ce0/2, E_0x55556fb07ce0/3, E_0x55556fb07ce0/4; E_0x55556fb07dc0/0 .event anyedge, v0x55556fb18340_0, v0x55556fb18560_0, v0x55556fb18240_0, v0x55556fb4b6e0_0; E_0x55556fb07dc0/1 .event anyedge, v0x55556fb4b6e0_1, v0x55556fb4b6e0_2, v0x55556fb4b6e0_3, v0x55556fb4b6e0_4; E_0x55556fb07dc0/2 .event anyedge, v0x55556fb4b6e0_5, v0x55556fb4b6e0_6, v0x55556fb4b6e0_7, v0x55556fb4b6e0_8; E_0x55556fb07dc0/3 .event anyedge, v0x55556fb4b6e0_9, v0x55556fb4b6e0_10, v0x55556fb4b6e0_11, v0x55556fb4b6e0_12; E_0x55556fb07dc0/4 .event anyedge, v0x55556fb4b6e0_13, v0x55556fb4b6e0_14, v0x55556fb4b6e0_15, v0x55556fb18400_0; E_0x55556fb07dc0/5 .event anyedge, v0x55556fb184a0_0; E_0x55556fb07dc0 .event/or E_0x55556fb07dc0/0, E_0x55556fb07dc0/1, E_0x55556fb07dc0/2, E_0x55556fb07dc0/3, E_0x55556fb07dc0/4, E_0x55556fb07dc0/5; E_0x55556fafe5a0/0 .event negedge, v0x55556fb40360_0; E_0x55556fafe5a0/1 .event posedge, v0x55556fb401c0_0; E_0x55556fafe5a0 .event/or E_0x55556fafe5a0/0, E_0x55556fafe5a0/1; S_0x55556fbd4480 .scope module, "u_branch_test" "rv_branch_test" 2 366, 6 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 64 "alu_result_i"; .port_info 1 /INPUT 3 "funct3_i"; .port_info 2 /OUTPUT 1 "taken_o"; L_0x55556fbfd160 .functor NOT 1, L_0x55556fbfd030, C4<0>, C4<0>, C4<0>; v0x55556fbd4670_0 .net *"_ivl_1", 0 0, L_0x55556fbfd030; 1 drivers v0x55556fbd4750_0 .net "alu_result_i", 63 0, L_0x55556fbfcf40; alias, 1 drivers v0x55556fbd4810_0 .net "funct3_i", 2 0, L_0x55556fbfd1d0; 1 drivers v0x55556fbd48e0_0 .var "taken_o", 0 0; v0x55556fbd49b0_0 .net "zero", 0 0, L_0x55556fbfd160; 1 drivers E_0x55556fbd4610 .event anyedge, v0x55556fafe380_0, v0x55556fbd4810_0; L_0x55556fbfd030 .reduce/or L_0x55556fbfcf40; S_0x55556fbd4b20 .scope module, "u_ctrl" "rv_ctrl" 2 326, 7 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "rstn"; .port_info 1 /INPUT 7 "opcode_i"; .port_info 2 /OUTPUT 1 "branch_o"; .port_info 3 /OUTPUT 1 "mem_read_o"; .port_info 4 /OUTPUT 1 "mem_to_reg_o"; .port_info 5 /OUTPUT 1 "mem_write_o"; .port_info 6 /OUTPUT 2 "alu1_src_o"; .port_info 7 /OUTPUT 1 "alu2_src_o"; .port_info 8 /OUTPUT 2 "reg_read_o"; .port_info 9 /OUTPUT 1 "reg_write_o"; .port_info 10 /OUTPUT 1 "jal_o"; .port_info 11 /OUTPUT 1 "jalr_o"; v0x55556fbd4f40_0 .var "alu1_src_o", 1 0; v0x55556fbd5040_0 .var "alu2_src_o", 0 0; v0x55556fbd5100_0 .var "branch_o", 0 0; v0x55556fbd51a0_0 .var "jal_o", 0 0; v0x55556fbd5240_0 .var "jalr_o", 0 0; v0x55556fbd5330_0 .var "mem_read_o", 0 0; v0x55556fbd53f0_0 .var "mem_to_reg_o", 0 0; v0x55556fbd54b0_0 .var "mem_write_o", 0 0; v0x55556fbd5570_0 .net "opcode_i", 6 0, L_0x55556fbfa110; 1 drivers v0x55556fbd56e0_0 .var "reg_read_o", 1 0; v0x55556fbd57c0_0 .var "reg_write_o", 0 0; v0x55556fbd5880_0 .net "rstn", 0 0, o0x7f6f44ac6918; alias, 0 drivers E_0x55556fbd4ee0/0 .event anyedge, v0x55556fbd5570_0; E_0x55556fbd4ee0/1 .event negedge, v0x55556fb40360_0; E_0x55556fbd4ee0 .event/or E_0x55556fbd4ee0/0, E_0x55556fbd4ee0/1; S_0x55556fbd5a80 .scope module, "u_data_mem" "rv_data_mem" 2 379, 8 20 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 64 "addr_i"; .port_info 2 /INPUT 1 "wr_en_i"; .port_info 3 /INPUT 8 "wr_strobe_i"; .port_info 4 /INPUT 64 "wr_data_i"; .port_info 5 /INPUT 1 "rd_en_i"; .port_info 6 /OUTPUT 64 "rd_data_o"; v0x55556fbd88a0_0 .net "addr_i", 63 0, L_0x55556fbff4f0; alias, 1 drivers v0x55556fbd89a0_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fbd8a60_0 .net "rd_data_o", 63 0, L_0x55556fbfd7e0; alias, 1 drivers v0x55556fbd8b30_0 .net "rd_en_i", 0 0, L_0x55556fbf8e60; alias, 1 drivers v0x55556fbd8c00_0 .net "wr_data_i", 63 0, L_0x55556fbfdb70; 1 drivers v0x55556fbd8cf0_0 .net "wr_en_i", 0 0, L_0x55556fbf9010; alias, 1 drivers v0x55556fbd8dc0_0 .net "wr_strobe_i", 7 0, v0x55556fbde0f0_0; alias, 1 drivers L_0x55556fbfd9a0 .part L_0x55556fbff4f0, 0, 12; L_0x55556fbfda40 .part L_0x55556fbff4f0, 0, 12; S_0x55556fbd5d40 .scope module, "u_data_dpram" "rv_dpram" 8 35, 9 17 0, S_0x55556fbd5a80; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "wena"; .port_info 2 /INPUT 8 "strobe"; .port_info 3 /INPUT 12 "addra"; .port_info 4 /INPUT 64 "dina"; .port_info 5 /INPUT 1 "renb"; .port_info 6 /INPUT 12 "addrb"; .port_info 7 /OUTPUT 64 "doutb"; P_0x55556fbd5f40 .param/l "DEPTH" 0 9 19, +C4<00000000000000000001000000000000>; P_0x55556fbd5f80 .param/l "WIDTH" 0 9 18, +C4<00000000000000000000000001000000>; v0x55556fbd7c40 .array "BRAM", 0 4095, 63 0; v0x55556fbd7d00_0 .net *"_ivl_0", 63 0, L_0x55556fbfd530; 1 drivers v0x55556fbd7de0_0 .net *"_ivl_2", 13 0, L_0x55556fbfd630; 1 drivers L_0x7f6f44a7d210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; v0x55556fbd7ea0_0 .net *"_ivl_5", 1 0, L_0x7f6f44a7d210; 1 drivers L_0x7f6f44a7d258 .functor BUFT 1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; v0x55556fbd7f80_0 .net/2u *"_ivl_6", 63 0, L_0x7f6f44a7d258; 1 drivers v0x55556fbd80b0_0 .net "addra", 11 0, L_0x55556fbfd9a0; 1 drivers v0x55556fbd8190_0 .net "addrb", 11 0, L_0x55556fbfda40; 1 drivers v0x55556fbd8270_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fbd8310_0 .net "dina", 63 0, L_0x55556fbfdb70; alias, 1 drivers v0x55556fbd8460_0 .net "doutb", 63 0, L_0x55556fbfd7e0; alias, 1 drivers v0x55556fbd8540_0 .net "renb", 0 0, L_0x55556fbf8e60; alias, 1 drivers v0x55556fbd8600_0 .net "strobe", 7 0, v0x55556fbde0f0_0; alias, 1 drivers v0x55556fbd86e0_0 .net "wena", 0 0, L_0x55556fbf9010; alias, 1 drivers L_0x55556fbfd530 .array/port v0x55556fbd7c40, L_0x55556fbfd630; L_0x55556fbfd630 .concat [ 12 2 0 0], L_0x55556fbfda40, L_0x7f6f44a7d210; L_0x55556fbfd7e0 .functor MUXZ 64, L_0x7f6f44a7d258, L_0x55556fbfd530, L_0x55556fbf8e60, C4<>; S_0x55556fbd61b0 .scope function.vec4.u32, "clog2" "clog2" 9 70, 9 70 0, S_0x55556fbd5d40; .timescale -9 -12; ; Variable clog2 is vec4 return value of scope S_0x55556fbd61b0 v0x55556fbd64b0_0 .var/i "depth", 31 0; TD_rv_core.u_data_mem.u_data_dpram.clog2 ; %load/vec4 v0x55556fbd64b0_0; %subi 1, 0, 32; %store/vec4 v0x55556fbd64b0_0, 0, 32; %pushi/vec4 0, 0, 32; %ret/vec4 0, 0, 32; Assign to clog2 (store_vec4_to_lval) T_0.0 ; Top of for-loop %load/vec4 v0x55556fbd64b0_0; %cmpi/s 0, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_0.1, 5; %load/vec4 v0x55556fbd64b0_0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; %shiftr 4; %store/vec4 v0x55556fbd64b0_0, 0, 32; T_0.2 ; for-loop step statement %retload/vec4 0; Load clog2 (draw_signal_vec4) %addi 1, 0, 32; %ret/vec4 0, 0, 32; Assign to clog2 (store_vec4_to_lval) %jmp T_0.0; T_0.1 ; for-loop exit label %end; S_0x55556fbd6590 .scope generate, "genblk1[0]" "genblk1[0]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd67b0 .param/l "i" 1 9 55, +C4<00>; E_0x55556fbd6870 .event posedge, v0x55556fb401c0_0; S_0x55556fbd68d0 .scope generate, "genblk1[1]" "genblk1[1]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd6b00 .param/l "i" 1 9 55, +C4<01>; S_0x55556fbd6bc0 .scope generate, "genblk1[2]" "genblk1[2]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd6da0 .param/l "i" 1 9 55, +C4<010>; S_0x55556fbd6e80 .scope generate, "genblk1[3]" "genblk1[3]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd70b0 .param/l "i" 1 9 55, +C4<011>; S_0x55556fbd7190 .scope generate, "genblk1[4]" "genblk1[4]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd7370 .param/l "i" 1 9 55, +C4<0100>; S_0x55556fbd7450 .scope generate, "genblk1[5]" "genblk1[5]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd7630 .param/l "i" 1 9 55, +C4<0101>; S_0x55556fbd7710 .scope generate, "genblk1[6]" "genblk1[6]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd78f0 .param/l "i" 1 9 55, +C4<0110>; S_0x55556fbd79d0 .scope generate, "genblk1[7]" "genblk1[7]" 9 55, 9 55 0, S_0x55556fbd5d40; .timescale -9 -12; P_0x55556fbd7060 .param/l "i" 1 9 55, +C4<0111>; S_0x55556fbd8f30 .scope module, "u_forward" "rv_forward" 2 389, 10 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 7 "opcode_i"; .port_info 1 /INPUT 5 "EX_rs1_i"; .port_info 2 /INPUT 5 "EX_rs2_i"; .port_info 3 /INPUT 1 "MEM_reg_write_i"; .port_info 4 /INPUT 5 "MEM_rd_i"; .port_info 5 /INPUT 1 "WB_reg_write_i"; .port_info 6 /INPUT 5 "WB_rd_i"; .port_info 7 /OUTPUT 2 "forward_A_o"; .port_info 8 /OUTPUT 2 "forward_B_o"; L_0x55556fbfde70 .functor OR 1, L_0x55556fbfdc10, L_0x55556fbfdd00, C4<0>, C4<0>; v0x55556fbd91c0_0 .net "EX_rs1_i", 4 0, L_0x55556fbfe1c0; 1 drivers v0x55556fbd92c0_0 .net "EX_rs2_i", 4 0, L_0x55556fbfe260; 1 drivers v0x55556fbd93a0_0 .net "MEM_rd_i", 4 0, L_0x55556fbfe550; 1 drivers v0x55556fbd9490_0 .net "MEM_reg_write_i", 0 0, L_0x55556fbfe4b0; 1 drivers v0x55556fbd9550_0 .net "WB_rd_i", 4 0, L_0x55556fbfe8d0; 1 drivers v0x55556fbd9680_0 .net "WB_reg_write_i", 0 0, L_0x55556fbfe830; 1 drivers L_0x7f6f44a7d2a0 .functor BUFT 1, C4<0010011>, C4<0>, C4<0>, C4<0>; v0x55556fbd9740_0 .net/2u *"_ivl_0", 6 0, L_0x7f6f44a7d2a0; 1 drivers v0x55556fbd9820_0 .net *"_ivl_2", 0 0, L_0x55556fbfdc10; 1 drivers L_0x7f6f44a7d2e8 .functor BUFT 1, C4<0000011>, C4<0>, C4<0>, C4<0>; v0x55556fbd98e0_0 .net/2u *"_ivl_4", 6 0, L_0x7f6f44a7d2e8; 1 drivers v0x55556fbd9a50_0 .net *"_ivl_6", 0 0, L_0x55556fbfdd00; 1 drivers v0x55556fbd9b10_0 .var "forward_A_o", 1 0; v0x55556fbd9bf0_0 .var "forward_B_o", 1 0; v0x55556fbd9cd0_0 .net "opcode_i", 6 0, L_0x55556fbfdf80; 1 drivers v0x55556fbd9db0_0 .net "type_I", 0 0, L_0x55556fbfde70; 1 drivers E_0x55556fbd5c10/0 .event anyedge, v0x55556fbd9490_0, v0x55556fbd93a0_0, v0x55556fbd91c0_0, v0x55556fbd9680_0; E_0x55556fbd5c10/1 .event anyedge, v0x55556fbd9550_0, v0x55556fbd92c0_0, v0x55556fbd9db0_0; E_0x55556fbd5c10 .event/or E_0x55556fbd5c10/0, E_0x55556fbd5c10/1; L_0x55556fbfdc10 .cmp/eq 7, L_0x55556fbfdf80, L_0x7f6f44a7d2a0; L_0x55556fbfdd00 .cmp/eq 7, L_0x55556fbfdf80, L_0x7f6f44a7d2e8; S_0x55556fbd9f90 .scope module, "u_hzd_detect" "rv_hzd_detect" 2 401, 11 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rstn"; .port_info 2 /INPUT 1 "EX_mem_read_i"; .port_info 3 /INPUT 5 "EX_reg_rd_i"; .port_info 4 /INPUT 1 "EX_branch_i"; .port_info 5 /INPUT 32 "instr_i"; .port_info 6 /OUTPUT 1 "PC_write_o"; .port_info 7 /OUTPUT 1 "IF_ID_write_o"; .port_info 8 /OUTPUT 1 "ctrl_write_o"; v0x55556fbda200_0 .net "EX_branch_i", 0 0, L_0x55556fbe7ac0; alias, 1 drivers v0x55556fbda2c0_0 .net "EX_mem_read_i", 0 0, L_0x55556fbfed10; 1 drivers v0x55556fbda360_0 .net "EX_reg_rd_i", 4 0, L_0x55556fbfede0; 1 drivers v0x55556fbda450_0 .net "ID_reg_rs1", 4 0, L_0x55556fbfeb70; 1 drivers v0x55556fbda530_0 .net "ID_reg_rs2", 4 0, L_0x55556fbfec40; 1 drivers v0x55556fbda660_0 .var "IF_ID_write_o", 0 0; v0x55556fbda720_0 .var "PC_write_o", 0 0; v0x55556fbda7e0_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fbda880_0 .var "ctrl_write_o", 0 0; v0x55556fbda9d0_0 .net "instr_i", 31 0, L_0x55556fbe7340; alias, 1 drivers v0x55556fbdaab0_0 .net "rstn", 0 0, o0x7f6f44ac6918; alias, 0 drivers E_0x55556fbda170/0 .event anyedge, v0x55556fbda2c0_0, v0x55556fbda360_0, v0x55556fbda450_0, v0x55556fbda530_0; E_0x55556fbda170/1 .event anyedge, v0x55556fb18340_0; E_0x55556fbda170 .event/or E_0x55556fbda170/0, E_0x55556fbda170/1; L_0x55556fbfeb70 .part L_0x55556fbe7340, 15, 5; L_0x55556fbfec40 .part L_0x55556fbe7340, 20, 5; S_0x55556fbdacc0 .scope module, "u_imm_gen" "rv_imm_gen" 2 353, 12 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 32 "instr_i"; .port_info 1 /OUTPUT 64 "expand_o"; v0x55556fbdaf80_0 .var "expand_o", 63 0; v0x55556fbdb080_0 .net "funct3", 2 0, L_0x55556fbfc870; 1 drivers v0x55556fbdb160_0 .net "instr_i", 31 0, L_0x55556fbfc970; 1 drivers E_0x55556fbdaf00 .event anyedge, v0x55556fbdb160_0; L_0x55556fbfc870 .part L_0x55556fbfc970, 12, 3; S_0x55556fbdb280 .scope module, "u_instr_mem" "rv_instr_mem" 2 320, 13 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 64 "pc_i"; .port_info 2 /OUTPUT 32 "instr_o"; v0x55556fbdd4b0_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fbdd570_0 .net "instr_o", 31 0, L_0x55556fbff6d0; alias, 1 drivers v0x55556fbdd630_0 .net "pc_i", 63 0, v0x55556fbe4a20_0; 1 drivers L_0x55556fbf9fd0 .part v0x55556fbe4a20_0, 2, 8; S_0x55556fbdb460 .scope module, "u_instr_dpram" "rv_dpram" 13 29, 9 17 0, S_0x55556fbdb280; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "wena"; .port_info 2 /INPUT 4 "strobe"; .port_info 3 /INPUT 8 "addra"; .port_info 4 /INPUT 32 "dina"; .port_info 5 /INPUT 1 "renb"; .port_info 6 /INPUT 8 "addrb"; .port_info 7 /OUTPUT 32 "doutb"; P_0x55556fbdb660 .param/l "DEPTH" 0 9 19, +C4<00000000000000000000000100000000>; P_0x55556fbdb6a0 .param/l "WIDTH" 0 9 18, +C4<00000000000000000000000000100000>; L_0x55556fbff6d0 .functor BUFT 32, L_0x55556fbf9da0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; v0x55556fbdc910 .array "BRAM", 0 255, 31 0; v0x55556fbdc9d0_0 .net *"_ivl_0", 31 0, L_0x55556fbf9da0; 1 drivers v0x55556fbdcab0_0 .net *"_ivl_2", 9 0, L_0x55556fbf9e40; 1 drivers L_0x7f6f44a7d060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; v0x55556fbdcb70_0 .net *"_ivl_5", 1 0, L_0x7f6f44a7d060; 1 drivers L_0x7f6f44a7d138 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; v0x55556fbdcc50_0 .net "addra", 7 0, L_0x7f6f44a7d138; 1 drivers v0x55556fbdcd80_0 .net "addrb", 7 0, L_0x55556fbf9fd0; 1 drivers v0x55556fbdce60_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers L_0x7f6f44a7d180 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; v0x55556fbdcf00_0 .net "dina", 31 0, L_0x7f6f44a7d180; 1 drivers v0x55556fbdcfe0_0 .net "doutb", 31 0, L_0x55556fbff6d0; alias, 1 drivers L_0x7f6f44a7d1c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; v0x55556fbdd150_0 .net "renb", 0 0, L_0x7f6f44a7d1c8; 1 drivers L_0x7f6f44a7d0f0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; v0x55556fbdd210_0 .net "strobe", 3 0, L_0x7f6f44a7d0f0; 1 drivers L_0x7f6f44a7d0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; v0x55556fbdd2f0_0 .net "wena", 0 0, L_0x7f6f44a7d0a8; 1 drivers L_0x55556fbf9da0 .array/port v0x55556fbdc910, L_0x55556fbf9e40; L_0x55556fbf9e40 .concat [ 8 2 0 0], L_0x55556fbf9fd0, L_0x7f6f44a7d060; S_0x55556fbdb9b0 .scope function.vec4.u32, "clog2" "clog2" 9 70, 9 70 0, S_0x55556fbdb460; .timescale -9 -12; ; Variable clog2 is vec4 return value of scope S_0x55556fbdb9b0 v0x55556fbdbcb0_0 .var/i "depth", 31 0; TD_rv_core.u_instr_mem.u_instr_dpram.clog2 ; %load/vec4 v0x55556fbdbcb0_0; %subi 1, 0, 32; %store/vec4 v0x55556fbdbcb0_0, 0, 32; %pushi/vec4 0, 0, 32; %ret/vec4 0, 0, 32; Assign to clog2 (store_vec4_to_lval) T_1.3 ; Top of for-loop %load/vec4 v0x55556fbdbcb0_0; %cmpi/s 0, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_1.4, 5; %load/vec4 v0x55556fbdbcb0_0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; %shiftr 4; %store/vec4 v0x55556fbdbcb0_0, 0, 32; T_1.5 ; for-loop step statement %retload/vec4 0; Load clog2 (draw_signal_vec4) %addi 1, 0, 32; %ret/vec4 0, 0, 32; Assign to clog2 (store_vec4_to_lval) %jmp T_1.3; T_1.4 ; for-loop exit label %end; S_0x55556fbdbd90 .scope generate, "genblk1[0]" "genblk1[0]" 9 55, 9 55 0, S_0x55556fbdb460; .timescale -9 -12; P_0x55556fbdbfb0 .param/l "i" 1 9 55, +C4<00>; S_0x55556fbdc070 .scope generate, "genblk1[1]" "genblk1[1]" 9 55, 9 55 0, S_0x55556fbdb460; .timescale -9 -12; P_0x55556fbdc280 .param/l "i" 1 9 55, +C4<01>; S_0x55556fbdc340 .scope generate, "genblk1[2]" "genblk1[2]" 9 55, 9 55 0, S_0x55556fbdb460; .timescale -9 -12; P_0x55556fbdc520 .param/l "i" 1 9 55, +C4<010>; S_0x55556fbdc600 .scope generate, "genblk1[3]" "genblk1[3]" 9 55, 9 55 0, S_0x55556fbdb460; .timescale -9 -12; P_0x55556fbdc830 .param/l "i" 1 9 55, +C4<011>; S_0x55556fbdd780 .scope module, "u_mem_map" "rv_mem_map" 2 427, 14 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 3 "funct3_i"; .port_info 1 /INPUT 64 "addr_i"; .port_info 2 /INPUT 64 "rd_data_i"; .port_info 3 /OUTPUT 64 "addr_map_o"; .port_info 4 /OUTPUT 8 "wr_strobe_o"; .port_info 5 /OUTPUT 64 "rd_data_map_o"; L_0x7f6f44a7d330 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; v0x55556fbdda80_0 .net/2u *"_ivl_0", 2 0, L_0x7f6f44a7d330; 1 drivers v0x55556fbddb80_0 .net *"_ivl_3", 60 0, L_0x55556fbff420; 1 drivers v0x55556fbddc60_0 .net "addr_i", 63 0, L_0x55556fbf9100; alias, 1 drivers v0x55556fbddd50_0 .net "addr_map_o", 63 0, L_0x55556fbff4f0; alias, 1 drivers v0x55556fbdde40_0 .net "funct3_i", 2 0, L_0x55556fbff630; 1 drivers v0x55556fbddf00_0 .net "rd_data_i", 63 0, L_0x55556fbfd7e0; alias, 1 drivers v0x55556fbde010_0 .var "rd_data_map_o", 63 0; v0x55556fbde0f0_0 .var "wr_strobe_o", 7 0; E_0x55556fbdda20 .event anyedge, v0x55556fbdde40_0, v0x55556fbddc60_0, v0x55556fbd8460_0; L_0x55556fbff420 .part L_0x55556fbf9100, 3, 61; L_0x55556fbff4f0 .concat [ 61 3 0 0], L_0x55556fbff420, L_0x7f6f44a7d330; S_0x55556fbde300 .scope module, "u_rf" "rv_rf" 2 341, 15 18 0, S_0x55556fbc8600; .timescale -9 -12; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rstn"; .port_info 2 /INPUT 5 "rd_reg1_i"; .port_info 3 /INPUT 5 "rd_reg2_i"; .port_info 4 /INPUT 5 "wr_reg_i"; .port_info 5 /INPUT 64 "wr_data_i"; .port_info 6 /INPUT 1 "wr_en_i"; .port_info 7 /OUTPUT 64 "rd_data1_o"; .port_info 8 /OUTPUT 64 "rd_data2_o"; v0x55556fbdebc0_0 .array/port v0x55556fbdebc0, 0; L_0x55556fbe7510 .functor BUFZ 64, v0x55556fbdebc0_0, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_1 .array/port v0x55556fbdebc0, 1; L_0x55556fbfa310 .functor BUFZ 64, v0x55556fbdebc0_1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_2 .array/port v0x55556fbdebc0, 2; L_0x55556fbfa380 .functor BUFZ 64, v0x55556fbdebc0_2, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_3 .array/port v0x55556fbdebc0, 3; L_0x55556fbfa450 .functor BUFZ 64, v0x55556fbdebc0_3, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_4 .array/port v0x55556fbdebc0, 4; L_0x55556fbfa550 .functor BUFZ 64, v0x55556fbdebc0_4, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_5 .array/port v0x55556fbdebc0, 5; L_0x55556fbfa620 .functor BUFZ 64, v0x55556fbdebc0_5, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_6 .array/port v0x55556fbdebc0, 6; L_0x55556fbfa730 .functor BUFZ 64, v0x55556fbdebc0_6, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_7 .array/port v0x55556fbdebc0, 7; L_0x55556fbfa7d0 .functor BUFZ 64, v0x55556fbdebc0_7, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_8 .array/port v0x55556fbdebc0, 8; L_0x55556fbfa8f0 .functor BUFZ 64, v0x55556fbdebc0_8, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_9 .array/port v0x55556fbdebc0, 9; L_0x55556fbfa9c0 .functor BUFZ 64, v0x55556fbdebc0_9, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_10 .array/port v0x55556fbdebc0, 10; L_0x55556fbfaaf0 .functor BUFZ 64, v0x55556fbdebc0_10, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_11 .array/port v0x55556fbdebc0, 11; L_0x55556fbfabc0 .functor BUFZ 64, v0x55556fbdebc0_11, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_12 .array/port v0x55556fbdebc0, 12; L_0x55556fbfad00 .functor BUFZ 64, v0x55556fbdebc0_12, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_13 .array/port v0x55556fbdebc0, 13; L_0x55556fbfadd0 .functor BUFZ 64, v0x55556fbdebc0_13, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_14 .array/port v0x55556fbdebc0, 14; L_0x55556fbfac90 .functor BUFZ 64, v0x55556fbdebc0_14, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_15 .array/port v0x55556fbdebc0, 15; L_0x55556fbfaf80 .functor BUFZ 64, v0x55556fbdebc0_15, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_16 .array/port v0x55556fbdebc0, 16; L_0x55556fbfb0e0 .functor BUFZ 64, v0x55556fbdebc0_16, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_17 .array/port v0x55556fbdebc0, 17; L_0x55556fbfb1b0 .functor BUFZ 64, v0x55556fbdebc0_17, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_18 .array/port v0x55556fbdebc0, 18; L_0x55556fbfb320 .functor BUFZ 64, v0x55556fbdebc0_18, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_19 .array/port v0x55556fbdebc0, 19; L_0x55556fbfb3f0 .functor BUFZ 64, v0x55556fbdebc0_19, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_20 .array/port v0x55556fbdebc0, 20; L_0x55556fbfb570 .functor BUFZ 64, v0x55556fbdebc0_20, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_21 .array/port v0x55556fbdebc0, 21; L_0x55556fbfb640 .functor BUFZ 64, v0x55556fbdebc0_21, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_22 .array/port v0x55556fbdebc0, 22; L_0x55556fbfb7d0 .functor BUFZ 64, v0x55556fbdebc0_22, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_23 .array/port v0x55556fbdebc0, 23; L_0x55556fbfb8a0 .functor BUFZ 64, v0x55556fbdebc0_23, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_24 .array/port v0x55556fbdebc0, 24; L_0x55556fbfba40 .functor BUFZ 64, v0x55556fbdebc0_24, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_25 .array/port v0x55556fbdebc0, 25; L_0x55556fbfbb10 .functor BUFZ 64, v0x55556fbdebc0_25, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_26 .array/port v0x55556fbdebc0, 26; L_0x55556fbfbcc0 .functor BUFZ 64, v0x55556fbdebc0_26, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_27 .array/port v0x55556fbdebc0, 27; L_0x55556fbfbd90 .functor BUFZ 64, v0x55556fbdebc0_27, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_28 .array/port v0x55556fbdebc0, 28; L_0x55556fbfbf50 .functor BUFZ 64, v0x55556fbdebc0_28, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_29 .array/port v0x55556fbdebc0, 29; L_0x55556fbfc020 .functor BUFZ 64, v0x55556fbdebc0_29, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_30 .array/port v0x55556fbdebc0, 30; L_0x55556fbfc1f0 .functor BUFZ 64, v0x55556fbdebc0_30, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbdebc0_31 .array/port v0x55556fbdebc0, 31; L_0x55556fbfc2c0 .functor BUFZ 64, v0x55556fbdebc0_31, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; v0x55556fbde670_0 .net "clk", 0 0, o0x7f6f44ac68b8; alias, 0 drivers v0x55556fbde730_0 .var/i "i", 31 0; v0x55556fbde810_0 .var "rd_data1_o", 63 0; v0x55556fbde8d0_0 .var "rd_data2_o", 63 0; v0x55556fbde9b0_0 .net "rd_reg1_i", 4 0, L_0x55556fbfb280; 1 drivers v0x55556fbdeae0_0 .net "rd_reg2_i", 4 0, L_0x55556fbfc4d0; 1 drivers v0x55556fbdebc0 .array "reg_x", 0 31, 63 0; v0x55556fbdf190_0 .net "rstn", 0 0, o0x7f6f44ac6918; alias, 0 drivers v0x55556fbdf230_0 .net "wr_data_i", 63 0, L_0x55556fbf99d0; alias, 1 drivers v0x55556fbdf3a0_0 .net "wr_en_i", 0 0, L_0x55556fbf9400; alias, 1 drivers v0x55556fbdf460_0 .net "wr_reg_i", 4 0, L_0x55556fbfc710; 1 drivers v0x55556fbdf540_0 .net "x0", 63 0, L_0x55556fbe7510; 1 drivers v0x55556fbdf620_0 .net "x1", 63 0, L_0x55556fbfa310; 1 drivers v0x55556fbdf700_0 .net "x10", 63 0, L_0x55556fbfaaf0; 1 drivers v0x55556fbdf7e0_0 .net "x11", 63 0, L_0x55556fbfabc0; 1 drivers v0x55556fbdf8c0_0 .net "x12", 63 0, L_0x55556fbfad00; 1 drivers v0x55556fbdf9a0_0 .net "x13", 63 0, L_0x55556fbfadd0; 1 drivers v0x55556fbdfb90_0 .net "x14", 63 0, L_0x55556fbfac90; 1 drivers v0x55556fbdfc70_0 .net "x15", 63 0, L_0x55556fbfaf80; 1 drivers v0x55556fbdfd50_0 .net "x16", 63 0, L_0x55556fbfb0e0; 1 drivers v0x55556fbdfe30_0 .net "x17", 63 0, L_0x55556fbfb1b0; 1 drivers v0x55556fbdff10_0 .net "x18", 63 0, L_0x55556fbfb320; 1 drivers v0x55556fbdfff0_0 .net "x19", 63 0, L_0x55556fbfb3f0; 1 drivers v0x55556fbe00d0_0 .net "x2", 63 0, L_0x55556fbfa380; 1 drivers v0x55556fbe01b0_0 .net "x20", 63 0, L_0x55556fbfb570; 1 drivers v0x55556fbe0290_0 .net "x21", 63 0, L_0x55556fbfb640; 1 drivers v0x55556fbe0370_0 .net "x22", 63 0, L_0x55556fbfb7d0; 1 drivers v0x55556fbe0450_0 .net "x23", 63 0, L_0x55556fbfb8a0; 1 drivers v0x55556fbe0530_0 .net "x24", 63 0, L_0x55556fbfba40; 1 drivers v0x55556fbe0610_0 .net "x25", 63 0, L_0x55556fbfbb10; 1 drivers v0x55556fbe06f0_0 .net "x26", 63 0, L_0x55556fbfbcc0; 1 drivers v0x55556fbe07d0_0 .net "x27", 63 0, L_0x55556fbfbd90; 1 drivers v0x55556fbe08b0_0 .net "x28", 63 0, L_0x55556fbfbf50; 1 drivers v0x55556fbe0990_0 .net "x29", 63 0, L_0x55556fbfc020; 1 drivers v0x55556fbe0a70_0 .net "x3", 63 0, L_0x55556fbfa450; 1 drivers v0x55556fbe0b50_0 .net "x30", 63 0, L_0x55556fbfc1f0; 1 drivers v0x55556fbe0c30_0 .net "x31", 63 0, L_0x55556fbfc2c0; 1 drivers v0x55556fbe0d10_0 .net "x4", 63 0, L_0x55556fbfa550; 1 drivers v0x55556fbe0df0_0 .net "x5", 63 0, L_0x55556fbfa620; 1 drivers v0x55556fbe0ed0_0 .net "x6", 63 0, L_0x55556fbfa730; 1 drivers v0x55556fbe0fb0_0 .net "x7", 63 0, L_0x55556fbfa7d0; 1 drivers v0x55556fbe1090_0 .net "x8", 63 0, L_0x55556fbfa8f0; 1 drivers v0x55556fbe1170_0 .net "x9", 63 0, L_0x55556fbfa9c0; 1 drivers E_0x55556fbdd910/0 .event anyedge, v0x55556fbde9b0_0, v0x55556fbdebc0_0, v0x55556fbdebc0_1, v0x55556fbdebc0_2; E_0x55556fbdd910/1 .event anyedge, v0x55556fbdebc0_3, v0x55556fbdebc0_4, v0x55556fbdebc0_5, v0x55556fbdebc0_6; E_0x55556fbdd910/2 .event anyedge, v0x55556fbdebc0_7, v0x55556fbdebc0_8, v0x55556fbdebc0_9, v0x55556fbdebc0_10; E_0x55556fbdd910/3 .event anyedge, v0x55556fbdebc0_11, v0x55556fbdebc0_12, v0x55556fbdebc0_13, v0x55556fbdebc0_14; E_0x55556fbdd910/4 .event anyedge, v0x55556fbdebc0_15, v0x55556fbdebc0_16, v0x55556fbdebc0_17, v0x55556fbdebc0_18; E_0x55556fbdd910/5 .event anyedge, v0x55556fbdebc0_19, v0x55556fbdebc0_20, v0x55556fbdebc0_21, v0x55556fbdebc0_22; E_0x55556fbdd910/6 .event anyedge, v0x55556fbdebc0_23, v0x55556fbdebc0_24, v0x55556fbdebc0_25, v0x55556fbdebc0_26; E_0x55556fbdd910/7 .event anyedge, v0x55556fbdebc0_27, v0x55556fbdebc0_28, v0x55556fbdebc0_29, v0x55556fbdebc0_30; E_0x55556fbdd910/8 .event anyedge, v0x55556fbdebc0_31, v0x55556fbdeae0_0; E_0x55556fbdd910 .event/or E_0x55556fbdd910/0, E_0x55556fbdd910/1, E_0x55556fbdd910/2, E_0x55556fbdd910/3, E_0x55556fbdd910/4, E_0x55556fbdd910/5, E_0x55556fbdd910/6, E_0x55556fbdd910/7, E_0x55556fbdd910/8; .scope S_0x55556fbdbd90; T_2 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbdd2f0_0; %flag_set/vec4 8; %jmp/0xz T_2.0, 8; %load/vec4 v0x55556fbdd210_0; %parti/s 1, 0, 2; %flag_set/vec4 8; %jmp/0xz T_2.2, 8; %load/vec4 v0x55556fbdcf00_0; %parti/s 8, 0, 2; %load/vec4 v0x55556fbdcc50_0; %pad/u 10; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdc910, 0, 4; T_2.2 ; T_2.0 ; %jmp T_2; .thread T_2; .scope S_0x55556fbdc070; T_3 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbdd2f0_0; %flag_set/vec4 8; %jmp/0xz T_3.0, 8; %load/vec4 v0x55556fbdd210_0; %parti/s 1, 1, 2; %flag_set/vec4 8; %jmp/0xz T_3.2, 8; %load/vec4 v0x55556fbdcf00_0; %parti/s 8, 8, 5; %load/vec4 v0x55556fbdcc50_0; %pad/u 10; %ix/vec4 3; %ix/load 4, 8, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdc910, 4, 5; T_3.2 ; T_3.0 ; %jmp T_3; .thread T_3; .scope S_0x55556fbdc340; T_4 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbdd2f0_0; %flag_set/vec4 8; %jmp/0xz T_4.0, 8; %load/vec4 v0x55556fbdd210_0; %parti/s 1, 2, 3; %flag_set/vec4 8; %jmp/0xz T_4.2, 8; %load/vec4 v0x55556fbdcf00_0; %parti/s 8, 16, 6; %load/vec4 v0x55556fbdcc50_0; %pad/u 10; %ix/vec4 3; %ix/load 4, 16, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdc910, 4, 5; T_4.2 ; T_4.0 ; %jmp T_4; .thread T_4; .scope S_0x55556fbdc600; T_5 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbdd2f0_0; %flag_set/vec4 8; %jmp/0xz T_5.0, 8; %load/vec4 v0x55556fbdd210_0; %parti/s 1, 3, 3; %flag_set/vec4 8; %jmp/0xz T_5.2, 8; %load/vec4 v0x55556fbdcf00_0; %parti/s 8, 24, 6; %load/vec4 v0x55556fbdcc50_0; %pad/u 10; %ix/vec4 3; %ix/load 4, 24, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdc910, 4, 5; T_5.2 ; T_5.0 ; %jmp T_5; .thread T_5; .scope S_0x55556fbd4b20; T_6 ; %wait E_0x55556fbd4ee0; %load/vec4 v0x55556fbd5880_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.1; T_6.0 ; %load/vec4 v0x55556fbd5570_0; %dup/vec4; %pushi/vec4 51, 0, 7; %cmp/u; %jmp/1 T_6.2, 6; %dup/vec4; %pushi/vec4 59, 0, 7; %cmp/u; %jmp/1 T_6.3, 6; %dup/vec4; %pushi/vec4 19, 0, 7; %cmp/u; %jmp/1 T_6.4, 6; %dup/vec4; %pushi/vec4 27, 0, 7; %cmp/u; %jmp/1 T_6.5, 6; %dup/vec4; %pushi/vec4 3, 0, 7; %cmp/u; %jmp/1 T_6.6, 6; %dup/vec4; %pushi/vec4 35, 0, 7; %cmp/u; %jmp/1 T_6.7, 6; %dup/vec4; %pushi/vec4 99, 0, 7; %cmp/u; %jmp/1 T_6.8, 6; %dup/vec4; %pushi/vec4 111, 0, 7; %cmp/u; %jmp/1 T_6.9, 6; %dup/vec4; %pushi/vec4 55, 0, 7; %cmp/u; %jmp/1 T_6.10, 6; %dup/vec4; %pushi/vec4 23, 0, 7; %cmp/u; %jmp/1 T_6.11, 6; %dup/vec4; %pushi/vec4 103, 0, 7; %cmp/u; %jmp/1 T_6.12, 6; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.2 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 3, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.3 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 3, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.4 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.5 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.6 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.7 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 3, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.8 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 3, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.9 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 2, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.10 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.11 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 2, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.12 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5100_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd5330_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd53f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd54b0_0, 0; %pushi/vec4 2, 0, 2; %assign/vec4 v0x55556fbd4f40_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5040_0, 0; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd56e0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd57c0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd51a0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbd5240_0, 0; %jmp T_6.14; T_6.14 ; %pop/vec4 1; T_6.1 ; %jmp T_6; .thread T_6; .scope S_0x55556fbde300; T_7 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbdf3a0_0; %flag_set/vec4 8; %jmp/0xz T_7.0, 8; %load/vec4 v0x55556fbdf460_0; %pad/u 32; %cmpi/ne 0, 0, 32; %jmp/0xz T_7.2, 4; %load/vec4 v0x55556fbdf230_0; %load/vec4 v0x55556fbdf460_0; %pad/u 7; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdebc0, 0, 4; T_7.2 ; T_7.0 ; %jmp T_7; .thread T_7; .scope S_0x55556fbde300; T_8 ; %wait E_0x55556fbdd910; %load/vec4 v0x55556fbde9b0_0; %pad/u 7; %ix/vec4 4; %load/vec4a v0x55556fbdebc0, 4; %assign/vec4 v0x55556fbde810_0, 0; %load/vec4 v0x55556fbdeae0_0; %pad/u 7; %ix/vec4 4; %load/vec4a v0x55556fbdebc0, 4; %assign/vec4 v0x55556fbde8d0_0, 0; %jmp T_8; .thread T_8, $push; .scope S_0x55556fbde300; T_9 ; %pushi/vec4 0, 0, 32; %store/vec4 v0x55556fbde730_0, 0, 32; T_9.0 ; Top of for-loop %load/vec4 v0x55556fbde730_0; %cmpi/s 32, 0, 32; %jmp/0xz T_9.1, 5; %pushi/vec4 0, 0, 64; %ix/getv/s 3, v0x55556fbde730_0; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbdebc0, 0, 4; T_9.2 ; for-loop step statement %load/vec4 v0x55556fbde730_0; %addi 1, 0, 32; %store/vec4 v0x55556fbde730_0, 0, 32; %jmp T_9.0; T_9.1 ; for-loop exit label %end; .thread T_9; .scope S_0x55556fbdacc0; T_10 ; %wait E_0x55556fbdaf00; %load/vec4 v0x55556fbdb160_0; %parti/s 7, 0, 2; %dup/vec4; %pushi/vec4 3, 0, 7; %cmp/u; %jmp/1 T_10.0, 6; %dup/vec4; %pushi/vec4 19, 0, 7; %cmp/u; %jmp/1 T_10.1, 6; %dup/vec4; %pushi/vec4 27, 0, 7; %cmp/u; %jmp/1 T_10.2, 6; %dup/vec4; %pushi/vec4 103, 0, 7; %cmp/u; %jmp/1 T_10.3, 6; %dup/vec4; %pushi/vec4 35, 0, 7; %cmp/u; %jmp/1 T_10.4, 6; %dup/vec4; %pushi/vec4 99, 0, 7; %cmp/u; %jmp/1 T_10.5, 6; %dup/vec4; %pushi/vec4 55, 0, 7; %cmp/u; %jmp/1 T_10.6, 6; %dup/vec4; %pushi/vec4 23, 0, 7; %cmp/u; %jmp/1 T_10.7, 6; %dup/vec4; %pushi/vec4 111, 0, 7; %cmp/u; %jmp/1 T_10.8, 6; %pushi/vec4 0, 0, 64; %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.0 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 12, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.1 ; %load/vec4 v0x55556fbdb080_0; %parti/s 2, 0, 2; %cmpi/e 1, 0, 2; %jmp/0xz T_10.11, 4; %pushi/vec4 0, 0, 58; %load/vec4 v0x55556fbdb160_0; %parti/s 6, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.12; T_10.11 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 12, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; T_10.12 ; %jmp T_10.10; T_10.2 ; %load/vec4 v0x55556fbdb080_0; %parti/s 2, 0, 2; %cmpi/e 1, 0, 2; %jmp/0xz T_10.13, 4; %pushi/vec4 0, 0, 58; %load/vec4 v0x55556fbdb160_0; %parti/s 6, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.14; T_10.13 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 12, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; T_10.14 ; %jmp T_10.10; T_10.3 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 12, 20, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.4 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 7, 25, 6; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 5, 7, 4; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.5 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 52; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 1, 7, 4; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 6, 25, 6; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 4, 8, 5; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.6 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 32; %load/vec4 v0x55556fbdb160_0; %parti/s 20, 12, 5; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 12; %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.7 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 32; %load/vec4 v0x55556fbdb160_0; %parti/s 20, 12, 5; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 12; %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.8 ; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %replicate 31; %load/vec4 v0x55556fbdb160_0; %parti/s 1, 31, 6; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 8, 12, 5; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 1, 20, 6; %concat/vec4; draw_concat_vec4 %load/vec4 v0x55556fbdb160_0; %parti/s 10, 21, 6; %concat/vec4; draw_concat_vec4 %concati/vec4 0, 0, 1; %pad/u 64; %assign/vec4 v0x55556fbdaf80_0, 0; %jmp T_10.10; T_10.10 ; %pop/vec4 1; %jmp T_10; .thread T_10, $push; .scope S_0x55556fbb5ee0; T_11 ; %wait E_0x55556fbd3b00; %load/vec4 v0x55556fafe1c0_0; %dup/vec4; %pushi/vec4 0, 0, 4; %cmp/u; %jmp/1 T_11.0, 6; %dup/vec4; %pushi/vec4 8, 0, 4; %cmp/u; %jmp/1 T_11.1, 6; %dup/vec4; %pushi/vec4 1, 0, 4; %cmp/u; %jmp/1 T_11.2, 6; %dup/vec4; %pushi/vec4 2, 0, 4; %cmp/u; %jmp/1 T_11.3, 6; %dup/vec4; %pushi/vec4 3, 0, 4; %cmp/u; %jmp/1 T_11.4, 6; %dup/vec4; %pushi/vec4 4, 0, 4; %cmp/u; %jmp/1 T_11.5, 6; %dup/vec4; %pushi/vec4 5, 0, 4; %cmp/u; %jmp/1 T_11.6, 6; %dup/vec4; %pushi/vec4 13, 0, 4; %cmp/u; %jmp/1 T_11.7, 6; %dup/vec4; %pushi/vec4 6, 0, 4; %cmp/u; %jmp/1 T_11.8, 6; %dup/vec4; %pushi/vec4 7, 0, 4; %cmp/u; %jmp/1 T_11.9, 6; %pushi/vec4 0, 0, 64; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.0 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %add; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.1 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %sub; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.2 ; %load/vec4 v0x55556fbad9c0_0; %ix/getv 4, v0x55556fb80190_0; %shiftl 4; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.3 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %cmp/s; %flag_mov 8, 5; %jmp/0 T_11.12, 8; %pushi/vec4 1, 0, 64; %jmp/1 T_11.13, 8; T_11.12 ; End of true expr. %pushi/vec4 0, 0, 64; %jmp/0 T_11.13, 8; ; End of false expr. %blend; T_11.13; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.4 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %cmp/u; %flag_mov 8, 5; %jmp/0 T_11.14, 8; %pushi/vec4 1, 0, 64; %jmp/1 T_11.15, 8; T_11.14 ; End of true expr. %pushi/vec4 0, 0, 64; %jmp/0 T_11.15, 8; ; End of false expr. %blend; T_11.15; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.5 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %xor; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.6 ; %load/vec4 v0x55556fbad9c0_0; %ix/getv 4, v0x55556fb80190_0; %shiftr 4; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.7 ; %load/vec4 v0x55556fbad9c0_0; %ix/getv 4, v0x55556fb80190_0; %shiftr/s 4; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.8 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %or; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.9 ; %load/vec4 v0x55556fbad9c0_0; %load/vec4 v0x55556fb80190_0; %and; %assign/vec4 v0x55556fafe2a0_0, 0; %jmp T_11.11; T_11.11 ; %pop/vec4 1; %jmp T_11; .thread T_11, $push; .scope S_0x55556fbd4480; T_12 ; %wait E_0x55556fbd4610; %load/vec4 v0x55556fbd4810_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; %jmp/1 T_12.0, 6; %dup/vec4; %pushi/vec4 1, 0, 3; %cmp/u; %jmp/1 T_12.1, 6; %dup/vec4; %pushi/vec4 4, 0, 3; %cmp/u; %jmp/1 T_12.2, 6; %dup/vec4; %pushi/vec4 5, 0, 3; %cmp/u; %jmp/1 T_12.3, 6; %dup/vec4; %pushi/vec4 6, 0, 3; %cmp/u; %jmp/1 T_12.4, 6; %dup/vec4; %pushi/vec4 7, 0, 3; %cmp/u; %jmp/1 T_12.5, 6; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.0 ; %load/vec4 v0x55556fbd49b0_0; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.1 ; %load/vec4 v0x55556fbd49b0_0; %inv; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.2 ; %load/vec4 v0x55556fbd4750_0; %parti/s 1, 0, 2; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.3 ; %load/vec4 v0x55556fbd4750_0; %parti/s 1, 0, 2; %inv; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.4 ; %load/vec4 v0x55556fbd4750_0; %parti/s 1, 0, 2; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.5 ; %load/vec4 v0x55556fbd4750_0; %parti/s 1, 0, 2; %inv; %assign/vec4 v0x55556fbd48e0_0, 0; %jmp T_12.7; T_12.7 ; %pop/vec4 1; %jmp T_12; .thread T_12, $push; .scope S_0x55556fb059f0; T_13 ; %wait E_0x55556fb05ba0; %load/vec4 v0x55556fb05e00_0; %dup/vec4; %pushi/vec4 51, 0, 7; %cmp/u; %jmp/1 T_13.0, 6; %dup/vec4; %pushi/vec4 59, 0, 7; %cmp/u; %jmp/1 T_13.1, 6; %dup/vec4; %pushi/vec4 19, 0, 7; %cmp/u; %jmp/1 T_13.2, 6; %dup/vec4; %pushi/vec4 27, 0, 7; %cmp/u; %jmp/1 T_13.3, 6; %dup/vec4; %pushi/vec4 3, 0, 7; %cmp/u; %jmp/1 T_13.4, 6; %dup/vec4; %pushi/vec4 35, 0, 7; %cmp/u; %jmp/1 T_13.5, 6; %dup/vec4; %pushi/vec4 99, 0, 7; %cmp/u; %jmp/1 T_13.6, 6; %dup/vec4; %pushi/vec4 55, 0, 7; %cmp/u; %jmp/1 T_13.7, 6; %dup/vec4; %pushi/vec4 23, 0, 7; %cmp/u; %jmp/1 T_13.8, 6; %dup/vec4; %pushi/vec4 111, 0, 7; %cmp/u; %jmp/1 T_13.9, 6; %dup/vec4; %pushi/vec4 103, 0, 7; %cmp/u; %jmp/1 T_13.10, 6; %pushi/vec4 15, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.0 ; %load/vec4 v0x55556fb05d60_0; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.1 ; %load/vec4 v0x55556fb05d60_0; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.2 ; %load/vec4 v0x55556fb05d60_0; %parti/s 3, 0, 2; %cmpi/e 5, 0, 3; %jmp/0xz T_13.13, 4; %load/vec4 v0x55556fb05d60_0; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.14; T_13.13 ; %pushi/vec4 0, 0, 1; %load/vec4 v0x55556fb05d60_0; %parti/s 3, 0, 2; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fb05cc0_0, 0; T_13.14 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.3 ; %load/vec4 v0x55556fb05d60_0; %parti/s 3, 0, 2; %cmpi/e 5, 0, 3; %jmp/0xz T_13.15, 4; %load/vec4 v0x55556fb05d60_0; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.16; T_13.15 ; %pushi/vec4 0, 0, 1; %load/vec4 v0x55556fb05d60_0; %parti/s 3, 0, 2; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fb05cc0_0, 0; T_13.16 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.4 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.5 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.6 ; %load/vec4 v0x55556fb05d60_0; %parti/s 3, 0, 2; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; %jmp/1 T_13.17, 6; %dup/vec4; %pushi/vec4 1, 0, 3; %cmp/u; %jmp/1 T_13.18, 6; %dup/vec4; %pushi/vec4 4, 0, 3; %cmp/u; %jmp/1 T_13.19, 6; %dup/vec4; %pushi/vec4 5, 0, 3; %cmp/u; %jmp/1 T_13.20, 6; %dup/vec4; %pushi/vec4 6, 0, 3; %cmp/u; %jmp/1 T_13.21, 6; %dup/vec4; %pushi/vec4 7, 0, 3; %cmp/u; %jmp/1 T_13.22, 6; %pushi/vec4 15, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.17 ; %pushi/vec4 8, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.18 ; %pushi/vec4 8, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.19 ; %pushi/vec4 2, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.20 ; %pushi/vec4 2, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.21 ; %pushi/vec4 3, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.22 ; %pushi/vec4 3, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %jmp T_13.24; T_13.24 ; %pop/vec4 1; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.7 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.8 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.9 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.10 ; %pushi/vec4 0, 0, 4; %assign/vec4 v0x55556fb05cc0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb05c00_0, 0; %jmp T_13.12; T_13.12 ; %pop/vec4 1; %jmp T_13; .thread T_13, $push; .scope S_0x55556fbd6590; T_14 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_14.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 0, 2; %flag_set/vec4 8; %jmp/0xz T_14.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 0, 2; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 0, 4; T_14.2 ; T_14.0 ; %jmp T_14; .thread T_14; .scope S_0x55556fbd68d0; T_15 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_15.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 1, 2; %flag_set/vec4 8; %jmp/0xz T_15.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 8, 5; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 8, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_15.2 ; T_15.0 ; %jmp T_15; .thread T_15; .scope S_0x55556fbd6bc0; T_16 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_16.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 2, 3; %flag_set/vec4 8; %jmp/0xz T_16.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 16, 6; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 16, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_16.2 ; T_16.0 ; %jmp T_16; .thread T_16; .scope S_0x55556fbd6e80; T_17 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_17.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 3, 3; %flag_set/vec4 8; %jmp/0xz T_17.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 24, 6; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 24, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_17.2 ; T_17.0 ; %jmp T_17; .thread T_17; .scope S_0x55556fbd7190; T_18 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_18.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 4, 4; %flag_set/vec4 8; %jmp/0xz T_18.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 32, 7; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 32, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_18.2 ; T_18.0 ; %jmp T_18; .thread T_18; .scope S_0x55556fbd7450; T_19 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_19.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 5, 4; %flag_set/vec4 8; %jmp/0xz T_19.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 40, 7; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 40, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_19.2 ; T_19.0 ; %jmp T_19; .thread T_19; .scope S_0x55556fbd7710; T_20 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_20.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 6, 4; %flag_set/vec4 8; %jmp/0xz T_20.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 48, 7; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 48, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_20.2 ; T_20.0 ; %jmp T_20; .thread T_20; .scope S_0x55556fbd79d0; T_21 ; %wait E_0x55556fbd6870; %load/vec4 v0x55556fbd86e0_0; %flag_set/vec4 8; %jmp/0xz T_21.0, 8; %load/vec4 v0x55556fbd8600_0; %parti/s 1, 7, 4; %flag_set/vec4 8; %jmp/0xz T_21.2, 8; %load/vec4 v0x55556fbd8310_0; %parti/s 8, 56, 7; %load/vec4 v0x55556fbd80b0_0; %pad/u 14; %ix/vec4 3; %ix/load 4, 56, 0; part off %ix/load 5, 0, 0; Constant delay %assign/vec4/a/d v0x55556fbd7c40, 4, 5; T_21.2 ; T_21.0 ; %jmp T_21; .thread T_21; .scope S_0x55556fbd8f30; T_22 ; %wait E_0x55556fbd5c10; %load/vec4 v0x55556fbd9490_0; %load/vec4 v0x55556fbd93a0_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/ne; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd93a0_0; %load/vec4 v0x55556fbd91c0_0; %cmp/e; %flag_get/vec4 4; %and; %flag_set/vec4 8; %jmp/0xz T_22.0, 8; %pushi/vec4 2, 0, 2; %assign/vec4 v0x55556fbd9b10_0, 0; %jmp T_22.1; T_22.0 ; %load/vec4 v0x55556fbd9680_0; %load/vec4 v0x55556fbd9550_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/ne; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd9550_0; %load/vec4 v0x55556fbd91c0_0; %cmp/e; %flag_get/vec4 4; %and; %flag_set/vec4 8; %jmp/0xz T_22.2, 8; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd9b10_0, 0; %jmp T_22.3; T_22.2 ; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd9b10_0, 0; T_22.3 ; T_22.1 ; %load/vec4 v0x55556fbd9490_0; %load/vec4 v0x55556fbd93a0_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/ne; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd93a0_0; %load/vec4 v0x55556fbd92c0_0; %cmp/e; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd9db0_0; %inv; %and; %flag_set/vec4 8; %jmp/0xz T_22.4, 8; %pushi/vec4 2, 0, 2; %assign/vec4 v0x55556fbd9bf0_0, 0; %jmp T_22.5; T_22.4 ; %load/vec4 v0x55556fbd9490_0; %load/vec4 v0x55556fbd93a0_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/ne; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd9550_0; %load/vec4 v0x55556fbd92c0_0; %cmp/e; %flag_get/vec4 4; %and; %load/vec4 v0x55556fbd9db0_0; %inv; %and; %flag_set/vec4 8; %jmp/0xz T_22.6, 8; %pushi/vec4 1, 0, 2; %assign/vec4 v0x55556fbd9bf0_0, 0; %jmp T_22.7; T_22.6 ; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbd9bf0_0, 0; T_22.7 ; T_22.5 ; %jmp T_22; .thread T_22, $push; .scope S_0x55556fbd9f90; T_23 ; %wait E_0x55556fbda170; %load/vec4 v0x55556fbda2c0_0; %load/vec4 v0x55556fbda360_0; %load/vec4 v0x55556fbda450_0; %cmp/e; %flag_get/vec4 4; %load/vec4 v0x55556fbda360_0; %load/vec4 v0x55556fbda530_0; %cmp/e; %flag_get/vec4 4; %or; %and; %flag_set/vec4 8; %jmp/0xz T_23.0, 8; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbda720_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbda660_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbda880_0, 0; %jmp T_23.1; T_23.0 ; %load/vec4 v0x55556fbda200_0; %cmpi/e 1, 0, 1; %jmp/0xz T_23.2, 4; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbda880_0, 0; %jmp T_23.3; T_23.2 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbda720_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbda660_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbda880_0, 0; T_23.3 ; T_23.1 ; %jmp T_23; .thread T_23, $push; .scope S_0x55556fb079e0; T_24 ; %wait E_0x55556fafe5a0; %load/vec4 v0x55556fb40360_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_24.0, 8; %pushi/vec4 0, 0, 32; %store/vec4 v0x55556fb40280_0, 0, 32; T_24.2 ; Top of for-loop %load/vec4 v0x55556fb40280_0; %cmpi/s 15, 0, 32; %flag_or 5, 4; %jmp/0xz T_24.3, 5; %pushi/vec4 0, 0, 2; %ix/getv/s 3, v0x55556fb40280_0; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fb4b6e0, 0, 4; T_24.4 ; for-loop step statement %load/vec4 v0x55556fb40280_0; %addi 1, 0, 32; %store/vec4 v0x55556fb40280_0, 0, 32; %jmp T_24.2; T_24.3 ; for-loop exit label %jmp T_24.1; T_24.0 ; %load/vec4 v0x55556fb18340_0; %load/vec4 v0x55556fb18560_0; %and; %flag_set/vec4 8; %jmp/0xz T_24.5, 8; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %pad/u 32; %cmpi/u 3, 0, 32; %jmp/0xz T_24.7, 5; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %addi 1, 0, 2; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fb4b6e0, 0, 4; T_24.7 ; %jmp T_24.6; T_24.5 ; %load/vec4 v0x55556fb18340_0; %load/vec4 v0x55556fb18560_0; %nor/r; %and; %flag_set/vec4 8; %jmp/0xz T_24.9, 8; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %pad/u 32; %cmpi/u 0, 0, 32; %flag_or 5, 4; GT is !LE %flag_inv 5; %jmp/0xz T_24.11, 5; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %subi 1, 0, 2; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 3; %ix/load 4, 0, 0; Constant delay %assign/vec4/a/d v0x55556fb4b6e0, 0, 4; T_24.11 ; T_24.9 ; T_24.6 ; T_24.1 ; %jmp T_24; .thread T_24; .scope S_0x55556fb079e0; T_25 ; %wait E_0x55556fb07dc0; %load/vec4 v0x55556fb18340_0; %flag_set/vec4 8; %jmp/0xz T_25.0, 8; %load/vec4 v0x55556fb18560_0; %flag_set/vec4 8; %jmp/0xz T_25.2, 8; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %pad/u 32; %cmpi/u 2, 0, 32; %flag_inv 5; GE is !LT %jmp/0xz T_25.4, 5; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; %jmp T_25.5; T_25.4 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; T_25.5 ; %jmp T_25.3; T_25.2 ; %load/vec4 v0x55556fb18240_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %pad/u 32; %cmpi/u 2, 0, 32; %jmp/0xz T_25.6, 5; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; %jmp T_25.7; T_25.6 ; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; T_25.7 ; T_25.3 ; %load/vec4 v0x55556fb18400_0; %load/vec4 v0x55556fb184a0_0; %or; %flag_set/vec4 8; %jmp/0xz T_25.8, 8; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; T_25.8 ; %jmp T_25.1; T_25.0 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb4b560_0, 0; T_25.1 ; %jmp T_25; .thread T_25, $push; .scope S_0x55556fb079e0; T_26 ; %wait E_0x55556fb07ce0; %load/vec4 v0x55556fb4b4a0_0; %flag_set/vec4 8; %jmp/0xz T_26.0, 8; %load/vec4 v0x55556fb18620_0; %pad/u 6; %ix/vec4 4; %load/vec4a v0x55556fb4b6e0, 4; %pad/u 32; %cmpi/u 2, 0, 32; %flag_inv 5; GE is !LT %jmp/0xz T_26.2, 5; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fb4b620_0, 0; %jmp T_26.3; T_26.2 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb4b620_0, 0; T_26.3 ; %jmp T_26.1; T_26.0 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fb4b620_0, 0; T_26.1 ; %jmp T_26; .thread T_26, $push; .scope S_0x55556fbdd780; T_27 ; %wait E_0x55556fbdda20; %load/vec4 v0x55556fbdde40_0; %parti/s 2, 0, 2; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_27.0, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_27.1, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_27.2, 6; %dup/vec4; %pushi/vec4 3, 0, 2; %cmp/u; %jmp/1 T_27.3, 6; %jmp T_27.4; T_27.0 ; %load/vec4 v0x55556fbddc60_0; %parti/s 3, 0, 2; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; %jmp/1 T_27.5, 6; %dup/vec4; %pushi/vec4 1, 0, 3; %cmp/u; %jmp/1 T_27.6, 6; %dup/vec4; %pushi/vec4 2, 0, 3; %cmp/u; %jmp/1 T_27.7, 6; %dup/vec4; %pushi/vec4 3, 0, 3; %cmp/u; %jmp/1 T_27.8, 6; %dup/vec4; %pushi/vec4 4, 0, 3; %cmp/u; %jmp/1 T_27.9, 6; %dup/vec4; %pushi/vec4 5, 0, 3; %cmp/u; %jmp/1 T_27.10, 6; %dup/vec4; %pushi/vec4 6, 0, 3; %cmp/u; %jmp/1 T_27.11, 6; %dup/vec4; %pushi/vec4 7, 0, 3; %cmp/u; %jmp/1 T_27.12, 6; %jmp T_27.14; T_27.5 ; %pushi/vec4 1, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 7, 4; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 0, 2; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.6 ; %pushi/vec4 2, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 15, 5; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 8, 5; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.7 ; %pushi/vec4 4, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 23, 6; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 16, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.8 ; %pushi/vec4 8, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 31, 6; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 24, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.9 ; %pushi/vec4 16, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 39, 7; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 32, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.10 ; %pushi/vec4 32, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 47, 7; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 40, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.11 ; %pushi/vec4 64, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 55, 7; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 48, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.12 ; %pushi/vec4 128, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 63, 7; %and; %replicate 56; %load/vec4 v0x55556fbddf00_0; %parti/s 8, 56, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.14; T_27.14 ; %pop/vec4 1; %jmp T_27.4; T_27.1 ; %load/vec4 v0x55556fbddc60_0; %parti/s 2, 0, 2; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_27.15, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_27.16, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_27.17, 6; %dup/vec4; %pushi/vec4 3, 0, 2; %cmp/u; %jmp/1 T_27.18, 6; %jmp T_27.20; T_27.15 ; %pushi/vec4 3, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 15, 5; %and; %replicate 48; %load/vec4 v0x55556fbddf00_0; %parti/s 16, 0, 2; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.20; T_27.16 ; %pushi/vec4 12, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 31, 6; %and; %replicate 48; %load/vec4 v0x55556fbddf00_0; %parti/s 16, 16, 6; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.20; T_27.17 ; %pushi/vec4 48, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 47, 7; %and; %replicate 48; %load/vec4 v0x55556fbddf00_0; %parti/s 16, 32, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.20; T_27.18 ; %pushi/vec4 192, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 63, 7; %and; %replicate 48; %load/vec4 v0x55556fbddf00_0; %parti/s 16, 48, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.20; T_27.20 ; %pop/vec4 1; %jmp T_27.4; T_27.2 ; %load/vec4 v0x55556fbddc60_0; %parti/s 1, 0, 2; %dup/vec4; %pushi/vec4 0, 0, 1; %cmp/u; %jmp/1 T_27.21, 6; %dup/vec4; %pushi/vec4 1, 0, 1; %cmp/u; %jmp/1 T_27.22, 6; %jmp T_27.24; T_27.21 ; %pushi/vec4 15, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 31, 6; %and; %replicate 32; %load/vec4 v0x55556fbddf00_0; %parti/s 32, 0, 2; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.24; T_27.22 ; %pushi/vec4 240, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbdde40_0; %parti/s 1, 2, 3; %inv; %load/vec4 v0x55556fbddf00_0; %parti/s 1, 63, 7; %and; %replicate 32; %load/vec4 v0x55556fbddf00_0; %parti/s 32, 32, 7; %concat/vec4; draw_concat_vec4 %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.24; T_27.24 ; %pop/vec4 1; %jmp T_27.4; T_27.3 ; %pushi/vec4 255, 0, 8; %assign/vec4 v0x55556fbde0f0_0, 0; %load/vec4 v0x55556fbddf00_0; %assign/vec4 v0x55556fbde010_0, 0; %jmp T_27.4; T_27.4 ; %pop/vec4 1; %jmp T_27; .thread T_27, $push; .scope S_0x55556fbc8600; T_28 ; %wait E_0x55556fafe5a0; %load/vec4 v0x55556fbe65d0_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_28.0, 8; %pushi/vec4 0, 0, 64; %assign/vec4 v0x55556fbe4a20_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe3e30_0, 0; %pushi/vec4 0, 0, 96; %assign/vec4 v0x55556fbe3a30_0, 0; %jmp T_28.1; T_28.0 ; %load/vec4 v0x55556fbe3d60_0; %assign/vec4 v0x55556fbe3e30_0, 0; %load/vec4 v0x55556fbe3d60_0; %flag_set/vec4 8; %jmp/0xz T_28.2, 8; %load/vec4 v0x55556fbe2750_0; %assign/vec4 v0x55556fbe4a20_0, 0; %jmp T_28.3; T_28.2 ; %load/vec4 v0x55556fbe3bc0_0; %flag_set/vec4 8; %jmp/0xz T_28.4, 8; %load/vec4 v0x55556fbe3e30_0; %load/vec4 v0x55556fbe3c90_0; %and; %flag_set/vec4 8; %jmp/0xz T_28.6, 8; %load/vec4 v0x55556fbe4ba0_0; %assign/vec4 v0x55556fbe4a20_0, 0; %jmp T_28.7; T_28.6 ; %load/vec4 v0x55556fbe1550_0; %load/vec4 v0x55556fbe3e30_0; %nor/r; %and; %flag_set/vec4 8; %jmp/0xz T_28.8, 8; %load/vec4 v0x55556fbe15f0_0; %assign/vec4 v0x55556fbe4a20_0, 0; %jmp T_28.9; T_28.8 ; %load/vec4 v0x55556fbe4a20_0; %addi 4, 0, 64; %assign/vec4 v0x55556fbe4a20_0, 0; T_28.9 ; T_28.7 ; T_28.4 ; T_28.3 ; %load/vec4 v0x55556fbe3c90_0; %flag_set/vec4 8; %jmp/0xz T_28.10, 8; %pushi/vec4 0, 0, 32; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3a30_0, 4, 5; %jmp T_28.11; T_28.10 ; %load/vec4 v0x55556fbe3af0_0; %flag_set/vec4 8; %jmp/0xz T_28.12, 8; %load/vec4 v0x55556fbe6320_0; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3a30_0, 4, 5; %load/vec4 v0x55556fbe4a20_0; %ix/load 5, 0, 0; %ix/load 4, 32, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3a30_0, 4, 5; T_28.12 ; T_28.11 ; T_28.1 ; %jmp T_28; .thread T_28; .scope S_0x55556fbc8600; T_29 ; %wait E_0x55556fafe5a0; %load/vec4 v0x55556fbe65d0_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_29.0, 8; %pushi/vec4 0, 0, 352; %assign/vec4 v0x55556fbe2670_0, 0; %pushi/vec4 0, 0, 10; %assign/vec4 v0x55556fbe2590_0, 0; %jmp T_29.1; T_29.0 ; %load/vec4 v0x55556fbe2d70_0; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe6230_0; %ix/load 5, 0, 0; %ix/load 4, 64, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe37b0_0; %parti/s 1, 0, 2; %flag_set/vec4 8; %jmp/0 T_29.2, 8; %load/vec4 v0x55556fbe4fa0_0; %jmp/1 T_29.3, 8; T_29.2 ; End of true expr. %load/vec4 v0x55556fbe3870_0; %jmp/0 T_29.3, 8; ; End of false expr. %blend; T_29.3; %ix/load 5, 0, 0; %ix/load 4, 96, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe37b0_0; %parti/s 1, 1, 2; %flag_set/vec4 8; %jmp/0 T_29.4, 8; %load/vec4 v0x55556fbe4fa0_0; %jmp/1 T_29.5, 8; T_29.4 ; End of true expr. %load/vec4 v0x55556fbe3960_0; %jmp/0 T_29.5, 8; ; End of false expr. %blend; T_29.5; %ix/load 5, 0, 0; %ix/load 4, 160, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe4ba0_0; %ix/load 5, 0, 0; %ix/load 4, 224, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe2750_0; %ix/load 5, 0, 0; %ix/load 4, 288, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2670_0, 4, 5; %load/vec4 v0x55556fbe3640_0; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe3290_0; %ix/load 5, 0, 0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe2b40_0; %ix/load 5, 0, 0; %ix/load 4, 2, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe3120_0; %ix/load 5, 0, 0; %ix/load 4, 3, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe3400_0; %ix/load 5, 0, 0; %ix/load 4, 4, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe29d0_0; %ix/load 5, 0, 0; %ix/load 4, 5, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe2830_0; %ix/load 5, 0, 0; %ix/load 4, 6, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe2e40_0; %ix/load 5, 0, 0; %ix/load 4, 8, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; %load/vec4 v0x55556fbe2fb0_0; %ix/load 5, 0, 0; %ix/load 4, 9, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe2590_0, 4, 5; T_29.1 ; %jmp T_29; .thread T_29; .scope S_0x55556fbc8600; T_30 ; %wait E_0x55556fbd3680; %load/vec4 v0x55556fbe2cd0_0; %flag_set/vec4 8; %jmp/0xz T_30.0, 8; %load/vec4 v0x55556fbe2be0_0; %assign/vec4 v0x55556fbe2b40_0, 0; %load/vec4 v0x55556fbe31c0_0; %assign/vec4 v0x55556fbe3120_0, 0; %load/vec4 v0x55556fbe3330_0; %assign/vec4 v0x55556fbe3290_0, 0; %load/vec4 v0x55556fbe34a0_0; %assign/vec4 v0x55556fbe3400_0, 0; %load/vec4 v0x55556fbe2910_0; %assign/vec4 v0x55556fbe2830_0, 0; %load/vec4 v0x55556fbe2a70_0; %assign/vec4 v0x55556fbe29d0_0, 0; %load/vec4 v0x55556fbe36e0_0; %assign/vec4 v0x55556fbe3640_0, 0; %load/vec4 v0x55556fbe2ee0_0; %assign/vec4 v0x55556fbe2e40_0, 0; %load/vec4 v0x55556fbe3050_0; %assign/vec4 v0x55556fbe2fb0_0, 0; %jmp T_30.1; T_30.0 ; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe2b40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe3120_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe3290_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe3400_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbe2830_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe29d0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe3640_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe2e40_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v0x55556fbe2fb0_0, 0; T_30.1 ; %jmp T_30; .thread T_30, $push; .scope S_0x55556fbc8600; T_31 ; %wait E_0x55556fa38ca0; %load/vec4 v0x55556fbe2e40_0; %flag_set/vec4 8; %jmp/0xz T_31.0, 8; %load/vec4 v0x55556fbe4ba0_0; %load/vec4 v0x55556fbe2d70_0; %add; %assign/vec4 v0x55556fbe2750_0, 0; %jmp T_31.1; T_31.0 ; %load/vec4 v0x55556fbe2fb0_0; %flag_set/vec4 8; %jmp/0xz T_31.2, 8; %load/vec4 v0x55556fbe3870_0; %load/vec4 v0x55556fbe2d70_0; %parti/s 63, 1, 2; %concati/vec4 0, 0, 1; %add; %assign/vec4 v0x55556fbe2750_0, 0; %jmp T_31.3; T_31.2 ; %load/vec4 v0x55556fbe4ba0_0; %load/vec4 v0x55556fbe2d70_0; %parti/s 63, 0, 2; %concati/vec4 0, 0, 1; %add; %assign/vec4 v0x55556fbe2750_0, 0; T_31.3 ; T_31.1 ; %jmp T_31; .thread T_31, $push; .scope S_0x55556fbc8600; T_32 ; %wait E_0x55556fafe5a0; %load/vec4 v0x55556fbe65d0_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_32.0, 8; %pushi/vec4 0, 0, 160; %assign/vec4 v0x55556fbe1470_0, 0; %pushi/vec4 0, 0, 5; %assign/vec4 v0x55556fbe1370_0, 0; %jmp T_32.1; T_32.0 ; %load/vec4 v0x55556fbe1d20_0; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1470_0, 4, 5; %load/vec4 v0x55556fbe1ab0_0; %ix/load 5, 0, 0; %ix/load 4, 64, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1470_0, 4, 5; %load/vec4 v0x55556fbe6150_0; %ix/load 5, 0, 0; %ix/load 4, 128, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1470_0, 4, 5; %load/vec4 v0x55556fbe2590_0; %parti/s 1, 0, 2; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1370_0, 4, 5; %load/vec4 v0x55556fbe2590_0; %parti/s 1, 1, 2; %ix/load 5, 0, 0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1370_0, 4, 5; %load/vec4 v0x55556fbe2590_0; %parti/s 1, 2, 3; %ix/load 5, 0, 0; %ix/load 4, 2, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1370_0, 4, 5; %load/vec4 v0x55556fbe2590_0; %parti/s 1, 3, 3; %ix/load 5, 0, 0; %ix/load 4, 3, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1370_0, 4, 5; %load/vec4 v0x55556fbe2590_0; %parti/s 1, 4, 4; %ix/load 5, 0, 0; %ix/load 4, 4, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe1370_0, 4, 5; T_32.1 ; %jmp T_32; .thread T_32; .scope S_0x55556fbc8600; T_33 ; %wait E_0x55556fb41c60; %load/vec4 v0x55556fbe2010_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_33.0, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_33.1, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_33.2, 6; %load/vec4 v0x55556fbe2430_0; %assign/vec4 v0x55556fbe1930_0, 0; %jmp T_33.4; T_33.0 ; %load/vec4 v0x55556fbe2430_0; %assign/vec4 v0x55556fbe1930_0, 0; %jmp T_33.4; T_33.1 ; %load/vec4 v0x55556fbe4140_0; %assign/vec4 v0x55556fbe1930_0, 0; %jmp T_33.4; T_33.2 ; %load/vec4 v0x55556fbe4fa0_0; %assign/vec4 v0x55556fbe1930_0, 0; %jmp T_33.4; T_33.4 ; %pop/vec4 1; %jmp T_33; .thread T_33, $push; .scope S_0x55556fbc8600; T_34 ; %wait E_0x55556fb416d0; %load/vec4 v0x55556fbe20d0_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_34.0, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_34.1, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_34.2, 6; %load/vec4 v0x55556fbe24d0_0; %assign/vec4 v0x55556fbe1ab0_0, 0; %jmp T_34.4; T_34.0 ; %load/vec4 v0x55556fbe24d0_0; %assign/vec4 v0x55556fbe1ab0_0, 0; %jmp T_34.4; T_34.1 ; %load/vec4 v0x55556fbe4140_0; %assign/vec4 v0x55556fbe1ab0_0, 0; %jmp T_34.4; T_34.2 ; %load/vec4 v0x55556fbe4fa0_0; %assign/vec4 v0x55556fbe1ab0_0, 0; %jmp T_34.4; T_34.4 ; %pop/vec4 1; %jmp T_34; .thread T_34, $push; .scope S_0x55556fbc8600; T_35 ; %wait E_0x55556fb41860; %load/vec4 v0x55556fbe22f0_0; %flag_set/vec4 8; %jmp/0xz T_35.0, 8; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbe1550_0, 0; %jmp T_35.1; T_35.0 ; %load/vec4 v0x55556fbe2390_0; %flag_set/vec4 8; %jmp/0xz T_35.2, 8; %pushi/vec4 1, 0, 1; %assign/vec4 v0x55556fbe1550_0, 0; %jmp T_35.3; T_35.2 ; %load/vec4 v0x55556fbe1e30_0; %load/vec4 v0x55556fbe1f20_0; %and; %assign/vec4 v0x55556fbe1550_0, 0; T_35.3 ; T_35.1 ; %jmp T_35; .thread T_35, $push; .scope S_0x55556fbc8600; T_36 ; %wait E_0x55556fafe5a0; %load/vec4 v0x55556fbe65d0_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_36.0, 8; %pushi/vec4 0, 0, 160; %assign/vec4 v0x55556fbe3f70_0, 0; %pushi/vec4 0, 0, 2; %assign/vec4 v0x55556fbe3ed0_0, 0; %jmp T_36.1; T_36.0 ; %load/vec4 v0x55556fbe42a0_0; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3f70_0, 4, 5; %load/vec4 v0x55556fbe4140_0; %ix/load 5, 0, 0; %ix/load 4, 64, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3f70_0, 4, 5; %load/vec4 v0x55556fbe6410_0; %ix/load 5, 0, 0; %ix/load 4, 128, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3f70_0, 4, 5; %load/vec4 v0x55556fbe1370_0; %parti/s 1, 0, 2; %ix/load 5, 0, 0; %ix/load 4, 0, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3ed0_0, 4, 5; %load/vec4 v0x55556fbe1370_0; %parti/s 1, 1, 2; %ix/load 5, 0, 0; %ix/load 4, 1, 0; %flag_set/imm 4, 0; %assign/vec4/off/d v0x55556fbe3ed0_0, 4, 5; T_36.1 ; %jmp T_36; .thread T_36; # The file index is used to find the file name in the following table. :file_names 16; "N/A"; ""; "core/rtl/rv_core.v"; "core/rtl/rv_alu.v"; "core/rtl/rv_alu_ctrl.v"; "core/rtl/rv_branch_predict.v"; "core/rtl/rv_branch_test.v"; "core/rtl/rv_ctrl.v"; "core/rtl/rv_data_mem.v"; "core/rtl/rv_dpram.v"; "core/rtl/rv_forward.v"; "core/rtl/rv_hzd_detect.v"; "core/rtl/rv_imm_gen.v"; "core/rtl/rv_instr_mem.v"; "core/rtl/rv_mem_map.v"; "core/rtl/rv_rf.v";