Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Still waiting to schedule task
Waiting for next available executor
Running on Jenkins in /var/lib/jenkins/workspace/Cores-VeeR-EH1
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -rf Cores-VeeR-EH1
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone --recursive <a href='https://github.com/chipsalliance/Cores-VeeR-EH1'>https://github.com/chipsalliance/Cores-VeeR-EH1</a> Cores-VeeR-EH1
Cloning into 'Cores-VeeR-EH1'...
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
<span class="pipeline-node-13">Running in /var/lib/jenkins/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-15">+ iverilog -o simulation.out -g2012 -s veer -I design/include design/dmi/dmi_jtag_to_core_sync.v design/dmi/dmi_wrapper.v design/dma_ctrl.sv design/mem.sv design/pic_ctrl.sv design/veer.sv design/veer_wrapper.sv design/dbg/dbg.sv design/dec/dec.sv design/dec/dec_decode_ctl.sv design/dec/dec_gpr_ctl.sv design/dec/dec_ib_ctl.sv design/dec/dec_tlu_ctl.sv design/dec/dec_trigger.sv design/dmi/rvjtag_tap.sv design/exu/exu.sv design/exu/exu_alu_ctl.sv design/exu/exu_div_ctl.sv design/exu/exu_mul_ctl.sv design/ifu/ifu.sv design/ifu/ifu_aln_ctl.sv design/ifu/ifu_bp_ctl.sv design/ifu/ifu_compress_ctl.sv design/ifu/ifu_ic_mem.sv design/ifu/ifu_iccm_mem.sv design/ifu/ifu_ifc_ctl.sv design/ifu/ifu_mem_ctl.sv design/include/veer_types.sv design/lib/ahb_to_axi4.sv design/lib/axi4_to_ahb.sv design/lib/beh_lib.sv design/lib/mem_lib.sv design/lib/svci_to_axi4.sv design/lsu/lsu.sv design/lsu/lsu_addrcheck.sv design/lsu/lsu_bus_buffer.sv design/lsu/lsu_bus_intf.sv design/lsu/lsu_clkdomain.sv design/lsu/lsu_dccm_ctl.sv design/lsu/lsu_dccm_mem.sv design/lsu/lsu_ecc.sv design/lsu/lsu_lsc_ctl.sv design/lsu/lsu_trigger.sv
design/dma_ctrl.sv:35: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/dma_ctrl.sv:51: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/dma_ctrl.sv:56: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/dma_ctrl.sv:65: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:16: warning: macro RV_PIC_TOTAL_INT_PLUS1 undefined (and assumed null) at this point.
design/include/global.h:18: warning: macro RV_DCCM_BITS undefined (and assumed null) at this point.
design/include/global.h:19: warning: macro RV_DCCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:20: warning: macro RV_DCCM_NUM_BANKS undefined (and assumed null) at this point.
design/include/global.h:21: warning: macro RV_DCCM_DATA_WIDTH undefined (and assumed null) at this point.
design/include/global.h:22: warning: macro RV_DCCM_FDATA_WIDTH undefined (and assumed null) at this point.
design/include/global.h:23: warning: macro RV_DCCM_BYTE_WIDTH undefined (and assumed null) at this point.
design/include/global.h:24: warning: macro RV_DCCM_ECC_WIDTH undefined (and assumed null) at this point.
design/include/global.h:26: warning: macro RV_LSU_NUM_NBLOAD undefined (and assumed null) at this point.
design/include/global.h:27: warning: macro RV_DMA_BUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:28: warning: macro RV_LSU_STBUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:29: warning: macro RV_LSU_SB_BITS undefined (and assumed null) at this point.
design/include/global.h:31: warning: macro RV_DEC_INSTBUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:33: warning: macro RV_ICCM_SIZE undefined (and assumed null) at this point.
design/include/global.h:34: warning: macro RV_ICCM_BITS undefined (and assumed null) at this point.
design/include/global.h:35: warning: macro RV_ICCM_NUM_BANKS undefined (and assumed null) at this point.
design/include/global.h:36: warning: macro RV_ICCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:37: warning: macro RV_ICCM_INDEX_BITS undefined (and assumed null) at this point.
design/include/global.h:38: warning: macro RV_ICCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:40: warning: macro RV_ICACHE_TAG_HIGH undefined (and assumed null) at this point.
design/include/global.h:41: warning: macro RV_ICACHE_TAG_LOW undefined (and assumed null) at this point.
design/include/global.h:42: warning: macro RV_ICACHE_IC_DEPTH undefined (and assumed null) at this point.
design/include/global.h:43: warning: macro RV_ICACHE_TAG_DEPTH undefined (and assumed null) at this point.
design/include/global.h:45: warning: macro RV_LSU_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:46: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:47: warning: macro RV_SB_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:49: warning: macro RV_IFU_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:16: syntax error
design/include/global.h:16: error: syntax error localparam list.
design/include/global.h:18: syntax error
design/include/global.h:18: error: syntax error localparam list.
design/include/global.h:19: syntax error
design/include/global.h:19: error: syntax error localparam list.
design/include/global.h:20: syntax error
design/include/global.h:20: error: syntax error localparam list.
design/include/global.h:21: syntax error
design/include/global.h:21: error: syntax error localparam list.
design/include/global.h:22: syntax error
design/include/global.h:22: error: syntax error localparam list.
design/include/global.h:23: syntax error
design/include/global.h:23: error: syntax error localparam list.
design/include/global.h:24: syntax error
design/include/global.h:24: error: syntax error localparam list.
design/include/global.h:26: syntax error
design/include/global.h:26: error: syntax error localparam list.
design/include/global.h:27: syntax error
design/include/global.h:27: error: syntax error localparam list.
design/include/global.h:28: syntax error
design/include/global.h:28: error: syntax error localparam list.
design/include/global.h:29: syntax error
design/include/global.h:29: error: syntax error localparam list.
design/include/global.h:31: syntax error
design/include/global.h:31: error: syntax error localparam list.
design/include/global.h:33: syntax error
design/include/global.h:33: error: syntax error localparam list.
design/include/global.h:34: syntax error
design/include/global.h:34: error: syntax error localparam list.
design/include/global.h:35: syntax error
design/include/global.h:35: error: syntax error localparam list.
design/include/global.h:36: syntax error
design/include/global.h:36: error: syntax error localparam list.
design/include/global.h:37: syntax error
design/include/global.h:37: error: syntax error localparam list.
design/include/global.h:38: syntax error
design/include/global.h:38: error: syntax error localparam list.
design/include/global.h:40: syntax error
design/include/global.h:40: error: syntax error localparam list.
design/include/global.h:41: syntax error
design/include/global.h:41: error: syntax error localparam list.
design/include/global.h:42: syntax error
design/include/global.h:42: error: syntax error localparam list.
design/include/global.h:43: syntax error
design/include/global.h:43: error: syntax error localparam list.
design/include/global.h:45: syntax error
design/include/global.h:45: error: syntax error localparam list.
design/include/global.h:46: syntax error
design/include/global.h:46: error: syntax error localparam list.
design/include/global.h:47: syntax error
design/include/global.h:47: error: syntax error localparam list.
design/include/global.h:49: syntax error
design/include/global.h:49: error: syntax error localparam list.
design/dma_ctrl.sv:374: warning: macro RV_DCCM_SADR undefined (and assumed null) at this point.
design/dma_ctrl.sv:375: warning: macro RV_DCCM_SIZE undefined (and assumed null) at this point.
design/dma_ctrl.sv:395: warning: macro RV_PIC_BASE_ADDR undefined (and assumed null) at this point.
design/dma_ctrl.sv:396: warning: macro RV_PIC_SIZE undefined (and assumed null) at this point.
design/mem.sv:31: warning: macro RV_DCCM_BITS undefined (and assumed null) at this point.
design/mem.sv:32: warning: macro RV_DCCM_BITS undefined (and assumed null) at this point.
design/mem.sv:33: warning: macro RV_DCCM_BITS undefined (and assumed null) at this point.
design/mem.sv:34: warning: macro RV_DCCM_FDATA_WIDTH undefined (and assumed null) at this point.
design/mem.sv:37: warning: macro RV_DCCM_FDATA_WIDTH undefined (and assumed null) at this point.
design/mem.sv:38: warning: macro RV_DCCM_FDATA_WIDTH undefined (and assumed null) at this point.
design/include/global.h:16: warning: macro RV_PIC_TOTAL_INT_PLUS1 undefined (and assumed null) at this point.
design/include/global.h:18: warning: macro RV_DCCM_BITS undefined (and assumed null) at this point.
design/include/global.h:19: warning: macro RV_DCCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:20: warning: macro RV_DCCM_NUM_BANKS undefined (and assumed null) at this point.
design/include/global.h:21: warning: macro RV_DCCM_DATA_WIDTH undefined (and assumed null) at this point.
design/include/global.h:22: warning: macro RV_DCCM_FDATA_WIDTH undefined (and assumed null) at this point.
design/include/global.h:23: warning: macro RV_DCCM_BYTE_WIDTH undefined (and assumed null) at this point.
design/include/global.h:24: warning: macro RV_DCCM_ECC_WIDTH undefined (and assumed null) at this point.
design/include/global.h:26: warning: macro RV_LSU_NUM_NBLOAD undefined (and assumed null) at this point.
design/include/global.h:27: warning: macro RV_DMA_BUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:28: warning: macro RV_LSU_STBUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:29: warning: macro RV_LSU_SB_BITS undefined (and assumed null) at this point.
design/include/global.h:31: warning: macro RV_DEC_INSTBUF_DEPTH undefined (and assumed null) at this point.
design/include/global.h:33: warning: macro RV_ICCM_SIZE undefined (and assumed null) at this point.
design/include/global.h:34: warning: macro RV_ICCM_BITS undefined (and assumed null) at this point.
design/include/global.h:35: warning: macro RV_ICCM_NUM_BANKS undefined (and assumed null) at this point.
design/include/global.h:36: warning: macro RV_ICCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:37: warning: macro RV_ICCM_INDEX_BITS undefined (and assumed null) at this point.
design/include/global.h:38: warning: macro RV_ICCM_BANK_BITS undefined (and assumed null) at this point.
design/include/global.h:40: warning: macro RV_ICACHE_TAG_HIGH undefined (and assumed null) at this point.
design/include/global.h:41: warning: macro RV_ICACHE_TAG_LOW undefined (and assumed null) at this point.
design/include/global.h:42: warning: macro RV_ICACHE_IC_DEPTH undefined (and assumed null) at this point.
design/include/global.h:43: warning: macro RV_ICACHE_TAG_DEPTH undefined (and assumed null) at this point.
design/include/global.h:45: warning: macro RV_LSU_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:46: warning: macro RV_DMA_BUS_TAG undefined (and assumed null) at this point.
design/include/global.h:47: warning: macro RV_SB_BUS_TAG undefined (and assumed null) at this point.
design/mem.sv:19: syntax error
I give up.
design/include/global.h:49: warning: macro RV_IFU_BUS_TAG undefined (and assumed null) at this point.
design/pic_ctrl.sv:32: warning: macro RV_PIC_TOTAL_INT_PLUS1 undefined (and assumed null) at this point.
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-67">Failed in branch colorlight_i9
</span>[Pipeline] }
<span class="pipeline-node-68">Failed in branch digilent_nexys4_ddr
</span>[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
<span class="pipeline-node-74">Running in /var/lib/jenkins/workspace/Cores-VeeR-EH1/Cores-VeeR-EH1
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-76">+ rm -rf LICENSE README.md configs design docs release-notes.md testbench tools veer.core
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 56
Finished: FAILURE