Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/Cores-SweRV-EH2 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf *.xml [Pipeline] sh + rm -rf Cores-SweRV-EH2 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV-EH2 Cores-SweRV-EH2 Cloning into 'Cores-SweRV-EH2'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Verilog Convert) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 [Pipeline] { [Pipeline] sh + pwd + RV_ROOT=/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128 veer: Using target default veer: Set(s) requested : fpga_optimize=1 btb_size=128 veer: Overriding btb_size value 512 with 128 VeeR configuration for target=default veer: icache_bank_width = 8 veer: icache_num_bypass = 4 veer: icache_size = 32 veer: icache_tag_bypass_enable = 1 veer: icache_waypack = 1 veer: icache_ecc = 1 veer: icache_ln_sz = 64 veer: icache_banks_way = 2 veer: icache_2banks = 1 veer: icache_tag_num_bypass = 2 veer: icache_enable = 1 veer: icache_bypass_enable = 1 veer: icache_num_ways = 4 veer: ret_stack_size = 4 veer: data_access_enable3 = 0x0 veer: data_access_addr7 = 0x00000000 veer: inst_access_mask4 = 0xffffffff veer: data_access_enable1 = 0x0 veer: data_access_mask0 = 0xffffffff veer: data_access_enable6 = 0x0 veer: data_access_enable5 = 0x0 veer: inst_access_enable7 = 0x0 veer: inst_access_addr3 = 0x00000000 veer: data_access_mask5 = 0xffffffff veer: inst_access_addr1 = 0x00000000 veer: data_access_enable4 = 0x0 veer: data_access_mask6 = 0xffffffff veer: data_access_mask2 = 0xffffffff veer: inst_access_addr5 = 0x00000000 veer: data_access_mask1 = 0xffffffff veer: inst_access_addr6 = 0x00000000 veer: inst_access_addr2 = 0x00000000 veer: inst_access_enable2 = 0x0 veer: inst_access_enable0 = 0x0 veer: data_access_mask3 = 0xffffffff veer: inst_access_addr0 = 0x00000000 veer: inst_access_mask7 = 0xffffffff veer: data_access_addr4 = 0x00000000 veer: inst_access_enable4 = 0x0 veer: inst_access_mask6 = 0xffffffff veer: inst_access_mask5 = 0xffffffff veer: data_access_addr1 = 0x00000000 veer: inst_access_mask2 = 0xffffffff veer: inst_access_enable6 = 0x0 veer: inst_access_enable5 = 0x0 veer: data_access_addr3 = 0x00000000 veer: data_access_enable7 = 0x0 veer: inst_access_mask0 = 0xffffffff veer: inst_access_addr7 = 0x00000000 veer: inst_access_enable3 = 0x0 veer: inst_access_enable1 = 0x0 veer: data_access_mask4 = 0xffffffff veer: data_access_mask7 = 0xffffffff veer: inst_access_addr4 = 0x00000000 veer: data_access_addr0 = 0x00000000 veer: data_access_enable2 = 0x0 veer: inst_access_mask3 = 0xffffffff veer: data_access_enable0 = 0x0 veer: data_access_addr6 = 0x00000000 veer: data_access_addr5 = 0x00000000 veer: inst_access_mask1 = 0xffffffff veer: data_access_addr2 = 0x00000000 veer: iccm_offset = 0xe000000 veer: iccm_size = 64 veer: iccm_enable = 1 veer: iccm_num_banks = 4 veer: iccm_region = 0xe veer: dccm_region = 0xf veer: dccm_enable = 1 veer: dccm_num_banks = 8 veer: dccm_offset = 0x40000 veer: dccm_size = 64 veer: ifu_bus_prty = 2 veer: bus_prty_default = 3 veer: sb_bus_prty = 2 veer: ifu_bus_tag = 4 veer: lsu_bus_id = 1 veer: dma_bus_id = 1 veer: sb_bus_id = 1 veer: sb_bus_tag = 1 veer: dma_bus_prty = 2 veer: dma_bus_tag = 1 veer: lsu_bus_prty = 2 veer: ifu_bus_id = 1 veer: lsu_bus_tag = 4 veer: bht_addr_lo = 3 veer: bht_size = 512 veer: load_to_use_bus_plus1 = 0 veer: bitmanip_zbb = 1 veer: div_bit = 4 veer: bitmanip_zbf = 0 veer: load_to_use_plus1 = 0 veer: atomic_enable = 1 veer: opensource = 0 veer: bitmanip_zbp = 0 veer: lsu_stbuf_depth = 10 veer: bitmanip_zbr = 0 veer: bitmanip_zbs = 1 veer: lsu_num_nbload = 8 veer: timer_legal_en = 1 veer: dma_buf_depth = 5 veer: bitmanip_zbe = 0 veer: bitmanip_zbc = 1 veer: fpga_optimize = 1 veer: verilator = veer: no_secondary_alu = 0 veer: fast_interrupt_redirect = 1 veer: div_new = 1 veer: num_threads = 1 veer: bitmanip_zba = 1 veer: btb_fullya = 0 veer: btb_bypass_enable = 1 veer: btb_num_bypass = 8 veer: btb_index1_lo = 3 veer: btb_addr_lo = 3 veer: btb_use_sram = 0 veer: btb_size = 128 veer: btb_toffset_size = 12 veer: pic_region = 0xf veer: pic_meipl_offset = 0x0000 veer: pic_meipl_mask = 0xf veer: pic_meigwclr_offset = 0x5000 veer: pic_size = 32 veer: pic_offset = 0xc0000 veer: pic_meidels_offset = 0x6000 veer: pic_meitp_mask = 0x0 veer: pic_mpiccfg_offset = 0x3000 veer: pic_meitp_offset = 0x1800 veer: pic_total_int = 127 veer: pic_meip_mask = 0x0 veer: pic_meip_offset = 0x1000 veer: pic_mpiccfg_count = 1 veer: pic_meigwctrl_offset = 0x4000 veer: pic_mpiccfg_mask = 0x1 veer: pic_meie_offset = 0x2000 veer: pic_meigwclr_mask = 0x0 veer: pic_meidels_mask = 0x1 veer: pic_2cycle = 1 veer: pic_meigwctrl_mask = 0x3 veer: pic_meie_mask = 0x1 veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/eh2_pdef.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/eh2_param.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/common_defines.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/defines.h veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/pd_defines.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/whisper.json veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/perl_configs.pl veer: Writing /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/snapshots/default/link.ld [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 [Pipeline] { [Pipeline] echo simulation not supported for System Verilog files [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/eh2_veer.sv Cache-related signals in eh2_veer.sv Cache-related signals in eh2_mem.sv Cache-related signals in eh2_veer_wrapper.sv Cache-related signals in eh2_dma_ctrl.sv Cache-related signals in axi4_to_ahb.sv Cache-related signals in ahb_to_axi4.sv Cache-related signals in eh2_lsu_addrcheck.sv Cache-related signals in eh2_lsu_trigger.sv Cache-related signals in eh2_lsu_amo.sv Cache-related signals in eh2_lsu_dccm_ctl.sv Cache-related signals in eh2_lsu_stbuf.sv Cache-related signals in eh2_lsu_ecc.sv Cache-related signals in eh2_lsu.sv Cache-related signals in eh2_lsu_lsc_ctl.sv Cache-related signals in eh2_lsu_bus_intf.sv Cache-related signals in eh2_lsu_bus_buffer.sv Cache-related signals in eh2_lsu_clkdomain.sv Cache-related signals in eh2_dec_csr.sv Cache-related signals in eh2_dec_decode_ctl.sv Cache-related signals in eh2_dec_tlu_top.sv Cache-related signals in eh2_dec_tlu_ctl.sv Cache-related signals in eh2_dec_ib_ctl.sv Cache-related signals in eh2_dec.sv Cache-related signals in eh2_dbg.sv Cache-related signals in eh2_def.sv Cache-related signals in eh2_ifu_ic_mem.sv Cache-related signals in eh2_ifu.sv Cache-related signals in eh2_ifu_btb_mem.sv Cache-related signals in eh2_ifu_bp_ctl.sv Cache-related signals in eh2_ifu_ifc_ctl.sv Cache-related signals in eh2_ifu_mem_ctl.sv Cache-related signals in eh2_ifu_aln_ctl.sv Cache-related signals in eh2_ifu_iccm_mem.sv Cache-related signals in eh2_exu.sv Cache-related signals in eh2_exu_div_ctl.sv Cache-related signals in eh2_exu_alu_ctl.sv Cache-related signals in eh2_exu_mul_ctl.sv Results saved to /jenkins/processor_ci_utils/labels/Cores-SweRV-EH2.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Cores-SweRV-EH2 -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Error executing Makefile. ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dmi/dmi_jtag_to_core_sync.v:51] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/Cores-SweRV-EH2/Cores-SweRV-EH2/design/dmi/dmi_jtag_to_core_sync.v:52] ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260] ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Cores-SweRV-EH2.sv:6] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 142, in <module> main( File "/eda/processor_ci/main.py", line 89, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 296, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: b24eef46-d49f-4eb0-9ae5-a98cf2d7a6e6 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE