Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/Baby-Risco-5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf Baby-Risco-5 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/JN513/Baby-Risco-5 Baby-Risco-5 Cloning into 'Baby-Risco-5'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Core src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/immediate_generator.v src/core/registers.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v Results saved to /jenkins/processor_ci_utils/labels/Baby-Risco-5.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Baby-Risco-5 -b colorlight_i9 + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Baby-Risco-5 -b digilent_arty_a7_100t File 'processor_ci_defines.vh' generated for board: 'colorlight_i9'. Final configuration file generated at /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/synlig -c /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_colorlight_i9.tcl 1. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v Parsing Verilog input from `/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 7. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/slpp_all/surelog.log". [NTE:PP0128] /eda/processor_ci/rtl/Baby-Risco-5.sv:96:24: Non ASCII character detected, replaced by space. [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 1 8. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/modules/uart.sv' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/fifo.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/fifo.sv' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/reset.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/reset.sv' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/clk_divider.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/clk_divider.sv' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/memory.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/memory.sv' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/interpreter.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/interpreter.sv' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/rtl/controller.sv Parsing SystemVerilog input from `/eda/processor-ci-controller/rtl/controller.sv' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 17. Executing SystemVerilog frontend. [INF:CM0023] Creating log file "/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/slpp_all/surelog.log". [INF:CP0300] Compilation... [INF:CP0303] /eda/processor_ci/rtl/Baby-Risco-5.sv:5:1: Compile module "work@processorci_top". [INF:EL0526] Design Elaboration... [NTE:EL0503] /eda/processor_ci/rtl/Baby-Risco-5.sv:5:1: Top level module "work@processorci_top". [WRN:EL0500] /eda/processor_ci/rtl/Baby-Risco-5.sv:57:1: Cannot find a module definition for "work@processorci_top::Controller". [WRN:EL0500] /eda/processor_ci/rtl/Baby-Risco-5.sv:121:1: Cannot find a module definition for "work@processorci_top::Core". [WRN:EL0500] /eda/processor_ci/rtl/Baby-Risco-5.sv:173:1: Cannot find a module definition for "work@processorci_top::ResetBootSystem". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 2. [NTE:EL0510] Nb instances: 4. [NTE:EL0511] Nb leaf instances: 3. [WRN:EL0512] Nb undefined modules: 3. [WRN:EL0513] Nb undefined instances: 3. [INF:UH0706] Creating UHDM Model... [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 5 [ NOTE] : 5 Generating RTLIL representation for module `\processorci_top'. 18. Executing SYNTH_ECP5 pass. 18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_sim.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 18.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_bb.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 18.3. Executing HIERARCHY pass (managing design hierarchy). 18.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \Core Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Control_Unit Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 18.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 18.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 100000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 18.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 100000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$4f95a2915948f32f9ea8a2df64dc16f0cc4d571e\UART'. Parameter \CLK_FREQ = 100000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 18.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 100000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$87e718ac378c2c007d548c98d7d17dd6861e7cf4\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 18.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter \CYCLES = 20 18.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \BOOT_ADDRESS = 0 18.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 1129270351 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 18.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 1129270351 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller'. 18.3.12. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Control_Unit Used module: $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 18.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 1129270351 Parameter \RESET_CLK_CYCLES = 20 18.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 1129270351 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 18.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 18.3.16. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Control_Unit Used module: $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 18.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 18.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Control_Unit Used module: $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 18.3.20. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Registers Used module: \Control_Unit Used module: $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$87e718ac378c2c007d548c98d7d17dd6861e7cf4\Interpreter'. Removing unused module `$paramod$4f95a2915948f32f9ea8a2df64dc16f0cc4d571e\UART'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removing unused module `\Core'. Removed 15 unused modules. 18.4. Executing PROC pass (convert processes to netlists). 18.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$414'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:0$659'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:0$659'. Cleaned up 2 empty switches. 18.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$521 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/controller.sv:158$765 in module $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/reset.sv:28$724 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$921 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$913 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$910 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$904 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$894 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$885 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$872 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$870 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$862 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$848 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$837 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/memory.sv:35$650 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788 in module $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50 in module Registers. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:18$45 in module Immediate_Generator. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.sv:192$783 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.sv:192$783 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.sv:169$778 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.sv:114$773 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.sv:56$768 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31 in module Control_Unit. Marked 6 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:54$28 in module Control_Unit. Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:26$3 in module Alu. Removed a total of 3 dead cases. 18.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 68 assignments to connections. 18.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$522'. Set init value: \Q = 1'0 Found init rule in `\processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:141$297'. Set init value: \clk_o = 1'0 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:0$730'. Set init value: \state = 2'01 Set init value: \rst_o = 1'0 Set init value: \counter = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$925'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$878'. Set init value: \i = 0 18.4.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \rst_n in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827'. Found async reset \rst_n in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. 18.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~111 debug messages> 18.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$522'. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$521'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. Creating decoders for process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473'. 1/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_EN[3:0]$479 2/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_DATA[3:0]$478 3/3: $1$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_ADDR[3:0]$477 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_EN[3:0]$421 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_DATA[3:0]$420 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_ADDR[3:0]$419 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$414'. Creating decoders for process `\processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:141$297'. Creating decoders for process `\processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:164$293'. Creating decoders for process `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller.$proc$/eda/processor-ci-controller/rtl/controller.sv:158$765'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. 1/3: $0\InstructionReg[31:0] 2/3: $0\PCOld[31:0] 3/3: $0\PC[31:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739'. 1/2: $0\alu_input_b[31:0] 2/2: $0\alu_input_a[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:0$730'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. 1/3: $0\counter[5:0] 2/3: $0\rst_o[0:0] 3/3: $0\state[1:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$925'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$921'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$913'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$910'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$904'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$894'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$885'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$878'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$872'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$870'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$862'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$848'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$837'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. 1/3: $1$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$658 2/3: $1$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_DATA[31:0]$657 3/3: $1$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_ADDR[9:0]$656 Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$637 2/7: $2$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_DATA[7:0]$636 3/7: $2$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_ADDR[2:0]$635 4/7: $1$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$632 5/7: $1$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_DATA[7:0]$631 6/7: $1$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_ADDR[2:0]$630 7/7: $0\write_ptr[3:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619'. 1/2: $0\read_ptr[3:0] 2/2: $0\read_data_o[7:0] Creating decoders for process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\return_state[7:0] 10/28: $0\temp_buffer[63:0] 11/28: $0\accumulator[63:0] 12/28: $0\timeout_counter[31:0] 13/28: $0\timeout[31:0] 14/28: $0\read_buffer[31:0] 15/28: $0\communication_buffer[31:0] 16/28: $0\num_of_positions[23:0] 17/28: $0\num_of_pages[23:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\counter[7:0] 27/28: $0\write_data[31:0] 28/28: $0\address[31:0] Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. 1/3: $1$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$58 2/3: $1$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_DATA[31:0]$57 3/3: $1$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_ADDR[4:0]$56 Creating decoders for process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:18$45'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_read_fifo_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:169$778'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_data_in[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_data_in[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. 1/13: $0\is_immediate[0:0] 2/13: $0\reg_write[0:0] 3/13: $0\alu_src_a[1:0] 4/13: $0\alu_src_b[1:0] 5/13: $0\aluop[1:0] 6/13: $0\pc_source[0:0] 7/13: $0\memory_to_reg[0:0] 8/13: $0\memory_write[0:0] 9/13: $0\memory_read[0:0] 10/13: $0\lorD[0:0] 11/13: $0\ir_write[0:0] 12/13: $0\pc_write[0:0] 13/13: $0\pc_write_cond[0:0] Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:54$28'. 1/1: $0\state[3:0] Creating decoders for process `\ALU_Control.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23'. 1/1: $0\aluop_out[3:0] Creating decoders for process `\Alu.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:26$3'. 1/1: $0\ALU_out_S[31:0] 18.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_input_a' from process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739'. No latch inferred for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_input_b' from process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$894'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$837'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:18$45'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23'. No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:26$3'. 18.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$521'. created $dff cell `$procdff$2521' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$457_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$458_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$459_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$460_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$461_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$462_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$463_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$464_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$465_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$466_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$467_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$468_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$469_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$470_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:281$471_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_ADDR' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473'. created $dff cell `$procdff$2522' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_DATA' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473'. created $dff cell `$procdff$2523' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/share/synlig/ecp5/cells_sim.v:287$472_EN' using process `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473'. created $dff cell `$procdff$2524' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$397_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$398_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$399_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$400_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$401_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$402_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$403_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$404_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$405_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$406_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$407_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$408_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$409_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$410_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$411_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$412_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415'. created $dff cell `$procdff$2525' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415'. created $dff cell `$procdff$2526' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$413_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415'. created $dff cell `$procdff$2527' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$414'. created direct connection (no actual register cell created). Creating register for signal `\processorci_top.\clk_o' using process `\processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:164$293'. created $dff cell `$procdff$2528' with positive edge clock. Creating register for signal `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller.\finish_execution' using process `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller.$proc$/eda/processor-ci-controller/rtl/controller.sv:158$765'. created $dff cell `$procdff$2529' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\PC' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2530' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\PCOld' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2531' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\RS1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2532' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\RS2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2533' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\ALUOutReg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2534' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\MemoryReg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2535' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\InstructionReg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. created $dff cell `$procdff$2536' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. created $dff cell `$procdff$2537' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\rst_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. created $dff cell `$procdff$2538' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. created $dff cell `$procdff$2539' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923'. created $dff cell `$procdff$2540' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923'. created $dff cell `$procdff$2541' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$921'. created $dff cell `$procdff$2542' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$913'. created $dff cell `$procdff$2543' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$910'. created $dff cell `$procdff$2544' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$904'. created $dff cell `$procdff$2545' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899'. created $dff cell `$procdff$2546' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899'. created $dff cell `$procdff$2547' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$885'. created $dff cell `$procdff$2548' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$872'. created $dff cell `$procdff$2549' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$870'. created $dff cell `$procdff$2550' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$862'. created $dff cell `$procdff$2551' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$848'. created $dff cell `$procdff$2552' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842'. created $dff cell `$procdff$2553' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842'. created $dff cell `$procdff$2554' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827'. created $adff cell `$procdff$2559' with positive edge clock and positive level reset. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. created $adff cell `$procdff$2564' with positive edge clock and positive level reset. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. created $adff cell `$procdff$2569' with positive edge clock and positive level reset. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. created $dff cell `$procdff$2570' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. created $dff cell `$procdff$2571' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. created $dff cell `$procdff$2572' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. created $dff cell `$procdff$2573' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. created $dff cell `$procdff$2574' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. created $dff cell `$procdff$2575' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. created $dff cell `$procdff$2576' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data_o' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619'. created $dff cell `$procdff$2577' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619'. created $dff cell `$procdff$2578' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\memory_read' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2579' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\memory_write' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2580' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\state' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2581' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\address' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2582' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\write_data' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2583' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\counter' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2584' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\write_pulse' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2585' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\communication_read' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2586' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\communication_write' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2587' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\communication_write_data' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2588' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\core_clk_enable' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2589' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\core_reset' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2590' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2591' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\reset_bus' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2592' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\bus_mode' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2593' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\memory_page_size' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2594' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\end_position' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2595' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\memory_mux_selector' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2596' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\memory_page_number' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2597' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\num_of_pages' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2598' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\num_of_positions' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2599' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\communication_buffer' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2600' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\read_buffer' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2601' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\timeout' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2602' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\timeout_counter' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2603' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\accumulator' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2604' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\temp_buffer' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2605' with positive edge clock. Creating register for signal `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.\return_state' using process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. created $dff cell `$procdff$2606' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_ADDR' using process `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. created $dff cell `$procdff$2607' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_DATA' using process `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. created $dff cell `$procdff$2608' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. created $dff cell `$procdff$2609' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:22$47_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. created $dff cell `$procdff$2610' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. created $dff cell `$procdff$2611' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. created $dff cell `$procdff$2612' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. created $dff cell `$procdff$2613' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_read_fifo_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. created $dff cell `$procdff$2614' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:169$778'. created $dff cell `$procdff$2615' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_data_in' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:169$778'. created $dff cell `$procdff$2616' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2617' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2618' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_data_in' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2619' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2620' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2621' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. created $dff cell `$procdff$2622' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. created $dff cell `$procdff$2623' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. created $dff cell `$procdff$2624' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. created $dff cell `$procdff$2625' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. created $dff cell `$procdff$2626' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. created $dff cell `$procdff$2627' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:54$28'. created $dff cell `$procdff$2628' with positive edge clock. 18.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$522'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$521'. Removing empty process `TRELLIS_FF.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:350$521'. Removing empty process `DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$496'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:285$473'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$439'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$415'. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$414'. Removing empty process `processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:141$297'. Removing empty process `processorci_top.$proc$/eda/processor_ci/rtl/Baby-Risco-5.sv:164$293'. Found and cleaned up 4 empty switches in `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller.$proc$/eda/processor-ci-controller/rtl/controller.sv:158$765'. Removing empty process `$paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller.$proc$/eda/processor-ci-controller/rtl/controller.sv:158$765'. Found and cleaned up 3 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:109$740'. Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:37$739'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:0$730'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/rtl/reset.sv:28$724'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$925'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$923'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$921'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$921'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$913'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$913'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$910'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$910'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$904'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$904'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$899'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$894'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$894'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$885'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$885'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$878'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$872'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$872'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$870'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$870'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$862'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$862'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$848'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$848'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$842'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$837'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$837'. Found and cleaned up 3 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:48$827'. Found and cleaned up 3 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/rtl/clk_divider.sv:27$817'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/rtl/memory.sv:35$650'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:39$625'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/rtl/fifo.sv:28$619'. Found and cleaned up 15 empty switches in `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. Removing empty process `$paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter.$proc$/eda/processor-ci-controller/rtl/interpreter.sv:110$788'. Found and cleaned up 1 empty switch in `\Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:17$50'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:18$45'. Removing empty process `Immediate_Generator.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:18$45'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:192$783'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:169$778'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:169$778'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:114$773'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.sv:56$768'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:108$31'. Found and cleaned up 6 empty switches in `\Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:54$28'. Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:54$28'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23'. Removing empty process `ALU_Control.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:9$23'. Found and cleaned up 1 empty switch in `\Alu.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:26$3'. Removing empty process `Alu.$proc$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:26$3'. Cleaned up 111 empty switches. 18.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. Optimizing module $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller. <suppressed ~5 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~10 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~6 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~9 debug messages> Optimizing module $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter. <suppressed ~34 debug messages> Optimizing module Registers. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~35 debug messages> Optimizing module Control_Unit. <suppressed ~3 debug messages> Optimizing module ALU_Control. <suppressed ~4 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> 18.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$a98c0be7345da9e874aad63ec0ad79675335e6c4\Controller. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$c1a834051cc8b9b52c6fdccabf551f9edb03a3b1\Interpreter. Deleting now unused module Registers. Deleting now unused module Immediate_Generator. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. <suppressed ~16 debug messages> 18.6. Executing TRIBUF pass. 18.7. Executing DEMINOUT pass (demote inout ports to input or output). 18.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~129 debug messages> 18.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 68 unused cells and 597 unused wires. <suppressed ~97 debug messages> 18.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [31] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [30] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [29] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [28] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [27] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [26] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [25] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [24] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [23] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [22] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [21] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [20] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [19] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [18] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [17] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [16] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [15] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [14] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [13] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [12] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [11] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [10] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [9] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [8] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [7] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [6] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [5] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [4] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [3] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [2] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [1] is used but has no driver. Warning: Wire processorci_top.\u_Controller.data_memory_read_data [0] is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Found and reported 35 problems. 18.11. Executing OPT pass (performing simple optimizations). 18.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~621 debug messages> Removed a total of 207 cells. 18.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\Core.\Immediate_Generator.$procmux$2110. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1330. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1336. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1342. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1330. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1336. dead port 1/2 on $mux $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1342. Removed 7 multiplexer ports. <suppressed ~126 debug messages> 18.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\u_Controller.\Core_Memory.$procmux$1318: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 New ports: A=1'0, B=1'1, Y=$flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] New connections: $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [31:1] = { $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] $flatten\u_Controller.\Core_Memory.$0$memwr$\memory$/eda/processor-ci-controller/rtl/memory.sv:37$643_EN[31:0]$653 [0] } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1370: { $flatten\u_Controller.\Interpreter.$procmux$1464_CMP $flatten\u_Controller.\Interpreter.$procmux$1460_CMP $flatten\u_Controller.\Interpreter.$procmux$1456_CMP $flatten\u_Controller.\Interpreter.$procmux$1430_CMP $flatten\u_Controller.\Interpreter.$procmux$1429_CMP $flatten\u_Controller.\Interpreter.$procmux$1425_CMP $flatten\u_Controller.\Interpreter.$procmux$1424_CMP $flatten\u_Controller.\Interpreter.$procmux$1420_CMP $flatten\u_Controller.\Interpreter.$procmux$1410_CMP $flatten\u_Controller.\Interpreter.$procmux$1406_CMP $auto$opt_reduce.cc:137:opt_pmux$2656 $flatten\u_Controller.\Interpreter.$procmux$1401_CMP $flatten\u_Controller.\Interpreter.$procmux$1400_CMP $auto$opt_reduce.cc:137:opt_pmux$2654 $flatten\u_Controller.\Interpreter.$procmux$1395_CMP $flatten\u_Controller.\Interpreter.$procmux$1394_CMP $flatten\u_Controller.\Interpreter.$procmux$1389_CMP $flatten\u_Controller.\Interpreter.$procmux$1385_CMP $flatten\u_Controller.\Interpreter.$procmux$1384_CMP $auto$opt_reduce.cc:137:opt_pmux$2652 $flatten\u_Controller.\Interpreter.$procmux$1378_CMP $flatten\u_Controller.\Interpreter.$procmux$1377_CMP $flatten\u_Controller.\Interpreter.$procmux$1376_CMP $auto$opt_reduce.cc:137:opt_pmux$2650 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1470: $auto$opt_reduce.cc:137:opt_pmux$2658 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1494: $auto$opt_reduce.cc:137:opt_pmux$2660 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1516: $auto$opt_reduce.cc:137:opt_pmux$2662 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1527: $auto$opt_reduce.cc:137:opt_pmux$2664 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1575: $auto$opt_reduce.cc:137:opt_pmux$2666 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1617: $auto$opt_reduce.cc:137:opt_pmux$2668 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1625: { $flatten\u_Controller.\Interpreter.$procmux$1396_CMP $flatten\u_Controller.\Interpreter.$procmux$1389_CMP $flatten\u_Controller.\Interpreter.$procmux$1378_CMP $flatten\u_Controller.\Interpreter.$procmux$1372_CMP $auto$opt_reduce.cc:137:opt_pmux$2670 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2315: $auto$opt_reduce.cc:137:opt_pmux$2672 New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2325: $auto$opt_reduce.cc:137:opt_pmux$2674 New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2328: { $auto$opt_reduce.cc:137:opt_pmux$2678 $auto$opt_reduce.cc:137:opt_pmux$2676 $flatten\Core.\Control_Unit.$procmux$2329_CMP } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1660: { $flatten\u_Controller.\Interpreter.$procmux$1410_CMP $auto$opt_reduce.cc:137:opt_pmux$2680 $flatten\u_Controller.\Interpreter.$procmux$1400_CMP } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1713: { $auto$opt_reduce.cc:137:opt_pmux$2684 $auto$opt_reduce.cc:137:opt_pmux$2682 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2339: { $auto$opt_reduce.cc:137:opt_pmux$2688 $auto$opt_reduce.cc:137:opt_pmux$2686 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1782: $auto$opt_reduce.cc:137:opt_pmux$2690 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1807: { $flatten\u_Controller.\Interpreter.$procmux$1410_CMP $auto$opt_reduce.cc:137:opt_pmux$2692 $flatten\u_Controller.\Interpreter.$procmux$1400_CMP } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2353: { $auto$opt_reduce.cc:137:opt_pmux$2694 $flatten\Core.\Control_Unit.$procmux$2333_CMP } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2359: $auto$opt_reduce.cc:137:opt_pmux$2696 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1849: { $auto$opt_reduce.cc:137:opt_pmux$2700 $auto$opt_reduce.cc:137:opt_pmux$2698 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2397: $auto$opt_reduce.cc:137:opt_pmux$2702 New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2411: $auto$opt_reduce.cc:137:opt_pmux$2704 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1931: { $flatten\u_Controller.\Interpreter.$procmux$1390_CMP $auto$opt_reduce.cc:137:opt_pmux$2706 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2432: $auto$opt_reduce.cc:137:opt_pmux$2708 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1942: { $flatten\u_Controller.\Interpreter.$procmux$1531_CMP $flatten\u_Controller.\Interpreter.$procmux$1430_CMP $auto$opt_reduce.cc:137:opt_pmux$2710 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1952: { $flatten\u_Controller.\Interpreter.$procmux$1429_CMP $auto$opt_reduce.cc:137:opt_pmux$2714 $auto$opt_reduce.cc:137:opt_pmux$2712 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2443: { $flatten\Core.\Control_Unit.$procmux$2400_CMP $flatten\Core.\Control_Unit.$procmux$2348_CMP $flatten\Core.\Control_Unit.$procmux$2338_CMP $flatten\Core.\Control_Unit.$procmux$2337_CMP $flatten\Core.\Control_Unit.$procmux$2398_CMP $flatten\Core.\Control_Unit.$procmux$2385_CMP $flatten\Core.\Control_Unit.$procmux$2332_CMP $auto$opt_reduce.cc:137:opt_pmux$2716 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$2028: { $auto$opt_reduce.cc:137:opt_pmux$2718 $flatten\u_Controller.\Interpreter.$procmux$1429_CMP } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$2052: { $flatten\u_Controller.\Interpreter.$procmux$1497_CMP $flatten\u_Controller.\Interpreter.$procmux$1496_CMP $auto$opt_reduce.cc:137:opt_pmux$2720 } New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2461: { $auto$opt_reduce.cc:137:opt_pmux$2722 $flatten\Core.\Control_Unit.$procmux$2468_CMP $flatten\Core.\Control_Unit.$procmux$2467_CMP $flatten\Core.\Control_Unit.$procmux$2466_CMP $flatten\Core.\Control_Unit.$procmux$2465_CMP $flatten\Core.\Control_Unit.$procmux$2464_CMP $flatten\Core.\Control_Unit.$procmux$2463_CMP $flatten\Core.\Control_Unit.$procmux$2462_CMP } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$2078: { $auto$opt_reduce.cc:137:opt_pmux$2724 $flatten\u_Controller.\Interpreter.$procmux$1496_CMP $flatten\u_Controller.\Interpreter.$procmux$1415_CMP $flatten\u_Controller.\Interpreter.$procmux$1410_CMP $flatten\u_Controller.\Interpreter.$procmux$1400_CMP } New ctrl vector for $pmux cell $flatten\u_Controller.\Uart.$procmux$2179: $auto$opt_reduce.cc:137:opt_pmux$2726 New ctrl vector for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2113: { $flatten\Core.\Control_Unit.$procmux$2465_CMP $flatten\Core.\Control_Unit.$procmux$2466_CMP $auto$opt_reduce.cc:137:opt_pmux$2730 $flatten\Core.\Control_Unit.$procmux$2467_CMP $auto$opt_reduce.cc:137:opt_pmux$2728 $flatten\Core.\Immediate_Generator.$procmux$2115_CMP $flatten\Core.\Control_Unit.$procmux$2469_CMP } Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2093: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_EN[31:0]$53 [0] } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y New ports: A=1'0, B=1'1, Y=$flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] New connections: $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [7:1] = { $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0] } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y New ports: A=1'0, B=1'1, Y=$flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] New connections: $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [7:1] = { $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0] } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1345: Old ports: A=$flatten\u_Controller.\Uart.\rx_fifo.$2$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$637, B=8'00000000, Y=$flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 New ports: A=$flatten\u_Controller.\Uart.\rx_fifo.$procmux$1327_Y [0], B=1'0, Y=$flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] New connections: $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [7:1] = { $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\rx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1345: Old ports: A=$flatten\u_Controller.\Uart.\tx_fifo.$2$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$637, B=8'00000000, Y=$flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 New ports: A=$flatten\u_Controller.\Uart.\tx_fifo.$procmux$1327_Y [0], B=1'0, Y=$flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] New connections: $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [7:1] = { $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] $flatten\u_Controller.\Uart.\tx_fifo.$0$memwr$\memory$/eda/processor-ci-controller/rtl/fifo.sv:43$618_EN[7:0]$628 [0] } Optimizing cells in module \processorci_top. Performed a total of 38 changes. 18.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~33 debug messages> Removed a total of 11 cells. 18.11.6. Executing OPT_DFF pass (perform DFF optimizations). 18.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 222 unused wires. <suppressed ~1 debug messages> 18.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 18.11.9. Rerunning OPT passes. (Maybe there is more to do..) 18.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~125 debug messages> 18.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Core.\Alu.$procmux$2506: { $flatten\Core.\Alu.$procmux$2520_CMP $flatten\Core.\Alu.$procmux$2519_CMP $flatten\Core.\Alu.$procmux$2518_CMP $flatten\Core.\Alu.$procmux$2517_CMP $auto$opt_reduce.cc:137:opt_pmux$2734 $flatten\Core.\Alu.$procmux$2514_CMP $flatten\Core.\Alu.$procmux$2513_CMP $flatten\Core.\Alu.$procmux$2512_CMP $flatten\Core.\Alu.$procmux$2511_CMP $flatten\Core.\Alu.$procmux$2510_CMP $flatten\Core.\Alu.$procmux$2509_CMP $auto$opt_reduce.cc:137:opt_pmux$2732 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1660: { $auto$opt_reduce.cc:137:opt_pmux$2680 $auto$opt_reduce.cc:137:opt_pmux$2736 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1807: { $auto$opt_reduce.cc:137:opt_pmux$2680 $auto$opt_reduce.cc:137:opt_pmux$2738 } New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$2078: { $auto$opt_reduce.cc:137:opt_pmux$2724 $flatten\u_Controller.\Interpreter.$procmux$1496_CMP $flatten\u_Controller.\Interpreter.$procmux$1415_CMP $auto$opt_reduce.cc:137:opt_pmux$2740 } Optimizing cells in module \processorci_top. Performed a total of 4 changes. 18.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 18.11.13. Executing OPT_DFF pass (perform DFF optimizations). 18.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 18.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.16. Rerunning OPT passes. (Maybe there is more to do..) 18.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~125 debug messages> 18.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.11.20. Executing OPT_DFF pass (perform DFF optimizations). 18.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.11.23. Finished OPT passes. (There is nothing left to do.) 18.12. Executing FSM pass (extract and optimize FSM). 18.12.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register processorci_top.Core.Control_Unit.state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Not marking processorci_top.u_Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.u_Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_Controller.Uart.state_read. Found FSM state register processorci_top.u_Controller.Uart.state_write. Found FSM state register processorci_top.u_Controller.Uart.tx_read_fifo_state. 18.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Core.Control_Unit.state' from module `\processorci_top'. found $dff cell for state register: $flatten\Core.\Control_Unit.$procdff$2628 root of input selection tree: $flatten\Core.\Control_Unit.$0\state[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \u_Controller.Interpreter.core_reset found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$2716 found ctrl input: $flatten\Core.\Control_Unit.$procmux$2332_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2385_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2398_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2337_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2338_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2348_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2400_CMP found state code: 4'0000 found state code: 4'0111 found state code: 4'1011 found ctrl input: \Core.Control_Unit.memory_response found state code: 4'0101 found state code: 4'0100 found ctrl input: $flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:83$30_Y found state code: 4'0011 found ctrl input: $flatten\Core.\Control_Unit.$procmux$2462_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2463_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2464_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2465_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2466_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2467_CMP found ctrl input: $flatten\Core.\Control_Unit.$procmux$2468_CMP found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$2722 found state code: 4'1101 found state code: 4'1100 found state code: 4'1010 found state code: 4'1001 found state code: 4'1000 found state code: 4'0110 found state code: 4'0010 found state code: 4'0001 found state code: 4'1111 found ctrl output: $flatten\Core.\Control_Unit.$procmux$2316_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2317_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2326_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2327_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2329_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2330_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2332_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2333_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2334_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2336_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2337_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2338_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2348_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2385_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2398_CMP found ctrl output: $flatten\Core.\Control_Unit.$procmux$2400_CMP ctrl inputs: { $flatten\Core.\Control_Unit.$procmux$2468_CMP $flatten\Core.\Control_Unit.$procmux$2467_CMP $flatten\Core.\Control_Unit.$procmux$2466_CMP $flatten\Core.\Control_Unit.$procmux$2465_CMP $flatten\Core.\Control_Unit.$procmux$2464_CMP $flatten\Core.\Control_Unit.$procmux$2463_CMP $flatten\Core.\Control_Unit.$procmux$2462_CMP $flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:83$30_Y \Core.Control_Unit.memory_response $auto$opt_reduce.cc:137:opt_pmux$2716 $auto$opt_reduce.cc:137:opt_pmux$2722 \u_Controller.Interpreter.core_reset } ctrl outputs: { $flatten\Core.\Control_Unit.$procmux$2400_CMP $flatten\Core.\Control_Unit.$procmux$2398_CMP $flatten\Core.\Control_Unit.$procmux$2385_CMP $flatten\Core.\Control_Unit.$procmux$2348_CMP $flatten\Core.\Control_Unit.$procmux$2338_CMP $flatten\Core.\Control_Unit.$procmux$2337_CMP $flatten\Core.\Control_Unit.$procmux$2336_CMP $flatten\Core.\Control_Unit.$procmux$2334_CMP $flatten\Core.\Control_Unit.$procmux$2333_CMP $flatten\Core.\Control_Unit.$procmux$2332_CMP $flatten\Core.\Control_Unit.$procmux$2330_CMP $flatten\Core.\Control_Unit.$procmux$2329_CMP $flatten\Core.\Control_Unit.$procmux$2327_CMP $flatten\Core.\Control_Unit.$procmux$2326_CMP $flatten\Core.\Control_Unit.$procmux$2317_CMP $flatten\Core.\Control_Unit.$procmux$2316_CMP $flatten\Core.\Control_Unit.$0\state[3:0] } transition: 4'0000 12'--------0--0 -> 4'0000 20'10000000000000000000 transition: 4'0000 12'--------1--0 -> 4'1111 20'10000000000000001111 transition: 4'0000 12'-----------1 -> 4'0000 20'10000000000000000000 transition: 4'1000 12'-----------0 -> 4'0111 20'00000000000000100111 transition: 4'1000 12'-----------1 -> 4'0000 20'00000000000000100000 transition: 4'0100 12'-----------0 -> 4'0000 20'00000000000010000000 transition: 4'0100 12'-----------1 -> 4'0000 20'00000000000010000000 transition: 4'1100 12'-----------0 -> 4'0111 20'00000000001000000111 transition: 4'1100 12'-----------1 -> 4'0000 20'00000000001000000000 transition: 4'0010 12'-------0---0 -> 4'0101 20'00000100000000000101 transition: 4'0010 12'-------1---0 -> 4'0011 20'00000100000000000011 transition: 4'0010 12'-----------1 -> 4'0000 20'00000100000000000000 transition: 4'1010 12'-----------0 -> 4'0000 20'00000000100000000000 transition: 4'1010 12'-----------1 -> 4'0000 20'00000000100000000000 transition: 4'0110 12'-----------0 -> 4'0111 20'00000010000000000111 transition: 4'0110 12'-----------1 -> 4'0000 20'00000010000000000000 transition: 4'0001 12'0000000---00 -> 4'0000 20'00001000000000000000 transition: 4'0001 12'----------10 -> 4'0010 20'00001000000000000010 transition: 4'0001 12'1----------0 -> 4'0110 20'00001000000000000110 transition: 4'0001 12'-1---------0 -> 4'1000 20'00001000000000001000 transition: 4'0001 12'--1--------0 -> 4'1001 20'00001000000000001001 transition: 4'0001 12'---1-------0 -> 4'1010 20'00001000000000001010 transition: 4'0001 12'----1------0 -> 4'1011 20'00001000000000001011 transition: 4'0001 12'-----1-----0 -> 4'1100 20'00001000000000001100 transition: 4'0001 12'------1----0 -> 4'1101 20'00001000000000001101 transition: 4'0001 12'-----------1 -> 4'0000 20'00001000000000000000 transition: 4'1001 12'-----------0 -> 4'0111 20'00000001000000000111 transition: 4'1001 12'-----------1 -> 4'0000 20'00000001000000000000 transition: 4'0101 12'--------0--0 -> 4'0101 20'00100000000000000101 transition: 4'0101 12'--------1--0 -> 4'0000 20'00100000000000000000 transition: 4'0101 12'-----------1 -> 4'0000 20'00100000000000000000 transition: 4'1101 12'-----------0 -> 4'0111 20'00000000000100000111 transition: 4'1101 12'-----------1 -> 4'0000 20'00000000000100000000 transition: 4'0011 12'-----------0 -> 4'0100 20'01000000000000000100 transition: 4'0011 12'-----------1 -> 4'0000 20'01000000000000000000 transition: 4'1011 12'-----------0 -> 4'0111 20'00000000000000010111 transition: 4'1011 12'-----------1 -> 4'0000 20'00000000000000010000 transition: 4'0111 12'-----------0 -> 4'0000 20'00000000000001000000 transition: 4'0111 12'-----------1 -> 4'0000 20'00000000000001000000 transition: 4'1111 12'-----------0 -> 4'0001 20'00010000000000000001 transition: 4'1111 12'-----------1 -> 4'0000 20'00010000000000000000 Extracting FSM `\u_Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2542 root of input selection tree: $flatten\u_Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.rst_o found ctrl input: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$889_Y found ctrl input: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$902_Y found ctrl input: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$915_Y found ctrl input: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$901_Y found state code: 3'000 found ctrl input: \u_Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \u_Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \u_Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$915_Y found ctrl output: $flatten\u_Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$906_Y found ctrl output: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$902_Y found ctrl output: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$901_Y found ctrl output: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$889_Y ctrl inputs: { \ResetBootSystem.rst_o \u_Controller.Uart.i_uart_rx.rxd_reg \u_Controller.Uart.i_uart_rx.next_bit \u_Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$889_Y $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$901_Y $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$902_Y $flatten\u_Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$906_Y $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$915_Y $flatten\u_Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\u_Controller.Uart.state_read' from module `\processorci_top'. found $dff cell for state register: $flatten\u_Controller.\Uart.$procdff$2627 root of input selection tree: $flatten\u_Controller.\Uart.$0\state_read[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \ResetBootSystem.rst_o found ctrl input: $flatten\u_Controller.\Uart.$procmux$2265_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2266_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2258_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2276_CMP found state code: 4'0000 found state code: 4'0011 found state code: 4'0001 found ctrl input: $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:78$770_Y found state code: 4'0010 found ctrl input: \u_Controller.Interpreter.communication_rx_empty found state code: 4'0100 found ctrl input: \u_Controller.Interpreter.communication_read found ctrl output: $flatten\u_Controller.\Uart.$procmux$2244_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2258_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2265_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2266_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2276_CMP ctrl inputs: { \ResetBootSystem.rst_o \u_Controller.Interpreter.communication_read \u_Controller.Interpreter.communication_rx_empty $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:78$770_Y } ctrl outputs: { $flatten\u_Controller.\Uart.$procmux$2276_CMP $flatten\u_Controller.\Uart.$procmux$2266_CMP $flatten\u_Controller.\Uart.$procmux$2265_CMP $flatten\u_Controller.\Uart.$procmux$2258_CMP $flatten\u_Controller.\Uart.$procmux$2244_CMP $flatten\u_Controller.\Uart.$0\state_read[3:0] } transition: 4'0000 4'00-- -> 4'0000 9'100000000 transition: 4'0000 4'01-- -> 4'0001 9'100000001 transition: 4'0000 4'1--- -> 4'0000 9'100000000 transition: 4'0100 4'0--- -> 4'0001 9'010000001 transition: 4'0100 4'1--- -> 4'0000 9'010000000 transition: 4'0010 4'0--- -> 4'0011 9'001000011 transition: 4'0010 4'1--- -> 4'0000 9'001000000 transition: 4'0001 4'0--0 -> 4'0010 9'000100010 transition: 4'0001 4'0-01 -> 4'0100 9'000100100 transition: 4'0001 4'0-11 -> 4'0001 9'000100001 transition: 4'0001 4'1--- -> 4'0000 9'000100000 transition: 4'0011 4'0--- -> 4'0000 9'000010000 transition: 4'0011 4'1--- -> 4'0000 9'000010000 Extracting FSM `\u_Controller.Uart.state_write' from module `\processorci_top'. found $dff cell for state register: $flatten\u_Controller.\Uart.$procdff$2622 root of input selection tree: $flatten\u_Controller.\Uart.$0\state_write[3:0] found reset state: 4'0000 (guessed from mux tree) found ctrl input: \ResetBootSystem.rst_o found ctrl input: $flatten\u_Controller.\Uart.$procmux$2181_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2174_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2193_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2197_CMP found state code: 4'0000 found state code: 4'0011 found ctrl input: $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:141$775_Y found state code: 4'0010 found state code: 4'0101 found ctrl input: \u_Controller.Interpreter.communication_write found state code: 4'0100 found ctrl output: $flatten\u_Controller.\Uart.$procmux$2174_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2180_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2181_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2193_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2197_CMP ctrl inputs: { \ResetBootSystem.rst_o \u_Controller.Interpreter.communication_write $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:141$775_Y } ctrl outputs: { $flatten\u_Controller.\Uart.$procmux$2197_CMP $flatten\u_Controller.\Uart.$procmux$2193_CMP $flatten\u_Controller.\Uart.$procmux$2181_CMP $flatten\u_Controller.\Uart.$procmux$2180_CMP $flatten\u_Controller.\Uart.$procmux$2174_CMP $flatten\u_Controller.\Uart.$0\state_write[3:0] } transition: 4'0000 3'00- -> 4'0000 9'100000000 transition: 4'0000 3'01- -> 4'0100 9'100000100 transition: 4'0000 3'1-- -> 4'0000 9'100000000 transition: 4'0100 3'0-- -> 4'0101 9'010000101 transition: 4'0100 3'1-- -> 4'0000 9'010000000 transition: 4'0010 3'0-- -> 4'0011 9'001000011 transition: 4'0010 3'1-- -> 4'0000 9'001000000 transition: 4'0101 3'0-0 -> 4'0010 9'000010010 transition: 4'0101 3'0-1 -> 4'0101 9'000010101 transition: 4'0101 3'1-- -> 4'0000 9'000010000 transition: 4'0011 3'0-- -> 4'0000 9'000100000 transition: 4'0011 3'1-- -> 4'0000 9'000100000 Extracting FSM `\u_Controller.Uart.tx_read_fifo_state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_Controller.\Uart.$procdff$2614 root of input selection tree: $flatten\u_Controller.\Uart.$0\tx_read_fifo_state[1:0] found ctrl input: \ResetBootSystem.rst_o found ctrl input: $flatten\u_Controller.\Uart.$procmux$2140_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2135_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2142_CMP found ctrl input: $flatten\u_Controller.\Uart.$procmux$2129_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\u_Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.sv:201$787_Y found state code: 2'01 found ctrl output: $flatten\u_Controller.\Uart.$procmux$2129_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2135_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2140_CMP found ctrl output: $flatten\u_Controller.\Uart.$procmux$2142_CMP ctrl inputs: { \ResetBootSystem.rst_o $flatten\u_Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.sv:201$787_Y } ctrl outputs: { $flatten\u_Controller.\Uart.$procmux$2142_CMP $flatten\u_Controller.\Uart.$procmux$2140_CMP $flatten\u_Controller.\Uart.$procmux$2135_CMP $flatten\u_Controller.\Uart.$procmux$2129_CMP $flatten\u_Controller.\Uart.$0\tx_read_fifo_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'10 6'001010 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'01 6'100001 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'11 6'010011 18.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\u_Controller.Uart.tx_read_fifo_state$2780' from module `\processorci_top'. Optimizing FSM `$fsm$\u_Controller.Uart.state_write$2773' from module `\processorci_top'. Merging pattern 3'0-- and 3'1-- from group (4 0 9'000100000). Merging pattern 3'1-- and 3'0-- from group (4 0 9'000100000). Optimizing FSM `$fsm$\u_Controller.Uart.state_read$2766' from module `\processorci_top'. Merging pattern 4'0--- and 4'1--- from group (4 0 9'000010000). Merging pattern 4'1--- and 4'0--- from group (4 0 9'000010000). Optimizing FSM `$fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759' from module `\processorci_top'. Optimizing FSM `$fsm$\Core.Control_Unit.state$2741' from module `\processorci_top'. Merging pattern 12'-----------0 and 12'-----------1 from group (2 0 20'00000000000010000000). Merging pattern 12'-----------1 and 12'-----------0 from group (2 0 20'00000000000010000000). Merging pattern 12'-----------0 and 12'-----------1 from group (5 0 20'00000000100000000000). Merging pattern 12'-----------1 and 12'-----------0 from group (5 0 20'00000000100000000000). Merging pattern 12'-----------0 and 12'-----------1 from group (13 0 20'00000000000001000000). Merging pattern 12'-----------1 and 12'-----------0 from group (13 0 20'00000000000001000000). Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$2716. 18.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 60 unused cells and 60 unused wires. <suppressed ~61 debug messages> 18.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Core.Control_Unit.state$2741' from module `\processorci_top'. Removing unused output signal $flatten\Core.\Control_Unit.$0\state[3:0] [0]. Removing unused output signal $flatten\Core.\Control_Unit.$0\state[3:0] [1]. Removing unused output signal $flatten\Core.\Control_Unit.$0\state[3:0] [2]. Removing unused output signal $flatten\Core.\Control_Unit.$0\state[3:0] [3]. Optimizing FSM `$fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759' from module `\processorci_top'. Removing unused output signal $flatten\u_Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\u_Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\u_Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\u_Controller.Uart.state_read$2766' from module `\processorci_top'. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_read[3:0] [0]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_read[3:0] [1]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_read[3:0] [2]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_read[3:0] [3]. Removing unused output signal $flatten\u_Controller.\Uart.$procmux$2265_CMP. Removing unused output signal $flatten\u_Controller.\Uart.$procmux$2266_CMP. Optimizing FSM `$fsm$\u_Controller.Uart.state_write$2773' from module `\processorci_top'. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_write[3:0] [0]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_write[3:0] [1]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_write[3:0] [2]. Removing unused output signal $flatten\u_Controller.\Uart.$0\state_write[3:0] [3]. Optimizing FSM `$fsm$\u_Controller.Uart.tx_read_fifo_state$2780' from module `\processorci_top'. Removing unused output signal $flatten\u_Controller.\Uart.$0\tx_read_fifo_state[1:0] [0]. Removing unused output signal $flatten\u_Controller.\Uart.$0\tx_read_fifo_state[1:0] [1]. Removing unused output signal $flatten\u_Controller.\Uart.$procmux$2140_CMP. Removing unused output signal $flatten\u_Controller.\Uart.$procmux$2142_CMP. 18.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Core.Control_Unit.state$2741' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> --------------1 1000 -> -------------1- 0100 -> ------------1-- 1100 -> -----------1--- 0010 -> ----------1---- 1010 -> ---------1----- 0110 -> --------1------ 0001 -> -------1------- 1001 -> ------1-------- 0101 -> -----1--------- 1101 -> ----1---------- 0011 -> ---1----------- 1011 -> --1------------ 0111 -> -1------------- 1111 -> 1-------------- Recoding FSM `$fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\u_Controller.Uart.state_read$2766' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ----1 0100 -> ---1- 0010 -> --1-- 0001 -> -1--- 0011 -> 1---- Recoding FSM `$fsm$\u_Controller.Uart.state_write$2773' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> ----1 0100 -> ---1- 0010 -> --1-- 0101 -> -1--- 0011 -> 1---- Recoding FSM `$fsm$\u_Controller.Uart.tx_read_fifo_state$2780' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- 18.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Core.Control_Unit.state$2741' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Core.Control_Unit.state$2741 (\Core.Control_Unit.state): Number of input signals: 11 Number of output signals: 16 Number of state bits: 15 Input signals: 0: \u_Controller.Interpreter.core_reset 1: $auto$opt_reduce.cc:137:opt_pmux$2722 2: \Core.Control_Unit.memory_response 3: $flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:83$30_Y 4: $flatten\Core.\Control_Unit.$procmux$2462_CMP 5: $flatten\Core.\Control_Unit.$procmux$2463_CMP 6: $flatten\Core.\Control_Unit.$procmux$2464_CMP 7: $flatten\Core.\Control_Unit.$procmux$2465_CMP 8: $flatten\Core.\Control_Unit.$procmux$2466_CMP 9: $flatten\Core.\Control_Unit.$procmux$2467_CMP 10: $flatten\Core.\Control_Unit.$procmux$2468_CMP Output signals: 0: $flatten\Core.\Control_Unit.$procmux$2316_CMP 1: $flatten\Core.\Control_Unit.$procmux$2317_CMP 2: $flatten\Core.\Control_Unit.$procmux$2326_CMP 3: $flatten\Core.\Control_Unit.$procmux$2327_CMP 4: $flatten\Core.\Control_Unit.$procmux$2329_CMP 5: $flatten\Core.\Control_Unit.$procmux$2330_CMP 6: $flatten\Core.\Control_Unit.$procmux$2332_CMP 7: $flatten\Core.\Control_Unit.$procmux$2333_CMP 8: $flatten\Core.\Control_Unit.$procmux$2334_CMP 9: $flatten\Core.\Control_Unit.$procmux$2336_CMP 10: $flatten\Core.\Control_Unit.$procmux$2337_CMP 11: $flatten\Core.\Control_Unit.$procmux$2338_CMP 12: $flatten\Core.\Control_Unit.$procmux$2348_CMP 13: $flatten\Core.\Control_Unit.$procmux$2385_CMP 14: $flatten\Core.\Control_Unit.$procmux$2398_CMP 15: $flatten\Core.\Control_Unit.$procmux$2400_CMP State encoding: 0: 15'--------------1 <RESET STATE> 1: 15'-------------1- 2: 15'------------1-- 3: 15'-----------1--- 4: 15'----------1---- 5: 15'---------1----- 6: 15'--------1------ 7: 15'-------1------- 8: 15'------1-------- 9: 15'-----1--------- 10: 15'----1---------- 11: 15'---1----------- 12: 15'--1------------ 13: 15'-1------------- 14: 15'1-------------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 11'--------0-0 -> 0 16'1000000000000000 1: 0 11'----------1 -> 0 16'1000000000000000 2: 0 11'--------1-0 -> 14 16'1000000000000000 3: 1 11'----------1 -> 0 16'0000000000000010 4: 1 11'----------0 -> 13 16'0000000000000010 5: 2 11'----------- -> 0 16'0000000000001000 6: 3 11'----------1 -> 0 16'0000000000100000 7: 3 11'----------0 -> 13 16'0000000000100000 8: 4 11'----------1 -> 0 16'0000010000000000 9: 4 11'-------0--0 -> 9 16'0000010000000000 10: 4 11'-------1--0 -> 11 16'0000010000000000 11: 5 11'----------- -> 0 16'0000000010000000 12: 6 11'----------1 -> 0 16'0000001000000000 13: 6 11'----------0 -> 13 16'0000001000000000 14: 7 11'0000000--00 -> 0 16'0000100000000000 15: 7 11'----------1 -> 0 16'0000100000000000 16: 7 11'-1--------0 -> 1 16'0000100000000000 17: 7 11'-----1----0 -> 3 16'0000100000000000 18: 7 11'---------10 -> 4 16'0000100000000000 19: 7 11'---1------0 -> 5 16'0000100000000000 20: 7 11'1---------0 -> 6 16'0000100000000000 21: 7 11'--1-------0 -> 8 16'0000100000000000 22: 7 11'------1---0 -> 10 16'0000100000000000 23: 7 11'----1-----0 -> 12 16'0000100000000000 24: 8 11'----------1 -> 0 16'0000000100000000 25: 8 11'----------0 -> 13 16'0000000100000000 26: 9 11'--------1-0 -> 0 16'0010000000000000 27: 9 11'----------1 -> 0 16'0010000000000000 28: 9 11'--------0-0 -> 9 16'0010000000000000 29: 10 11'----------1 -> 0 16'0000000000010000 30: 10 11'----------0 -> 13 16'0000000000010000 31: 11 11'----------1 -> 0 16'0100000000000000 32: 11 11'----------0 -> 2 16'0100000000000000 33: 12 11'----------1 -> 0 16'0000000000000001 34: 12 11'----------0 -> 13 16'0000000000000001 35: 13 11'----------- -> 0 16'0000000000000100 36: 14 11'----------1 -> 0 16'0001000000000000 37: 14 11'----------0 -> 7 16'0001000000000000 ------------------------------------- FSM `$fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759 (\u_Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \u_Controller.Uart.i_uart_rx.payload_done 1: \u_Controller.Uart.i_uart_rx.next_bit 2: \u_Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.rst_o Output signals: 0: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$915_Y 1: $flatten\u_Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$906_Y 2: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$902_Y 3: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$901_Y 4: $flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$889_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\u_Controller.Uart.state_read$2766' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_Controller.Uart.state_read$2766 (\u_Controller.Uart.state_read): Number of input signals: 4 Number of output signals: 3 Number of state bits: 5 Input signals: 0: $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:78$770_Y 1: \u_Controller.Interpreter.communication_rx_empty 2: \u_Controller.Interpreter.communication_read 3: \ResetBootSystem.rst_o Output signals: 0: $flatten\u_Controller.\Uart.$procmux$2244_CMP 1: $flatten\u_Controller.\Uart.$procmux$2258_CMP 2: $flatten\u_Controller.\Uart.$procmux$2276_CMP State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'00-- -> 0 3'100 1: 0 4'1--- -> 0 3'100 2: 0 4'01-- -> 3 3'100 3: 1 4'1--- -> 0 3'000 4: 1 4'0--- -> 3 3'000 5: 2 4'1--- -> 0 3'000 6: 2 4'0--- -> 4 3'000 7: 3 4'1--- -> 0 3'010 8: 3 4'0-01 -> 1 3'010 9: 3 4'0--0 -> 2 3'010 10: 3 4'0-11 -> 3 3'010 11: 4 4'---- -> 0 3'001 ------------------------------------- FSM `$fsm$\u_Controller.Uart.state_write$2773' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_Controller.Uart.state_write$2773 (\u_Controller.Uart.state_write): Number of input signals: 3 Number of output signals: 5 Number of state bits: 5 Input signals: 0: $flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:141$775_Y 1: \u_Controller.Interpreter.communication_write 2: \ResetBootSystem.rst_o Output signals: 0: $flatten\u_Controller.\Uart.$procmux$2174_CMP 1: $flatten\u_Controller.\Uart.$procmux$2180_CMP 2: $flatten\u_Controller.\Uart.$procmux$2181_CMP 3: $flatten\u_Controller.\Uart.$procmux$2193_CMP 4: $flatten\u_Controller.\Uart.$procmux$2197_CMP State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'00- -> 0 5'10000 1: 0 3'1-- -> 0 5'10000 2: 0 3'01- -> 1 5'10000 3: 1 3'1-- -> 0 5'01000 4: 1 3'0-- -> 3 5'01000 5: 2 3'1-- -> 0 5'00100 6: 2 3'0-- -> 4 5'00100 7: 3 3'1-- -> 0 5'00001 8: 3 3'0-0 -> 2 5'00001 9: 3 3'0-1 -> 3 5'00001 10: 4 3'--- -> 0 5'00010 ------------------------------------- FSM `$fsm$\u_Controller.Uart.tx_read_fifo_state$2780' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_Controller.Uart.tx_read_fifo_state$2780 (\u_Controller.Uart.tx_read_fifo_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\u_Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.sv:201$787_Y 1: \ResetBootSystem.rst_o Output signals: 0: $flatten\u_Controller.\Uart.$procmux$2129_CMP 1: $flatten\u_Controller.\Uart.$procmux$2135_CMP State encoding: 0: 4'---1 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 1 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'0- -> 1 2'00 6: 2 2'1- -> 2 2'00 7: 3 2'0- -> 0 2'00 8: 3 2'1- -> 3 2'00 ------------------------------------- 18.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Core.Control_Unit.state$2741' from module `\processorci_top'. Mapping FSM `$fsm$\u_Controller.Uart.i_uart_rx.fsm_state$2759' from module `\processorci_top'. Mapping FSM `$fsm$\u_Controller.Uart.state_read$2766' from module `\processorci_top'. Mapping FSM `$fsm$\u_Controller.Uart.state_write$2773' from module `\processorci_top'. Mapping FSM `$fsm$\u_Controller.Uart.tx_read_fifo_state$2780' from module `\processorci_top'. 18.13. Executing OPT pass (performing simple optimizations). 18.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~31 debug messages> 18.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~36 debug messages> Removed a total of 12 cells. 18.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~120 debug messages> 18.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$2685: { \Core.Control_Unit.state [10] \Core.Control_Unit.state [7] \Core.Control_Unit.state [4:3] \Core.Control_Unit.state [1] } New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$2677: { \Core.Control_Unit.state [6:4] \Core.Control_Unit.state [1] } Optimizing cells in module \processorci_top. Performed a total of 2 changes. 18.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\u_Controller.\Uart.\tx_fifo.$procdff$2578 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1359_Y, Q = \u_Controller.Uart.tx_fifo.read_ptr, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3023 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624_Y, Q = \u_Controller.Uart.tx_fifo.read_ptr). Adding SRST signal on $flatten\u_Controller.\Uart.\tx_fifo.$procdff$2577 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1364_Y, Q = \u_Controller.Uart.tx_fifo.read_data_o, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3025 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$memrd$\memory$/eda/processor-ci-controller/rtl/fifo.sv:33$623_DATA, Q = \u_Controller.Uart.tx_fifo.read_data_o). Adding SRST signal on $flatten\u_Controller.\Uart.\tx_fifo.$procdff$2573 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$procmux$1354_Y, Q = \u_Controller.Uart.tx_fifo.write_ptr, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3027 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638_Y, Q = \u_Controller.Uart.tx_fifo.write_ptr). Adding SRST signal on $flatten\u_Controller.\Uart.\rx_fifo.$procdff$2578 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1359_Y, Q = \u_Controller.Uart.rx_fifo.read_ptr, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3029 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624_Y, Q = \u_Controller.Uart.rx_fifo.read_ptr). Adding SRST signal on $flatten\u_Controller.\Uart.\rx_fifo.$procdff$2577 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1364_Y, Q = \u_Controller.Uart.rx_fifo.read_data_o, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3031 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$memrd$\memory$/eda/processor-ci-controller/rtl/fifo.sv:33$623_DATA, Q = \u_Controller.Uart.rx_fifo.read_data_o). Adding SRST signal on $flatten\u_Controller.\Uart.\rx_fifo.$procdff$2573 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$procmux$1354_Y, Q = \u_Controller.Uart.rx_fifo.write_ptr, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3033 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638_Y, Q = \u_Controller.Uart.rx_fifo.write_ptr). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_tx.$procdff$2554 ($dff) from module processorci_top (D = { $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1277_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1271_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1262_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1253_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1244_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1235_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1217_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1226_Y }, Q = \u_Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3035 ($sdff) from module processorci_top (D = \u_Controller.Uart.uart_tx_data [7], Q = \u_Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$3035 ($sdff) from module processorci_top (D = { $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1271_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1262_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1253_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1244_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1235_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1217_Y $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1226_Y }, Q = \u_Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_tx.$procdff$2552 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1193_Y, Q = \u_Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3040 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1193_Y, Q = \u_Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_tx.$procdff$2551 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1182_Y, Q = \u_Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3046 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$869_Y, Q = \u_Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_tx.$procdff$2550 ($dff) from module processorci_top (D = \u_Controller.Uart.i_uart_tx.n_fsm_state, Q = \u_Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_tx.$procdff$2549 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1171_Y, Q = \u_Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$3051 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1171_Y, Q = \u_Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2548 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1160_Y, Q = \u_Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3057 ($sdff) from module processorci_top (D = \u_Controller.Uart.i_uart_rx.recieved_data, Q = \u_Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2546 ($dff) from module processorci_top (D = { $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1137_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1128_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1119_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1110_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1101_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1092_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1074_Y $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1083_Y }, Q = \u_Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3059 ($sdff) from module processorci_top (D = { \u_Controller.Uart.i_uart_rx.bit_sample \u_Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \u_Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2545 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1056_Y, Q = \u_Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3063 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$909_Y, Q = \u_Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2544 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1051_Y, Q = \u_Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3067 ($sdff) from module processorci_top (D = \u_Controller.Uart.i_uart_rx.rxd_reg, Q = \u_Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2543 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1043_Y, Q = \u_Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3069 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$920_Y, Q = \u_Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2541 ($dff) from module processorci_top (D = \rx, Q = \u_Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\u_Controller.\Uart.\i_uart_rx.$procdff$2540 ($dff) from module processorci_top (D = \u_Controller.Uart.i_uart_rx.rxd_reg_0, Q = \u_Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2626 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2289_Y, Q = \u_Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$3075 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2289_Y, Q = \u_Controller.Uart.counter_read). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2625 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2253_Y, Q = \u_Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2624 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2243_Y, Q = \u_Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2623 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2304_Y, Q = \u_Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3093 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2304_Y, Q = \u_Controller.Uart.read_data). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2621 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2209_Y, Q = \u_Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$3103 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2209_Y, Q = \u_Controller.Uart.counter_write). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2620 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2223_Y, Q = \u_Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3113 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2223_Y, Q = \u_Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2619 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2237_Y, Q = \u_Controller.Uart.tx_fifo_data_in, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3123 ($sdff) from module processorci_top (D = \u_Controller.Uart.write_data_buffer [31:24], Q = \u_Controller.Uart.tx_fifo_data_in). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2618 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2169_Y, Q = \u_Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2617 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2179_Y, Q = \u_Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2616 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2160_Y, Q = \u_Controller.Uart.rx_fifo_data_in, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3137 ($sdff) from module processorci_top (D = \u_Controller.Uart.i_uart_rx.uart_rx_data, Q = \u_Controller.Uart.rx_fifo_data_in). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2615 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2155_Y, Q = \u_Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2613 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2150_Y, Q = \u_Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3140 ($sdff) from module processorci_top (D = \u_Controller.Uart.tx_fifo.read_data_o, Q = \u_Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2612 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2126_Y, Q = \u_Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Uart.$procdff$2611 ($dff) from module processorci_top (D = $flatten\u_Controller.\Uart.$procmux$2134_Y, Q = \u_Controller.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2606 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1625_Y, Q = \u_Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3148 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1625_Y, Q = \u_Controller.Interpreter.return_state). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2605 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1660_Y, Q = \u_Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2604 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1703_Y, Q = \u_Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3165 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1703_Y [63:8], Q = \u_Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$3165 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1703_Y [7:0], Q = \u_Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2603 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1713_Y, Q = \u_Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3180 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1713_Y, Q = \u_Controller.Interpreter.timeout_counter). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2602 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1748_Y, Q = \u_Controller.Interpreter.timeout, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3184 ($sdff) from module processorci_top (D = { 8'00000000 \u_Controller.Interpreter.communication_buffer [31:8] }, Q = \u_Controller.Interpreter.timeout). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2601 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1754_Y, Q = \u_Controller.Interpreter.read_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3186 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1754_Y, Q = \u_Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2600 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1782_Y, Q = \u_Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3190 ($sdff) from module processorci_top (D = \u_Controller.Uart.read_data, Q = \u_Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2599 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1807_Y, Q = \u_Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2598 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1829_Y, Q = \u_Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3201 ($sdff) from module processorci_top (D = \u_Controller.Interpreter.communication_buffer [31:8], Q = \u_Controller.Interpreter.num_of_pages). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2597 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1841_Y, Q = \u_Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2596 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1849_Y, Q = \u_Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3210 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1849_Y, Q = \u_Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2595 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1889_Y, Q = \u_Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3214 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1889_Y, Q = \u_Controller.Interpreter.end_position). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2593 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1931_Y, Q = \u_Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3218 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1931_Y, Q = \u_Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2592 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1470_Y, Q = \u_Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2591 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1942_Y, Q = \u_Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2590 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1575_Y, Q = \u_Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2589 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1952_Y, Q = \u_Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3231 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1952_Y, Q = \u_Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2588 ($dff) from module processorci_top (D = \u_Controller.Interpreter.read_buffer, Q = \u_Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2587 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1594_Y, Q = \u_Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2586 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1617_Y, Q = \u_Controller.Interpreter.communication_read, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2585 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1527_Y, Q = \u_Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2584 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$2028_Y, Q = \u_Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3247 ($sdff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$2028_Y, Q = \u_Controller.Interpreter.counter). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2583 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$2052_Y, Q = \u_Controller.Interpreter.write_data). Adding EN signal on $flatten\u_Controller.\Interpreter.$procdff$2582 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$2078_Y, Q = \u_Controller.Interpreter.address). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2581 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1370_Y, Q = \u_Controller.Interpreter.state, rval = 8'00000000). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2580 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1494_Y, Q = \u_Controller.Interpreter.memory_write, rval = 1'0). Adding SRST signal on $flatten\u_Controller.\Interpreter.$procdff$2579 ($dff) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1516_Y, Q = \u_Controller.Interpreter.memory_read, rval = 1'0). Adding EN signal on $flatten\u_Controller.\ClkDivider.$procdff$2559 ($adff) from module processorci_top (D = $flatten\u_Controller.\ClkDivider.$0\pulse_counter[31:0], Q = \u_Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\u_Controller.$procdff$2529 ($dff) from module processorci_top (D = $flatten\u_Controller.$procmux$954_Y, Q = \u_Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3277 ($sdff) from module processorci_top (D = $flatten\u_Controller.$procmux$954_Y, Q = \u_Controller.finish_execution). Adding EN signal on $flatten\ResetBootSystem.$procdff$2539 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$994_Y, Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$2538 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$1004_Y, Q = \ResetBootSystem.rst_o). Adding SRST signal on $flatten\ResetBootSystem.$procdff$2537 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$1014_Y, Q = \ResetBootSystem.state, rval = 2'00). Adding EN signal on $auto$ff.cc:266:slice$3305 ($sdff) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$1014_Y, Q = \ResetBootSystem.state). Adding SRST signal on $flatten\Core.$procdff$2536 ($dff) from module processorci_top (D = $flatten\Core.$procmux$959_Y, Q = \Core.InstructionReg, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3313 ($sdff) from module processorci_top (D = \Core.read_data, Q = \Core.InstructionReg). Adding EN signal on $flatten\Core.$procdff$2531 ($dff) from module processorci_top (D = \Core.PC, Q = \Core.PCOld). Adding SRST signal on $flatten\Core.$procdff$2530 ($dff) from module processorci_top (D = $flatten\Core.$procmux$969_Y, Q = \Core.PC, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3320 ($sdff) from module processorci_top (D = \Core.PC_Input, Q = \Core.PC). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3185 ($sdffe) from module processorci_top. 18.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 131 unused cells and 186 unused wires. <suppressed ~132 debug messages> 18.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~29 debug messages> 18.13.9. Rerunning OPT passes. (Maybe there is more to do..) 18.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~88 debug messages> 18.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3065: { \ResetBootSystem.rst_o \u_Controller.Uart.i_uart_rx.fsm_state [3:2] \u_Controller.Uart.i_uart_rx.fsm_state [0] } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 18.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~54 debug messages> Removed a total of 18 cells. 18.13.13. Executing OPT_DFF pass (perform DFF optimizations). 18.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 19 unused wires. <suppressed ~2 debug messages> 18.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.13.16. Rerunning OPT passes. (Maybe there is more to do..) 18.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~88 debug messages> 18.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.13.20. Executing OPT_DFF pass (perform DFF optimizations). 18.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.13.23. Finished OPT passes. (There is nothing left to do.) 18.14. Executing WREDUCE pass (reducing word size of cells). Removed top 1 address bits (of 5) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2631 (Core.RegisterBank.registers). Removed top 28 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2632 (Core.RegisterBank.registers). Removed top 1 address bits (of 5) from memory read port processorci_top.$flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:14$48 (Core.RegisterBank.registers). Removed top 1 address bits (of 5) from memory read port processorci_top.$flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:15$49 (Core.RegisterBank.registers). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2931 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2935 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2959 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2967 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3006 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:78$770 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.sv:141$775 ($lt). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2902 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2888 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2877 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$898 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$897 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$896 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$895 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$890 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$888 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$864 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$856 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$854 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$851 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$850 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$846 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$841 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$840 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$839 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$838 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$834 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$832 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$eq$/eda/processor-ci-controller/rtl/interpreter.sv:214$792 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:297$795 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:359$798 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\u_Controller.\Interpreter.$lt$/eda/processor-ci-controller/rtl/interpreter.sv:450$805 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\u_Controller.\Interpreter.$eq$/eda/processor-ci-controller/rtl/interpreter.sv:489$809 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\u_Controller.\Interpreter.$ge$/eda/processor-ci-controller/rtl/interpreter.sv:506$811 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1371_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1372_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1374 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1376_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1377_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1378_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1379_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1380_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1382 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1384_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1385_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1387 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1389_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1390_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1394_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1395_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1396_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1398 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1400_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1401_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1402_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1404 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1406_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1408 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1410_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1411_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1412_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1413_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1414_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1415_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1416_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1418 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1420_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1422 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1424_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1425_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1427 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1429_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1430_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1433_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1432 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1434_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1435_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1436_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1437_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1438_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1439_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1440_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1441_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1442_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1443_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1444_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1445_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1446_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1447_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1448_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1449_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1450_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1451_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1452_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1453_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1454_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1455_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1456_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1458 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1460_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1462 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1496_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1497_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1498_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1531_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1704_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1705_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1706_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1749_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1857_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1890_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1891_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1964_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1965_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\ClkDivider.$gt$/eda/processor-ci-controller/rtl/clk_divider.sv:53$829 ($gt). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_Controller.\ClkDivider.$sub$/eda/processor-ci-controller/rtl/clk_divider.sv:54$830 ($sub). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\u_Controller.$ternary$/eda/processor-ci-controller/rtl/controller.sv:126$755 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3282 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:37$9 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$20 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2509_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2516_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2517_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2518_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$2519_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2504_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2488_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2489_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2490_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Core.\ALU_Control.$procmux$2492 ($mux). Removed top 1 bits (of 5) from mux cell processorci_top.$flatten\Core.\RegisterBank.$procmux$2099 ($mux). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:83$30 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3310 ($ne). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2462_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2463_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2467_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2468_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2469_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3291 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.$procmux$981_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.$procmux$977_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$2923 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3274 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$1025_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/rtl/reset.sv:45$728 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/rtl/reset.sv:43$726 ($lt). Removed top 1 bits (of 4) from wire processorci_top.$flatten\Core.\ALU_Control.$procmux$2492_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:45$15_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:37$9_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$20_Y. Removed top 1 bits (of 5) from wire processorci_top.$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:19$46_ADDR[4:0]$51. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\ResetBootSystem.$procmux$994_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1374_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1382_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1387_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1398_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1404_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1408_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1418_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1422_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1427_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1432_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1458_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\u_Controller.\Interpreter.$procmux$1462_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$895_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$896_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$897_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$898_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$838_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$839_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$840_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$841_Y. 18.15. Executing PEEPOPT pass (run peephole optimizers). 18.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 27 unused wires. <suppressed ~1 debug messages> 18.17. Executing SHARE pass (SAT-based resource sharing). Found 4 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\u_Controller.\Core_Memory.$memrd$\memory$/eda/processor-ci-controller/rtl/memory.sv:29$647 ($memrd): Found 2 activation_patterns using ctrl signal { $flatten\u_Controller.\Interpreter.$procmux$1414_CMP \u_Controller.Interpreter.address [31] \u_Controller.Interpreter.memory_mux_selector $flatten\u_Controller.\Core_Memory.$logic_and$/eda/processor-ci-controller/rtl/memory.sv:29$646_Y }. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$sshr$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:51$18 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2509_CMP. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shr$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:49$17 ($shr): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2510_CMP. No candidates found. Analyzing resource sharing options for $flatten\Core.\Alu.$shl$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:47$16 ($shl): Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$2511_CMP. No candidates found. 18.18. Executing TECHMAP pass (map to technology primitives). 18.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/cmp2lut.v Parsing Verilog input from `/usr/local/share/synlig/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 18.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. No more expansions possible. <suppressed ~197 debug messages> 18.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 18.21. Executing TECHMAP pass (map to technology primitives). 18.21.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/mul2dsp.v Parsing Verilog input from `/usr/local/share/synlig/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 18.21.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/dsp_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 18.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 18.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:33$6 ($add). creating $macc model for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:35$7 ($sub). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727 ($add). creating $macc model for $flatten\u_Controller.\ClkDivider.$sub$/eda/processor-ci-controller/rtl/clk_divider.sv:54$830 ($sub). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:213$791 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:275$794 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:297$795 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:359$798 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:449$803 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:459$807 ($add). creating $macc model for $flatten\u_Controller.\Interpreter.$sub$/eda/processor-ci-controller/rtl/interpreter.sv:356$797 ($sub). creating $macc model for $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:145$777 ($add). creating $macc model for $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:81$772 ($add). creating $macc model for $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$909 ($add). creating $macc model for $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$920 ($add). creating $macc model for $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$858 ($add). creating $macc model for $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$869 ($add). creating $macc model for $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624 ($add). creating $macc model for $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638 ($add). creating $macc model for $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624 ($add). creating $macc model for $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638 ($add). creating $alu model for $macc $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638. creating $alu model for $macc $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624. creating $alu model for $macc $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638. creating $alu model for $macc $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624. creating $alu model for $macc $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$869. creating $alu model for $macc $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$858. creating $alu model for $macc $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$920. creating $alu model for $macc $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$909. creating $alu model for $macc $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:81$772. creating $alu model for $macc $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:145$777. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$sub$/eda/processor-ci-controller/rtl/interpreter.sv:356$797. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:459$807. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:449$803. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:359$798. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:297$795. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:275$794. creating $alu model for $macc $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:213$791. creating $alu model for $macc $flatten\u_Controller.\ClkDivider.$sub$/eda/processor-ci-controller/rtl/clk_divider.sv:54$830. creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727. creating $alu model for $macc $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:35$7. creating $alu model for $macc $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:33$6. creating $alu model for $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$19 ($ge): new $alu creating $alu model for $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:37$8 ($lt): merged with $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$19. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/rtl/reset.sv:43$726 ($lt): new $alu creating $alu model for $flatten\u_Controller.\ClkDivider.$gt$/eda/processor-ci-controller/rtl/clk_divider.sv:53$829 ($gt): new $alu creating $alu model for $flatten\u_Controller.\Interpreter.$ge$/eda/processor-ci-controller/rtl/interpreter.sv:506$811 ($ge): new $alu creating $alu model for $flatten\u_Controller.\Interpreter.$lt$/eda/processor-ci-controller/rtl/interpreter.sv:450$805 ($lt): merged with $flatten\u_Controller.\Interpreter.$ge$/eda/processor-ci-controller/rtl/interpreter.sv:506$811. creating $alu model for $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:45$15 ($eq): merged with $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$19. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/rtl/reset.sv:45$728 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/rtl/reset.sv:43$726. creating $alu model for $flatten\u_Controller.\Interpreter.$eq$/eda/processor-ci-controller/rtl/interpreter.sv:489$809 ($eq): merged with $flatten\u_Controller.\Interpreter.$ge$/eda/processor-ci-controller/rtl/interpreter.sv:506$811. creating $alu cell for $flatten\u_Controller.\Interpreter.$ge$/eda/processor-ci-controller/rtl/interpreter.sv:506$811, $flatten\u_Controller.\Interpreter.$lt$/eda/processor-ci-controller/rtl/interpreter.sv:450$805, $flatten\u_Controller.\Interpreter.$eq$/eda/processor-ci-controller/rtl/interpreter.sv:489$809: $auto$alumacc.cc:485:replace_alu$3358 creating $alu cell for $flatten\u_Controller.\ClkDivider.$gt$/eda/processor-ci-controller/rtl/clk_divider.sv:53$829: $auto$alumacc.cc:485:replace_alu$3371 creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/rtl/reset.sv:43$726, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/rtl/reset.sv:45$728: $auto$alumacc.cc:485:replace_alu$3376 creating $alu cell for $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:53$19, $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:37$8, $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:45$15: $auto$alumacc.cc:485:replace_alu$3387 creating $alu cell for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:33$6: $auto$alumacc.cc:485:replace_alu$3400 creating $alu cell for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:35$7: $auto$alumacc.cc:485:replace_alu$3403 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/rtl/reset.sv:44$727: $auto$alumacc.cc:485:replace_alu$3406 creating $alu cell for $flatten\u_Controller.\ClkDivider.$sub$/eda/processor-ci-controller/rtl/clk_divider.sv:54$830: $auto$alumacc.cc:485:replace_alu$3409 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:213$791: $auto$alumacc.cc:485:replace_alu$3412 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:275$794: $auto$alumacc.cc:485:replace_alu$3415 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:297$795: $auto$alumacc.cc:485:replace_alu$3418 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:359$798: $auto$alumacc.cc:485:replace_alu$3421 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:449$803: $auto$alumacc.cc:485:replace_alu$3424 creating $alu cell for $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:459$807: $auto$alumacc.cc:485:replace_alu$3427 creating $alu cell for $flatten\u_Controller.\Interpreter.$sub$/eda/processor-ci-controller/rtl/interpreter.sv:356$797: $auto$alumacc.cc:485:replace_alu$3430 creating $alu cell for $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:145$777: $auto$alumacc.cc:485:replace_alu$3433 creating $alu cell for $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:81$772: $auto$alumacc.cc:485:replace_alu$3436 creating $alu cell for $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$909: $auto$alumacc.cc:485:replace_alu$3439 creating $alu cell for $flatten\u_Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$920: $auto$alumacc.cc:485:replace_alu$3442 creating $alu cell for $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$858: $auto$alumacc.cc:485:replace_alu$3445 creating $alu cell for $flatten\u_Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$869: $auto$alumacc.cc:485:replace_alu$3448 creating $alu cell for $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624: $auto$alumacc.cc:485:replace_alu$3451 creating $alu cell for $flatten\u_Controller.\Uart.\rx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638: $auto$alumacc.cc:485:replace_alu$3454 creating $alu cell for $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:34$624: $auto$alumacc.cc:485:replace_alu$3457 creating $alu cell for $flatten\u_Controller.\Uart.\tx_fifo.$add$/eda/processor-ci-controller/rtl/fifo.sv:44$638: $auto$alumacc.cc:485:replace_alu$3460 created 25 $alu and 0 $macc cells. 18.23. Executing OPT pass (performing simple optimizations). 18.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~4 debug messages> 18.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~88 debug messages> 18.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 18.23.6. Executing OPT_DFF pass (perform DFF optimizations). 18.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 12 unused wires. <suppressed ~2 debug messages> 18.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.23.9. Rerunning OPT passes. (Maybe there is more to do..) 18.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~88 debug messages> 18.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.23.13. Executing OPT_DFF pass (perform DFF optimizations). 18.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.23.16. Finished OPT passes. (There is nothing left to do.) 18.24. Executing MEMORY pass. 18.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 18.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 18.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Core.RegisterBank.registers write port 0. Analyzing processorci_top.Core.RegisterBank.registers write port 1. Analyzing processorci_top.u_Controller.Core_Memory.memory write port 0. Analyzing processorci_top.u_Controller.Uart.rx_fifo.memory write port 0. Analyzing processorci_top.u_Controller.Uart.tx_fifo.memory write port 0. 18.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 18.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Core.RegisterBank.registers'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Write port 1: non-transparent. Checking read port `\Core.RegisterBank.registers'[1] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Write port 1: non-transparent. Checking read port `\u_Controller.Core_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\u_Controller.Uart.rx_fifo.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: don't care on collision. Checking read port `\u_Controller.Uart.tx_fifo.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: don't care on collision. Checking read port address `\u_Controller.Core_Memory.memory'[0] in module `\processorci_top': no address FF found. 18.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 4 unused cells and 86 unused wires. <suppressed ~9 debug messages> 18.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.Core.RegisterBank.registers by address: Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address: 18.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 18.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 18.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory processorci_top.Core.RegisterBank.registers mapping memory processorci_top.u_Controller.Core_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.u_Controller.Uart.rx_fifo.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.u_Controller.Uart.rx_fifo.memory: $\u_Controller.Uart.rx_fifo.memory$rdreg[0] mapping memory processorci_top.u_Controller.Uart.tx_fifo.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.u_Controller.Uart.tx_fifo.memory: $\u_Controller.Uart.tx_fifo.memory$rdreg[0] <suppressed ~1008 debug messages> 18.27. Executing TECHMAP pass (map to technology primitives). 18.27.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/lutrams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 18.27.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/brams_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 18.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~534 debug messages> 18.28. Executing OPT pass (performing simple optimizations). 18.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~139 debug messages> 18.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.3. Executing OPT_DFF pass (perform DFF optimizations). Handling always-active SRST on $auto$ff.cc:266:slice$3306 ($sdffe) from module processorci_top (changing to const D). Handling never-active EN on $auto$ff.cc:266:slice$3296 ($dffe) from module processorci_top (removing D path). Handling never-active EN on $auto$ff.cc:266:slice$3285 ($dffe) from module processorci_top (removing D path). Adding SRST signal on $auto$ff.cc:266:slice$3203 ($dffe) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:459$807_Y, Q = \u_Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3156 ($dffe) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$procmux$1660_Y [1:0], Q = \u_Controller.Interpreter.temp_buffer [1:0]). Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3306 ($dff) from module processorci_top. 18.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 32 unused cells and 3726 unused wires. <suppressed ~33 debug messages> 18.28.5. Rerunning OPT passes. (Removed registers in this run.) 18.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~55 debug messages> 18.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.8. Executing OPT_DFF pass (perform DFF optimizations). Removing never-active SRST on $\u_Controller.Uart.rx_fifo.memory$rdreg[0] ($sdffe) from module processorci_top. Removing never-active SRST on $\u_Controller.Uart.tx_fifo.memory$rdreg[0] ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3322 ($sdffe) from module processorci_top. Removing never-active ARST on $auto$ff.cc:266:slice$3270 ($adffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3269 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3268 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3267 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3248 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3248 ($sdffe) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:213$791_Y, Q = \u_Controller.Interpreter.counter, rval = 8'00000000). Removing never-active SRST on $auto$ff.cc:266:slice$3246 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3245 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3244 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3232 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3230 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3222 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3219 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3215 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3215 ($sdffe) from module processorci_top (D = { \u_Controller.Interpreter.accumulator [31:26] \u_Controller.Interpreter.accumulator [1:0] }, Q = { \u_Controller.Interpreter.end_position [31:26] \u_Controller.Interpreter.end_position [1:0] }, rval = 8'00000000). Removing never-active SRST on $auto$ff.cc:266:slice$3211 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3202 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3191 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3187 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3181 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3181 ($sdffe) from module processorci_top (D = $flatten\u_Controller.\Interpreter.$add$/eda/processor-ci-controller/rtl/interpreter.sv:449$803_Y, Q = \u_Controller.Interpreter.timeout_counter, rval = 0). Removing never-active SRST on $auto$ff.cc:266:slice$3173 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3166 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3149 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3147 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3141 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3139 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3138 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3136 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3124 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3114 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3114 ($sdffe) from module processorci_top (D = \u_Controller.Interpreter.communication_write_data [7:0], Q = \u_Controller.Uart.write_data_buffer [7:0], rval = 8'00000000). Removing never-active SRST on $auto$ff.cc:266:slice$3104 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3104 ($sdffe) from module processorci_top (D = $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:145$777_Y, Q = \u_Controller.Uart.counter_write, rval = 3'000). Removing never-active SRST on $auto$ff.cc:266:slice$3094 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3094 ($sdffe) from module processorci_top (D = { \u_Controller.Uart.read_data [23:0] \u_Controller.Uart.rx_fifo.read_data_o }, Q = \u_Controller.Uart.read_data, rval = 0). Removing never-active SRST on $auto$ff.cc:266:slice$3092 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3076 ($sdffe) from module processorci_top. Adding SRST signal on $auto$ff.cc:266:slice$3076 ($sdffe) from module processorci_top (D = $flatten\u_Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.sv:81$772_Y, Q = \u_Controller.Uart.counter_read, rval = 3'000). Removing never-active SRST on $auto$ff.cc:266:slice$3074 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3073 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3068 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3058 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3050 ($sdff) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3037 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3036 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3034 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3030 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3028 ($sdffe) from module processorci_top. Removing never-active SRST on $auto$ff.cc:266:slice$3024 ($sdffe) from module processorci_top. 18.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 6 unused cells and 37 unused wires. <suppressed ~7 debug messages> 18.28.10. Rerunning OPT passes. (Removed registers in this run.) 18.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.28.13. Executing OPT_DFF pass (perform DFF optimizations). 18.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.28.15. Finished fast OPT passes. 18.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \Core.RegisterBank.registers in module \processorci_top: created 16 $dff cells and 0 static cells of width 32. Extracted data FF from read port 0 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[0] Extracted data FF from read port 1 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[1] read interface: 2 $dff and 30 $mux cells. write interface: 32 write mux blocks. 18.30. Executing OPT pass (performing simple optimizations). 18.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~46 debug messages> 18.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $memory\Core.RegisterBank.registers$wrmux[0][0][0]$4939. dead port 2/2 on $mux $memory\Core.RegisterBank.registers$wrmux[0][0][0]$4939. Removed 2 multiplexer ports. <suppressed ~62 debug messages> 18.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$4789: { $auto$opt_dff.cc:194:make_patterns_logic$4786 $auto$opt_dff.cc:194:make_patterns_logic$3159 $auto$opt_dff.cc:194:make_patterns_logic$3157 } Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$2484: Old ports: A=4'1001, B=4'0011, Y=$flatten\Core.\ALU_Control.$procmux$2484_Y New ports: A=2'10, B=2'01, Y={ $flatten\Core.\ALU_Control.$procmux$2484_Y [3] $flatten\Core.\ALU_Control.$procmux$2484_Y [1] } New connections: { $flatten\Core.\ALU_Control.$procmux$2484_Y [2] $flatten\Core.\ALU_Control.$procmux$2484_Y [0] } = 2'01 Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$2492: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3323 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3323 [2] New connections: $auto$wreduce.cc:461:run$3323 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2106: Old ports: A={ \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31] \Core.InstructionReg [31:20] }, B={ \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24:20] 20'00000000000000000000 \Core.InstructionReg [31:20] 27'000000000000000000000000000 \Core.InstructionReg [24:20] }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \Core.InstructionReg [31] \Core.InstructionReg [31:25] }, B={ \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] \Core.InstructionReg [24] 1'0 \Core.InstructionReg [31:25] 8'00000000 }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] \Core.InstructionReg [24:20] } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1382: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3331 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3331 [2] $auto$wreduce.cc:461:run$3331 [0] } New connections: $auto$wreduce.cc:461:run$3331 [1] = $auto$wreduce.cc:461:run$3331 [0] Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1387: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$3332 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$3332 [1:0] New connections: $auto$wreduce.cc:461:run$3332 [6:2] = { $auto$wreduce.cc:461:run$3332 [1] 3'010 $auto$wreduce.cc:461:run$3332 [0] } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1398: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$3333 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3333 [2] New connections: { $auto$wreduce.cc:461:run$3333 [3] $auto$wreduce.cc:461:run$3333 [1:0] } = { $auto$wreduce.cc:461:run$3333 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1408: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$3335 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3335 [0] New connections: $auto$wreduce.cc:461:run$3335 [3:1] = { $auto$wreduce.cc:461:run$3335 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1422: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$3337 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3337 [0] New connections: $auto$wreduce.cc:461:run$3337 [6:1] = { $auto$wreduce.cc:461:run$3337 [0] 1'0 $auto$wreduce.cc:461:run$3337 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1625: Old ports: A=8'00001011, B=302978816, Y=$flatten\u_Controller.\Interpreter.$procmux$1625_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\u_Controller.\Interpreter.$procmux$1625_Y [4:0] New connections: $flatten\u_Controller.\Interpreter.$procmux$1625_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1942: Old ports: A={ 8'00000000 \u_Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \u_Controller.Interpreter.timeout [23:0] }, Y=$flatten\u_Controller.\Interpreter.$procmux$1942_Y New ports: A=\u_Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \u_Controller.Interpreter.timeout [23:0] }, Y=$flatten\u_Controller.\Interpreter.$procmux$1942_Y [23:0] New connections: $flatten\u_Controller.\Interpreter.$procmux$1942_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1952: $auto$opt_reduce.cc:137:opt_pmux$2714 Consolidated identical input bits for $pmux cell $flatten\u_Controller.\Uart.\i_uart_rx.$procmux$1155: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3342 [0] 1'0 $auto$wreduce.cc:461:run$3343 [1:0] 2'01 \u_Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3345 [1:0] }, Y=\u_Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3342 [0] $auto$wreduce.cc:461:run$3343 [1:0] 1'1 \u_Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3345 [1:0] }, Y=\u_Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \u_Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$898: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3345 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3345 [0] New connections: $auto$wreduce.cc:461:run$3345 [1] = $auto$wreduce.cc:461:run$3345 [0] Consolidated identical input bits for $pmux cell $flatten\u_Controller.\Uart.\i_uart_tx.$procmux$1292: Old ports: A=3'000, B={ 2'00 \u_Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3347 [1:0] 2'01 \u_Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3349 [1:0] }, Y=\u_Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \u_Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$3347 [1:0] 1'1 \u_Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3349 [1:0] }, Y=\u_Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \u_Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$841: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3349 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3349 [0] New connections: $auto$wreduce.cc:461:run$3349 [1] = $auto$wreduce.cc:461:run$3349 [0] Optimizing cells in module \processorci_top. Performed a total of 16 changes. 18.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 18.30.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 1 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 2 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 3 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 4 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 6 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 7 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 8 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 9 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 10 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 11 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 12 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 13 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 14 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 15 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 16 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 17 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 18 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 19 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 20 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 21 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 22 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 23 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 24 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 25 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 26 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 27 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 28 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 29 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 30 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. Setting constant 0-bit at position 31 on $memory\Core.RegisterBank.registers[0]$4801 ($dff) from module processorci_top. 18.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 94 unused wires. <suppressed ~3 debug messages> 18.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 18.30.9. Rerunning OPT passes. (Maybe there is more to do..) 18.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~62 debug messages> 18.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\Core.RegisterBank.registers[9]$4819 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[9]). Adding EN signal on $memory\Core.RegisterBank.registers[8]$4817 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[8]). Adding EN signal on $memory\Core.RegisterBank.registers[7]$4815 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[7]). Adding EN signal on $memory\Core.RegisterBank.registers[6]$4813 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[6]). Adding EN signal on $memory\Core.RegisterBank.registers[5]$4811 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[5]). Adding EN signal on $memory\Core.RegisterBank.registers[4]$4809 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[4]). Adding EN signal on $memory\Core.RegisterBank.registers[3]$4807 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[3]). Adding EN signal on $memory\Core.RegisterBank.registers[2]$4805 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[2]). Adding EN signal on $memory\Core.RegisterBank.registers[1]$4803 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[1]). Adding EN signal on $memory\Core.RegisterBank.registers[15]$4831 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[15]). Adding EN signal on $memory\Core.RegisterBank.registers[14]$4829 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[14]). Adding EN signal on $memory\Core.RegisterBank.registers[13]$4827 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[13]). Adding EN signal on $memory\Core.RegisterBank.registers[12]$4825 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[12]). Adding EN signal on $memory\Core.RegisterBank.registers[11]$4823 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[11]). Adding EN signal on $memory\Core.RegisterBank.registers[10]$4821 ($dff) from module processorci_top (D = \Core.RegisterBank.writeData, Q = \Core.RegisterBank.registers[10]). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3050 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3149 ($dffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3149 ($dffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3149 ($dffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3223 ($dffe) from module processorci_top. 18.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 15 unused cells and 15 unused wires. <suppressed ~16 debug messages> 18.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~2 debug messages> 18.30.16. Rerunning OPT passes. (Maybe there is more to do..) 18.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~47 debug messages> 18.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\u_Controller.\Interpreter.$procmux$1392: Old ports: A=8'00000100, B={ 3'000 \u_Controller.Interpreter.return_state [4:0] }, Y=$flatten\u_Controller.\Interpreter.$procmux$1392_Y New ports: A=5'00100, B=\u_Controller.Interpreter.return_state [4:0], Y=$flatten\u_Controller.\Interpreter.$procmux$1392_Y [4:0] New connections: $flatten\u_Controller.\Interpreter.$procmux$1392_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\u_Controller.\Interpreter.$procmux$1370: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$3341 [0] 6'000000 $auto$wreduce.cc:461:run$3334 [1:0] 1'0 $auto$wreduce.cc:461:run$3339 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$3338 [1:0] 3'000 \u_Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$3337 [6] 1'0 $auto$wreduce.cc:461:run$3337 [6] 3'011 $auto$wreduce.cc:461:run$3337 [6] 7'0000011 \u_Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$3333 [3] 2'00 $auto$wreduce.cc:461:run$3333 [3] 6'000010 $auto$wreduce.cc:461:run$3334 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$3333 [3] $auto$wreduce.cc:461:run$3333 [3] 18'000000010100000100 $flatten\u_Controller.\Interpreter.$procmux$1392_Y 1'0 $auto$wreduce.cc:461:run$3332 [6] 3'010 $auto$wreduce.cc:461:run$3332 [2] $auto$wreduce.cc:461:run$3332 [6] $auto$wreduce.cc:461:run$3332 [2] 13'0001001100010 $auto$wreduce.cc:461:run$3331 [2:1] $auto$wreduce.cc:461:run$3331 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$3330 [0] 8'00000011 }, Y=$flatten\u_Controller.\Interpreter.$procmux$1370_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$3341 [0] 5'00000 $auto$wreduce.cc:461:run$3334 [1:0] $auto$wreduce.cc:461:run$3339 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$3338 [1:0] 2'00 \u_Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$3337 [6] 1'0 $auto$wreduce.cc:461:run$3337 [6] 3'011 $auto$wreduce.cc:461:run$3337 [6] 6'000011 \u_Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$3333 [3] 2'00 $auto$wreduce.cc:461:run$3333 [3] 5'00010 $auto$wreduce.cc:461:run$3334 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$3333 [3] $auto$wreduce.cc:461:run$3333 [3] 18'000000101000010000 $flatten\u_Controller.\Interpreter.$procmux$1392_Y [4:0] $auto$wreduce.cc:461:run$3332 [6] 3'010 $auto$wreduce.cc:461:run$3332 [2] $auto$wreduce.cc:461:run$3332 [6] $auto$wreduce.cc:461:run$3332 [2] 11'00100110010 $auto$wreduce.cc:461:run$3331 [2:1] $auto$wreduce.cc:461:run$3331 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$3330 [0] 7'0000011 }, Y=$flatten\u_Controller.\Interpreter.$procmux$1370_Y [6:0] New connections: $flatten\u_Controller.\Interpreter.$procmux$1370_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 18.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.20. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3270 ($dffe) from module processorci_top (D = $flatten\u_Controller.\ClkDivider.$procmux$1297_Y [31:24], Q = \u_Controller.ClkDivider.pulse_counter [31:24], rval = 8'00000000). 18.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.30.23. Rerunning OPT passes. (Maybe there is more to do..) 18.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~47 debug messages> 18.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3267 ($dff) from module processorci_top. 18.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 18.30.30. Rerunning OPT passes. (Maybe there is more to do..) 18.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~47 debug messages> 18.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.30.34. Executing OPT_DFF pass (perform DFF optimizations). 18.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.30.37. Finished OPT passes. (There is nothing left to do.) 18.31. Executing TECHMAP pass (map to technology primitives). 18.31.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.31.2. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/arith_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 18.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $lut. Using extmapper simplemap for cells of type $bmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4632 debug messages> 18.32. Executing OPT pass (performing simple optimizations). 18.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~6716 debug messages> 18.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3957 debug messages> Removed a total of 1319 cells. 18.32.3. Executing OPT_DFF pass (perform DFF optimizations). 18.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1253 unused cells and 4232 unused wires. <suppressed ~1259 debug messages> 18.32.5. Finished fast OPT passes. 18.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 18.35. Executing TECHMAP pass (map to technology primitives). 18.35.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 18.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. No more expansions possible. <suppressed ~1477 debug messages> 18.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~95 debug messages> 18.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 18.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 18.39. Executing ATTRMVCP pass (move or copy attributes). 18.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 6910 unused wires. <suppressed ~1 debug messages> 18.41. Executing TECHMAP pass (map to technology primitives). 18.41.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/latches_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 18.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 18.42. Executing ABC9 pass. 18.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.3. Executing PROC pass (convert processes to netlists). 18.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$29453'. Cleaned up 1 empty switch. 18.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 18.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 18.42.3.4. Executing PROC_INIT pass (extract init attributes). 18.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 18.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 18.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454'. 1/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_EN[3:0]$29458 2/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_DATA[3:0]$29460 3/3: $1$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_ADDR[3:0]$29459 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$29453'. 18.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 18.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29449_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29444_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29439_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29436_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29440_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29441_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29445_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29437_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29446_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29450_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29442_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29451_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29438_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29447_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29443_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:207$29448_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454'. created $dff cell `$procdff$29504' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454'. created $dff cell `$procdff$29505' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/share/synlig/ecp5/cells_sim.v:223$29452_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454'. created $dff cell `$procdff$29506' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$29453'. created direct connection (no actual register cell created). 18.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:0$29478'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:221$29454'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/usr/local/share/synlig/ecp5/cells_sim.v:213$29453'. Cleaned up 1 empty switch. 18.42.3.12. Executing OPT_EXPR pass (perform const folding). 18.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$6213 $auto$simplemap.cc:126:simplemap_reduce$6222 $auto$simplemap.cc:38:simplemap_not$19921 $auto$ff.cc:266:slice$9358 $auto$dfflegalize.cc:941:flip_pol$27833 $auto$ff.cc:485:convert_ce_over_srst$27831 $auto$simplemap.cc:126:simplemap_reduce$6215 $auto$simplemap.cc:126:simplemap_reduce$6211 $auto$simplemap.cc:126:simplemap_reduce$6209 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$27119 $auto$ff.cc:266:slice$9703 $auto$simplemap.cc:126:simplemap_reduce$9845 $auto$simplemap.cc:126:simplemap_reduce$9830 $auto$ff.cc:266:slice$9704 $auto$ff.cc:266:slice$9705 $auto$simplemap.cc:126:simplemap_reduce$17732 $auto$simplemap.cc:75:simplemap_bitop$17718 $auto$simplemap.cc:267:simplemap_mux$9812 $auto$simplemap.cc:225:simplemap_logbin$9815 $auto$simplemap.cc:196:simplemap_lognot$9835 $auto$simplemap.cc:126:simplemap_reduce$9833 $auto$simplemap.cc:126:simplemap_reduce$9831 $auto$opt_expr.cc:617:replace_const_cells$27015 $auto$simplemap.cc:267:simplemap_mux$17716 $auto$simplemap.cc:126:simplemap_reduce$17730 $auto$simplemap.cc:126:simplemap_reduce$17727 $auto$simplemap.cc:75:simplemap_bitop$17720 $auto$simplemap.cc:196:simplemap_lognot$9850 $auto$simplemap.cc:126:simplemap_reduce$9848 $auto$simplemap.cc:126:simplemap_reduce$9846 $auto$opt_expr.cc:617:replace_const_cells$27013 $auto$ff.cc:266:slice$9706 $auto$simplemap.cc:126:simplemap_reduce$9206 $auto$simplemap.cc:225:simplemap_logbin$9769 $auto$simplemap.cc:196:simplemap_lognot$9779 $auto$simplemap.cc:126:simplemap_reduce$9777 $auto$opt_expr.cc:617:replace_const_cells$27011 $auto$simplemap.cc:267:simplemap_mux$17717 $auto$simplemap.cc:126:simplemap_reduce$17735 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$27117 $auto$ff.cc:266:slice$9552 $auto$simplemap.cc:126:simplemap_reduce$9683 $auto$simplemap.cc:126:simplemap_reduce$9652 $auto$ff.cc:266:slice$9553 $auto$simplemap.cc:38:simplemap_not$18958 $auto$ff.cc:266:slice$9554 $auto$simplemap.cc:126:simplemap_reduce$9688 $auto$simplemap.cc:126:simplemap_reduce$9684 $auto$simplemap.cc:126:simplemap_reduce$9657 $auto$simplemap.cc:126:simplemap_reduce$9653 $auto$simplemap.cc:38:simplemap_not$18959 $auto$ff.cc:266:slice$9555 $auto$simplemap.cc:38:simplemap_not$18960 $auto$ff.cc:266:slice$9556 $auto$simplemap.cc:126:simplemap_reduce$9685 $auto$simplemap.cc:126:simplemap_reduce$9654 $auto$simplemap.cc:38:simplemap_not$18961 $auto$ff.cc:266:slice$9557 $auto$simplemap.cc:38:simplemap_not$18962 $auto$ff.cc:266:slice$9558 $auto$simplemap.cc:126:simplemap_reduce$9660 $auto$simplemap.cc:126:simplemap_reduce$9658 $auto$simplemap.cc:126:simplemap_reduce$9655 $auto$ff.cc:266:slice$9559 $auto$simplemap.cc:225:simplemap_logbin$9637 $auto$simplemap.cc:196:simplemap_lognot$9664 $auto$simplemap.cc:126:simplemap_reduce$9662 $auto$ff.cc:266:slice$9560 $auto$simplemap.cc:225:simplemap_logbin$9636 $auto$simplemap.cc:196:simplemap_lognot$9695 $auto$simplemap.cc:126:simplemap_reduce$9693 $auto$simplemap.cc:126:simplemap_reduce$9691 $auto$simplemap.cc:126:simplemap_reduce$9689 $auto$simplemap.cc:126:simplemap_reduce$9686 $auto$simplemap.cc:38:simplemap_not$18963 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$13551 $auto$simplemap.cc:38:simplemap_not$16665 $auto$ff.cc:266:slice$9425 $auto$dfflegalize.cc:941:flip_pol$27973 $auto$ff.cc:485:convert_ce_over_srst$27971 $auto$simplemap.cc:126:simplemap_reduce$6344 $auto$simplemap.cc:126:simplemap_reduce$6342 $auto$simplemap.cc:126:simplemap_reduce$8860 $auto$simplemap.cc:126:simplemap_reduce$6406 Found an SCC: $auto$ff.cc:266:slice$9708 $auto$dfflegalize.cc:941:flip_pol$27977 $auto$ff.cc:266:slice$9715 $auto$dfflegalize.cc:941:flip_pol$27991 $auto$simplemap.cc:38:simplemap_not$17647 $auto$ff.cc:266:slice$9714 $auto$dfflegalize.cc:941:flip_pol$27989 $auto$ff.cc:266:slice$9713 $auto$dfflegalize.cc:941:flip_pol$27987 $auto$ff.cc:266:slice$9712 $auto$dfflegalize.cc:941:flip_pol$27985 $auto$simplemap.cc:126:simplemap_reduce$9867 $auto$simplemap.cc:38:simplemap_not$17644 $auto$ff.cc:266:slice$9711 $auto$dfflegalize.cc:941:flip_pol$27983 $auto$ff.cc:266:slice$9709 $auto$dfflegalize.cc:941:flip_pol$27979 $auto$simplemap.cc:126:simplemap_reduce$9866 $auto$simplemap.cc:38:simplemap_not$17643 $auto$ff.cc:266:slice$9710 $auto$dfflegalize.cc:941:flip_pol$27981 $auto$simplemap.cc:126:simplemap_reduce$9870 $auto$simplemap.cc:126:simplemap_reduce$9865 $auto$opt_expr.cc:617:replace_const_cells$27111 $auto$ff.cc:266:slice$9707 $auto$dfflegalize.cc:941:flip_pol$27975 $auto$simplemap.cc:126:simplemap_reduce$9875 $auto$simplemap.cc:126:simplemap_reduce$9873 $auto$simplemap.cc:126:simplemap_reduce$9871 $auto$simplemap.cc:126:simplemap_reduce$9868 $auto$simplemap.cc:38:simplemap_not$17646 Found an SCC: $auto$ff.cc:266:slice$5944 $auto$ff.cc:479:convert_ce_over_srst$27813 $auto$ff.cc:266:slice$5943 $auto$ff.cc:479:convert_ce_over_srst$27811 $auto$ff.cc:266:slice$5942 $auto$ff.cc:479:convert_ce_over_srst$27809 $auto$ff.cc:266:slice$5941 $auto$ff.cc:479:convert_ce_over_srst$27807 $auto$alumacc.cc:485:replace_alu$3371.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$3371.slice[24].ccu2c_i $auto$ff.cc:266:slice$5940 $auto$ff.cc:479:convert_ce_over_srst$27805 $auto$alumacc.cc:485:replace_alu$3371.slice[28].ccu2c_i $auto$ff.cc:266:slice$5945 $auto$ff.cc:479:convert_ce_over_srst$27815 $auto$ff.cc:266:slice$5946 $auto$ff.cc:479:convert_ce_over_srst$27817 $auto$simplemap.cc:126:simplemap_reduce$16377 $auto$simplemap.cc:38:simplemap_not$16303 $auto$alumacc.cc:485:replace_alu$3371.slice[30].ccu2c_i $auto$ff.cc:266:slice$5947 $auto$ff.cc:479:convert_ce_over_srst$27819 $auto$simplemap.cc:126:simplemap_reduce$13661 Found 6 SCCs in module processorci_top. Found 6 SCCs. 18.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.6. Executing PROC pass (convert processes to netlists). 18.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 18.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 18.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 18.42.6.4. Executing PROC_INIT pass (extract init attributes). 18.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 18.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 18.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 18.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 18.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 18.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 18.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 18.42.6.12. Executing OPT_EXPR pass (perform const folding). 18.42.7. Executing TECHMAP pass (map to technology primitives). 18.42.7.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 18.42.8. Executing OPT pass (performing simple optimizations). 18.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 18.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 18.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 18.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 18.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 18.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 18.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 18.42.8.9. Finished OPT passes. (There is nothing left to do.) 18.42.9. Executing TECHMAP pass (map to technology primitives). 18.42.9.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_map.v Parsing Verilog input from `/usr/local/share/synlig/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 18.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~519 debug messages> 18.42.10. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_model.v Parsing Verilog input from `/usr/local/share/synlig/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 18.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 18.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 18.42.14. Executing TECHMAP pass (map to technology primitives). 18.42.14.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/techmap.v Parsing Verilog input from `/usr/local/share/synlig/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 18.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 18.42.15. Executing OPT pass (performing simple optimizations). 18.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 18.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 18.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 18.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 18.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 18.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 18.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 18.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 18.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 18.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 18.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 18.42.15.16. Finished OPT passes. (There is nothing left to do.) 18.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 18.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 5657 cells with 35200 new cells, skipped 4165 cells. replaced 4 cell types: 1373 $_OR_ 174 $_XOR_ 70 $_ORNOT_ 4040 $_MUX_ not replaced 8 cell types: 16 $scopeinfo 421 $_NOT_ 1126 $_AND_ 1373 TRELLIS_FF 1 $__ABC9_SCC_BREAKER 196 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 516 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 516 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 18.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 18.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 15211 AND gates and 43610 wires from module `processorci_top' to a netlist network with 3450 inputs and 1173 outputs. 18.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 18.42.17.5. Executing ABC9. Running ABC command: "built in abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 3450/ 1173 and = 14213 lev = 36 (2.81) mem = 0.36 MB box = 712 bb = 516 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 3450/ 1173 and = 20478 lev = 53 (2.59) mem = 0.44 MB ch = 2236 box = 712 bb = 516 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 20478. Ch = 1790. Total mem = 5.26 MB. Peak cut mem = 0.23 MB. ABC: P: Del = 5619.00. Ar = 16650.0. Edge = 19263. Cut = 232485. T = 0.11 sec ABC: P: Del = 5582.00. Ar = 16646.0. Edge = 19217. Cut = 228422. T = 0.11 sec ABC: P: Del = 5582.00. Ar = 8551.0. Edge = 19277. Cut = 513994. T = 0.21 sec ABC: F: Del = 5582.00. Ar = 6303.0. Edge = 16589. Cut = 410226. T = 0.18 sec ABC: A: Del = 5582.00. Ar = 5599.0. Edge = 14793. Cut = 402110. T = 0.27 sec ABC: A: Del = 5582.00. Ar = 5498.0. Edge = 14685. Cut = 398221. T = 0.26 sec ABC: Total time = 1.14 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 3450/ 1173 and = 13057 lev = 32 (2.65) mem = 0.35 MB box = 712 bb = 516 ABC: Mapping (K=7) : lut = 3668 edge = 14477 lev = 11 (1.24) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 32 mem = 0.18 MB ABC: LUT = 3668 : 2=222 6.1 % 3=811 22.1 % 4=1913 52.2 % 5=519 14.1 % 6=68 1.9 % 7=135 3.7 % Ave = 3.95 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 13.19 seconds, total: 13.19 seconds 18.42.17.6. Executing AIGER frontend. <suppressed ~9258 debug messages> Removed 18817 unused cells and 34395 unused wires. 18.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 3687 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 196 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 516 ABC RESULTS: input signals: 604 ABC RESULTS: output signals: 321 Removing temp directory. 18.42.18. Executing TECHMAP pass (map to technology primitives). 18.42.18.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/abc9_unmap.v Parsing Verilog input from `/usr/local/share/synlig/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 18.42.18.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~1248 debug messages> Removed 438 unused cells and 52184 unused wires. 18.43. Executing TECHMAP pass (map to technology primitives). 18.43.1. Executing Verilog-2005 frontend: /usr/local/share/synlig/ecp5/cells_map.v Parsing Verilog input from `/usr/local/share/synlig/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 18.43.2. Continuing TECHMAP pass. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. Using template $paramod$b37e62d0dd2269ea691d26c59bccb55e4d588045\$lut for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$e0bdbbec629f9ffb2ab0bfea0b9ab99e3c3f82d2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$5a3d8a2d0f8388ce80174b2e14473704d015aeff\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e\$lut for cells of type $lut. Using template $paramod$8dd42bf81ffad3d97e207e1565310c97cc60f1a7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$99b0ba94092ae0b544f25d7a7bfbffc967b1c1f1\$lut for cells of type $lut. Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$f63fe32f78d5f3c5de711945c592c8c5ec2303ae\$lut for cells of type $lut. Using template $paramod$11d98a734fddb972e4bcf061987d6c0007a7bbfa\$lut for cells of type $lut. Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$8df048773d683cb333dd5b49bcff8c9e90cbac43\$lut for cells of type $lut. Using template $paramod$1edf9c530bdf99659774b3d2ed34a16521f84c51\$lut for cells of type $lut. Using template $paramod$f185cd0aad2bca0fb298455c739c86a3ed2ebc15\$lut for cells of type $lut. Using template $paramod$7bccb9c410d396b7f6c8d1f48396148fc5f7efcd\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$87c81ad76cb201ea3dcc1353fa1c69357a621825\$lut for cells of type $lut. Using template $paramod$e968bfb454409f52f8a3680baeade174f67481b3\$lut for cells of type $lut. Using template $paramod$dfb43a0c594afb2a0305af3df72b3f7b4090611a\$lut for cells of type $lut. Using template $paramod$1e05dc6f7f59d7ec95e6e7485cfbde79b1ef3e6a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$27fb5fb8428f1042086729d0b0a954c9b1e1d978\$lut for cells of type $lut. Using template $paramod$ecc069ca9fcf74b6bef98c0ae2bb6d920c8aa107\$lut for cells of type $lut. Using template $paramod$bf8ea3449b4be75c7a9b0520316a412c1e7f7b2f\$lut for cells of type $lut. Using template $paramod$a960ec10664880420507457ef2d2cb13d760b3b1\$lut for cells of type $lut. Using template $paramod$6be1c8f14b3d20f109fab904f0aa9f4d6a208357\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$87659d35eed63507adbc882972cd66436315bdbc\$lut for cells of type $lut. Using template $paramod$69616d8ade62467fa999c33011951c6376a674c9\$lut for cells of type $lut. Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut. Using template $paramod$06bfc315e677da734aae83067c97393b98ea6dc4\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$f32bdd7cc07438f72cd437b3c5a28e8ae84afc03\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$6560d34ccfbd00e31297ee2463c8917174f13a56\$lut for cells of type $lut. Using template $paramod$0a782ed7ca84d665ddfb0df6ed4823d0aadea6bc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$fa2b97458de3878a623acac2346cd4a206161196\$lut for cells of type $lut. Using template $paramod$bb0f83b6fe751214bdd078b13245cd04d4d2b0b8\$lut for cells of type $lut. Using template $paramod$d1625ac9252291b6d8389f0dc44b6e90e417ba21\$lut for cells of type $lut. Using template $paramod$56c773b3f56f52fffab804322896df512a7a3969\$lut for cells of type $lut. Using template $paramod$1b0c8384e06903e9456947e835226d06a2caae47\$lut for cells of type $lut. Using template $paramod$c46e40f63b70ae6e47932756b5c21314e4b1be42\$lut for cells of type $lut. Using template $paramod$787e63c9e1fbffe8b4370f16a4735cb18ea1b5cb\$lut for cells of type $lut. Using template $paramod$077f0a484d58dac4e3c69c4cba040f8b2cba23bf\$lut for cells of type $lut. Using template $paramod$80920d9cf7f4787a43d74cb79933aea421e4b765\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$7ae625d4b67f60237891778aa86dbbe195e8cdbf\$lut for cells of type $lut. Using template $paramod$ce7e467b4ba43d9f323396fb5b149f2d84a89095\$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut. Using template $paramod$55290dc5b2d325b1a51b6c31876bbb759b0b4b79\$lut for cells of type $lut. Using template $paramod$a05df8efa9ef190a16528865520e971426538e07\$lut for cells of type $lut. Using template $paramod$eeefacbf6bf0344271add8dd4f3c603081de192b\$lut for cells of type $lut. Using template $paramod$5a883707b150ebf127dd2794b45a5067b19dea3f\$lut for cells of type $lut. Using template $paramod$0c61fb9db42ebd45e1e438f5020b596ef1633926\$lut for cells of type $lut. Using template $paramod$0ab0774a363f903f40ea383f3d9e598861c8a083\$lut for cells of type $lut. Using template $paramod$90d22152c41a40996833edeaa682a043ece939f4\$lut for cells of type $lut. Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84\$lut for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$0260ba258d9e1a608f5e349a51c65fb9e84b9283\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$0ae7705354ab4bfd071e2551e0df024a40a698f7\$lut for cells of type $lut. Using template $paramod$5bf555c50d0258e989b3a24dbf1900d587953838\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$89de210e11c16138f89688ab911d555676147dc8\$lut for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut. Using template $paramod$aff99c137af40c9f3a2f8bff1c989a4f5c51cd38\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$a6752c57bf9873c173efab040b6ae6fc357502f5\$lut for cells of type $lut. Using template $paramod$1f7ee4422e50154f59ed6c3a7ea550a55910c717\$lut for cells of type $lut. Using template $paramod$0477eb7c9cdfa97147568c4e7b11a4dcd6f4f17a\$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. Using template $paramod$d051b8be9e1759817bcd39d329efabc87e24ae6a\$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$a4f43488fbe7f64f800bdade5fff2f5a3e003efe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$b0878fe1110407fee18c8a936649bef81b1047a4\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut. Using template $paramod$267cb9a6978aefb4130af22060ba21ab6389a35a\$lut for cells of type $lut. Using template $paramod$91d74288e6b8d6f72d700c3e07967cffe209e738\$lut for cells of type $lut. Using template $paramod$b7592fac6d92417dfa6088c1615ec851e9a6918c\$lut for cells of type $lut. Using template $paramod$828096678386a4453f064d41cbed89443fa1b5d0\$lut for cells of type $lut. Using template $paramod$362fdef7bf08f7abf3063060492a1f414edeab3e\$lut for cells of type $lut. Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$ec455f199d180eb8df4efd9e4415a9fd4a5558f1\$lut for cells of type $lut. Using template $paramod$73e4dd6d876610d86f9709e540651b3d92ab603a\$lut for cells of type $lut. Using template $paramod$57baf56de1ae505c4ca014d3cc567b357f265759\$lut for cells of type $lut. Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut. Using template $paramod$920c30c965b89e85bc6c38e2211cf7b09d4fb168\$lut for cells of type $lut. Using template $paramod$ffcebf84761e736a9820940d5ddf577254c9e8f3\$lut for cells of type $lut. Using template $paramod$55cd24dc75c9df441970d5c4021e3e4022d76c6c\$lut for cells of type $lut. Using template $paramod$a457137fd2e705edc741a5ae47f1f8e8e1d2e15d\$lut for cells of type $lut. Using template $paramod$9ee1cec485b05d51e3035b95b44c9cb044a64a40\$lut for cells of type $lut. Using template $paramod$479ea6fe838844a478715882cf7334706d3120a7\$lut for cells of type $lut. Using template $paramod$95e3b069aff4a6adc0a3d90d66a109cc8ab110fa\$lut for cells of type $lut. Using template $paramod$7ba1e49cc7580287cbc6a3d81161ca68cd4b4d21\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut. Using template $paramod$4bca80b1a0ebd55cc472c8149b835530d696f6cd\$lut for cells of type $lut. Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut. Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut. Using template $paramod$696de6c060b80835e9c6fe2f7996811190ca441f\$lut for cells of type $lut. Using template $paramod$fd612331c30e9d253090fdb1f8a32e43d927e731\$lut for cells of type $lut. Using template $paramod$b14daf751d1d3d4f54e8096fdc714e8989ea5136\$lut for cells of type $lut. Using template $paramod$d22f57163d7bd9afc6b86c57ba978a218f3f7860\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$214030b75530a7dfe65411cfed7a9b1c9d0ddb26\$lut for cells of type $lut. Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut. Using template $paramod$5dd0a747ca3c1c3f3fa5939c11607b40c5c78b01\$lut for cells of type $lut. Using template $paramod$fbbae5a33259a57760a13dc86f71a6c105f6eead\$lut for cells of type $lut. Using template $paramod$be0ecd3ee852b1a24766050d2002c580421b74ff\$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut. Using template $paramod$68ed5886f51669d7dd7ce9aefa91b8b919b23721\$lut for cells of type $lut. Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut. Using template $paramod$139da405b825e7c50b83915af4de3ca91426b4cd\$lut for cells of type $lut. Using template $paramod$af1505355cee938b11b5062beda37680a2196d57\$lut for cells of type $lut. Using template $paramod$755260cedd3b8adcdc23261729688cf1d50e272a\$lut for cells of type $lut. Using template $paramod$cffcdcfefee28cb7804202d59fcab831562282d3\$lut for cells of type $lut. Using template $paramod$6d60dc16ae773211e6f9df665626d814d4433c6f\$lut for cells of type $lut. Using template $paramod$808901abc6daca2c334e1f2d6c7a4e99281d5ced\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut. Using template $paramod$c630b607ec452818644043d3dc460bc46d3023df\$lut for cells of type $lut. Using template $paramod$96a15bcfc7bc0ca82326ee51ba7a664f8f047fd6\$lut for cells of type $lut. Using template $paramod$5724694d96b585a5fc2e10b2a719ecbe75401256\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011111 for cells of type $lut. Using template $paramod$faeedcc045c5fd2fbd2cb0c24e50ae83fb289140\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$165be24785e4097ccfb74473951770165dd92dfc\$lut for cells of type $lut. Using template $paramod$d0efe6a4c5c1b8e7a1ea68a3035c784944bbb954\$lut for cells of type $lut. Using template $paramod$22dec7e8c4f4b1c3e62879fa2207e0c39047bbd3\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$edc7a7abfe65ffb5a448531d22d19cedbe7f7a70\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$bacdb2105cbfbe75cfbcc2fb021fd3aba864526b\$lut for cells of type $lut. Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod$37203517188e0e81c6d1574dd1c274ed56646adf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. Using template $paramod$756861dd4dfe0a5b9de37af2241117b1958e2ffe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101111 for cells of type $lut. Using template $paramod$6d937d8a77a6356f2f9cc89d5646fb948bb8225e\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$7c5af9f666cf38ac789ff4dbbb553e78a6e32f63\$lut for cells of type $lut. Using template $paramod$6d473153bc0717e92e23b21a92c71fa7e337bf4b\$lut for cells of type $lut. Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027\$lut for cells of type $lut. Using template $paramod$c7754eeb17b54dfe53ea4a973db3714d78ced2f9\$lut for cells of type $lut. Using template $paramod$04878a25687d8c6ebdb55a311552f7efcd0cac70\$lut for cells of type $lut. Using template $paramod$efc60783c939ae41b2f3555af407b17c007b27f8\$lut for cells of type $lut. Using template $paramod$77d6c852c4fa46d427070381e5194d5f2c61af9e\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$d97ee90637a1919112aecc4184ba4e2e7763d9ac\$lut for cells of type $lut. Using template $paramod$f90e2ec6b7a4c6db6f7a3682dfa870e7c33a78da\$lut for cells of type $lut. Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut. Using template $paramod$ae9b8688208bc968e066759f867620e9ddf86c4d\$lut for cells of type $lut. Using template $paramod$584e4a38268562e2142ef24a574198cdf8d42be8\$lut for cells of type $lut. Using template $paramod$38cb34907addf5cf72818a31c77fe410720c6567\$lut for cells of type $lut. Using template $paramod$592a80abc08dd12fe78e8ba336f582a4ddb301bd\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$5f87a93ef4cf35c280d95d6ee0abe4a24b1120ad\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$c5a72be5b8063575c133518a44f31db91f4eaba0\$lut for cells of type $lut. Using template $paramod$a06aa83841491819ea0cf939b57a7ccfb595b114\$lut for cells of type $lut. Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut. Using template $paramod$1cabbe2f17ea824b0f9f091fd1dc13fff0b3a362\$lut for cells of type $lut. Using template $paramod$9616fecedc1a6ce839b990a3156875e06908d6fa\$lut for cells of type $lut. Using template $paramod$a38225493adc19623c8cba71d7a6eb8be6da59f7\$lut for cells of type $lut. Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut. Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut. Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut. Using template $paramod$07fef70bb3e4892ea09b41636536ff249cf86fe8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod$1bf8193f89e07c76cd4e087f3f6a1030c4457b02\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$329bdc05585115f4ba0e3fcd3ad354e6446e3185\$lut for cells of type $lut. Using template $paramod$84cb95f8ff0d6a7447159d4e808aa714df704104\$lut for cells of type $lut. Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut. Using template $paramod$96b88e987a5a94f6555d50cd65fde7a290b148c8\$lut for cells of type $lut. Using template $paramod$f520e14adfd7009a3da8e79e5c0cb74f90a918a1\$lut for cells of type $lut. Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$f8e1bdecd38a1f2a88371fc52b96bff86506a2c7\$lut for cells of type $lut. Using template $paramod$f3dd377dcc11d5c9177d0bcf0d430f2405c6b456\$lut for cells of type $lut. Using template $paramod$2f216af0fda5d2c9dcbd73e07a35d81dd3199a62\$lut for cells of type $lut. Using template $paramod$469e5449f421a6d4ce864b18148ed2a4e2247a7d\$lut for cells of type $lut. Using template $paramod$a2f01eec25eb92d08608e73046bdb01195b11a42\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$5300828da4841674191ef4a0ff764d911064526f\$lut for cells of type $lut. Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$f65af1b660a013aeaba9a5dc41e6bdede642e3c3\$lut for cells of type $lut. Using template $paramod$3ec83cc0e0ec241030d7c40596e80d62c44c0f57\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$994d90e9e38bc4b3e41611c486bc42235dc97a88\$lut for cells of type $lut. Using template $paramod$41017bbfbc4d5b6aa9cc0bcf2514b82848f08ba8\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9\$lut for cells of type $lut. Using template $paramod$c5966e98773f1c185668bb7f5b6385d25e498be1\$lut for cells of type $lut. Using template $paramod$e9df7bcc76d24787206a64b3178b0e90b10ed7b1\$lut for cells of type $lut. Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut. Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut. Using template $paramod$ee211c3a0b6e08cd0edbf19d0e92a42ad70d569b\$lut for cells of type $lut. Using template $paramod$8e3ca194a0bba00a67249d0228c1b54c83044193\$lut for cells of type $lut. Using template $paramod$1c6c5e2dd54a0d65b24c58a2931678ac433cd362\$lut for cells of type $lut. Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c\$lut for cells of type $lut. Using template $paramod$911afe292eabae4c0c764aa65dd806d97d273557\$lut for cells of type $lut. Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut. Using template $paramod$c7b80ba430fcbff15d6bf260d454531db01b4698\$lut for cells of type $lut. Using template $paramod$05dd5d01546eff9da45f32c923ffbe0f9afdb118\$lut for cells of type $lut. Using template $paramod$77b566652a2449bae604a937e67f0c9bd49bb4a7\$lut for cells of type $lut. Using template $paramod$056d5a9438b208d5710860d404f760cee6ed2e40\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$d7ebeaef7104bab98c2de3262f04b026b127e6ce\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod$c5af5678e76c2f7359a5d42d1a07c7e309f457a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut. Using template $paramod$8a804b558e52ade6b8f5c28a56bcdd8cbb8abc7a\$lut for cells of type $lut. Using template $paramod$eb117e6cc6cf95759acbf9d33d7a66af3bc722fb\$lut for cells of type $lut. Using template $paramod$7929d818ff6cdab401756b40b10229878e94bd76\$lut for cells of type $lut. Using template $paramod$b3fd76af408ac5b5c1c11848f16097083cebf6fa\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$772c5f659e8e74aa2af7722fdbc641ce9b343490\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$e4d96f9bc2b931aa6c2488d28db99e95b7d85bcd\$lut for cells of type $lut. Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut. Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$e3232e0a90c8340ac10328f8e4e3ccd56fa7779b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$1d8da67e55226ee6f849b82c7c3ba5690a649089\$lut for cells of type $lut. Using template $paramod$4347d0f13de2ec73cebbbd39be8b55c50cb62a8f\$lut for cells of type $lut. Using template $paramod$69a9b041903cf6361b3361401b55e0bda8a97a88\$lut for cells of type $lut. Using template $paramod$cce4ac97db31dc53ae326437a5999af9a1eaaf37\$lut for cells of type $lut. Using template $paramod$9b6b8aa7625395c9335216e6d018599e368f4a01\$lut for cells of type $lut. Using template $paramod$52b16e02f9802938606ca1b07736b1ecf69f6eb1\$lut for cells of type $lut. Using template $paramod$07b8f12a43f56e5efa24153a1f14de8130ae18f9\$lut for cells of type $lut. Using template $paramod$7f88ae8b0ca78f7b736f446522956805c49fb79f\$lut for cells of type $lut. Using template $paramod$e05e4793e0e0e691922faf1582be264bfde2083a\$lut for cells of type $lut. Using template $paramod$9b39edf2b4be36681a7ce473537f2a556c611cd6\$lut for cells of type $lut. Using template $paramod$b465360eb4899fbf002553cea1e1b663b6668e97\$lut for cells of type $lut. Using template $paramod$ddb47b249929f98972c955e761889ead1a770cff\$lut for cells of type $lut. Using template $paramod$d96938b933811903763c8fc48238ba3a4fe3fe61\$lut for cells of type $lut. Using template $paramod$ca9123fde9180fccca7de99c191495af94099015\$lut for cells of type $lut. Using template $paramod$b982a14353084550ade100e35054c7cf02f76051\$lut for cells of type $lut. Using template $paramod$dd4ab03166f383203a04ee31bbd3d309e5cf35af\$lut for cells of type $lut. Using template $paramod$b857c4e37700f0b5c867bc0f3652592e4f3625f7\$lut for cells of type $lut. Using template $paramod$b7e1f0e44e1823882f3ed6063906649af1d55c48\$lut for cells of type $lut. Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut. Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut. Using template $paramod$dfbd57d69c129426ccd4849cefb8b1cfde58c8b7\$lut for cells of type $lut. Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01\$lut for cells of type $lut. Using template $paramod$fa90e6b4ff54c9a3f6bea754646eebea90c24aad\$lut for cells of type $lut. Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut. Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut. Using template $paramod$92730f5a8a4aea1eaf6c696475735f4203b441f9\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut. Using template $paramod$8417bd18654099a39056bad5f2790a28443b19e5\$lut for cells of type $lut. Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut. Using template $paramod$36a9ba010714a6e842d8f5e80a03649671ff94c6\$lut for cells of type $lut. Using template $paramod$adb84e058b0f32ce56f004e6ffa19883ace75fc0\$lut for cells of type $lut. Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut. Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut. Using template $paramod$4097301b985a22b6a64028421d42078032a45289\$lut for cells of type $lut. Using template $paramod$e7dd21ebe2a209013c5158379d639c69fca86be9\$lut for cells of type $lut. Using template $paramod$e5e3dc179838719e04d23a4718ce6496a825018a\$lut for cells of type $lut. Using template $paramod$5a2c0d15bf795ad3439b61fbba91651be8a816a4\$lut for cells of type $lut. Using template $paramod$fc3b705381336b09688b8db13f1530494dc3ca1c\$lut for cells of type $lut. Using template $paramod$2f9ab631c2c292dd343722365a65cff006ff6c9a\$lut for cells of type $lut. Using template $paramod$a133bd36ff4c016b7946de70b5b33064db8a3043\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$bb49d93b5c92bcbcf12a57800e969ff257ea87f3\$lut for cells of type $lut. Using template $paramod$f101fd32db6b0e2d2877d217811a9336d9e7af23\$lut for cells of type $lut. Using template $paramod$405b9a456570575505f8f3bb7a80fc8e29569905\$lut for cells of type $lut. Using template $paramod$66e806f5c36d785986a374982f6eac862966558b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$bf58e52cf1673fd938f656d7468b5e18a1334297\$lut for cells of type $lut. Using template $paramod$2a0d03f6478b694ef257f90d2fb1298fc509ab03\$lut for cells of type $lut. Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut. Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. Using template $paramod$83f8a77a82b30303d0d950f0eb545c79a45eece4\$lut for cells of type $lut. Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut. Using template $paramod$0f73e4d084e2665d715e2e36ebfbff963101ccea\$lut for cells of type $lut. Using template $paramod$a0a9aec7a5b82e6c253757a4bee106aab298a24f\$lut for cells of type $lut. Using template $paramod$746162a52dfe2dc95e0be8c773968141092fae9d\$lut for cells of type $lut. Using template $paramod$6b85005f52472512b211286b920c973a28f5655b\$lut for cells of type $lut. Using template $paramod$0cd6624728e68e87f93b3d27aef965436c9cc353\$lut for cells of type $lut. Using template $paramod$3a4677fef5f71333584acb6594004c8a5b45d3ca\$lut for cells of type $lut. Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut. Using template $paramod$9ec9d5b61a93936e5e60f3f314419bd757957188\$lut for cells of type $lut. Using template $paramod$94593104a360a40a55729e2bebaa210e6374fb7b\$lut for cells of type $lut. Using template $paramod$9553a4a69afa56381d93681858738ddbf7c42bf8\$lut for cells of type $lut. Using template $paramod$3128ede2c998148b098fc8ae777015bb2ba1835f\$lut for cells of type $lut. Using template $paramod$6bf2caa40fb1acb49d1a3518d072e0f81faf3832\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$2bdd43afe49ffa195fcadfd424faaa35608b7a22\$lut for cells of type $lut. Using template $paramod$4d3d51468293cc099a6c7c86b8a8065a39938e2c\$lut for cells of type $lut. Using template $paramod$1bb26330f94b9f62b6acb8cc6af86c50c7c3906f\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$949912d41b6703327b37a3cbe8a7a7bc923219b7\$lut for cells of type $lut. Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut. Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut. Using template $paramod$6b833746889ee78adce2af9a3c8eac2886a1f7a5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$1b6589a5b00bbad8e5635e71249e07e10bfc1308\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$5e96c51e862795fcf5123ad90ed33b3bddf109cb\$lut for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod$6efbfa72ec6f4430f746a9eeec729763cf9dc3a0\$lut for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut. Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. Using template $paramod$4e92aaae4d6dc82ec4f0a8579ea7380954206873\$lut for cells of type $lut. Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab\$lut for cells of type $lut. Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b\$lut for cells of type $lut. Using template $paramod$f377b83bfd4274750d2cc48e6e3fa52263d09667\$lut for cells of type $lut. Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e\$lut for cells of type $lut. Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821\$lut for cells of type $lut. Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633\$lut for cells of type $lut. Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut. Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2\$lut for cells of type $lut. Using template $paramod$9640380942618015231dc80e07fe9e6281ac216a\$lut for cells of type $lut. Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99\$lut for cells of type $lut. Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2\$lut for cells of type $lut. Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut. Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut. Using template $paramod$de3406006c16cf7256a0a2fdcbb1597ad8f6cb54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$11117e26c2e3f501cbd511ff6e86da30ada6dd62\$lut for cells of type $lut. Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut. Using template $paramod$19457468c03b53ec09024ada785c6816b7d0407d\$lut for cells of type $lut. Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut. Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010101 for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod$84f4f1db72921f11c5ff5a4dc511dfd4d3da404b\$lut for cells of type $lut. Using template $paramod$7a96d62884cccd5a8d3fffeab24306862b39f37c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut. Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut. Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut. Using template $paramod$223a1a0bfc3038108c8c5d096bc8fdc50fd540b0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut. Using template $paramod$b1eed235f4595099c4d6771c299862db0590e4ad\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut. Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut. Using template $paramod$22ca34e45145bb3eb2ce78f5debe5bf61645321e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$bd52683f5d7d773e55760c18e3bff8f6a3bc6c6d\$lut for cells of type $lut. Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$fe09243366e8c484d0c6bb5fc5e978dc10c22587\$lut for cells of type $lut. Using template $paramod$50d1e2cf3af42c32d48a486e5b0bef1dbacdd328\$lut for cells of type $lut. No more expansions possible. <suppressed ~9877 debug messages> 18.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$18251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$17899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$10059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$10047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$10082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$10464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$10511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$10647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$10879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11066.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$11971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$11990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$12037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$12182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$12639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$12772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$12907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$12926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$13319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$13665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$13944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$13963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$13963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$14970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$14970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$15584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$15837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$15856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$15878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$15983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$16034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$16857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$16968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$16968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$17908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$17951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$17951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18472.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$18787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$18819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$18936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$19008.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$19027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$19027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$19052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$19052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10659.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$6560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$6575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$6619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$6959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$10431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8661.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$12585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9761.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$16306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$14243.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$flatten\u_Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.sv:176$782_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$11085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut\u_Controller.Core_Memory.addr_i[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101102.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$100886$lut$aiger100885$9452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101215.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$9592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$9657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$8332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$100886$lut$aiger100885$7432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$8004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$100886$lut$aiger100885$7817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$101327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$100886$lut$aiger100885$7533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Removed 0 unused cells and 10333 unused wires. 18.45. Executing AUTONAME pass. Renamed 676279 objects in module processorci_top (320 iterations). <suppressed ~14667 debug messages> 18.46. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `processorci_top'. Setting top module to processorci_top. 18.46.1. Analyzing design hierarchy.. Top module: \processorci_top 18.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 18.47. Printing statistics. === processorci_top === Number of wires: 6289 Number of wire bits: 16603 Number of public wires: 6289 Number of public wire bits: 16603 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 9132 $scopeinfo 16 CCU2C 196 L6MUX21 473 LUT4 5363 PFUMX 1195 TRELLIS_DPR16X4 516 TRELLIS_FF 1373 18.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 18.49. Executing JSON backend. Warnings: 35 unique messages, 35 total End of script. Logfile hash: c602ece767, CPU: user 39.09s system 0.33s, MEM: 275.07 MB peak Time spent: 33% 1x abc9_exe (13 sec), 16% 1x autoname (6 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Baby-Risco-5 -b colorlight_i9 -l File 'processor_ci_defines.vh' generated for board: 'colorlight_i9'. Final configuration file generated at /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [===== ] 9.27% Loading: [========== ] 18.18% Loading: [============== ] 27.44% Loading: [=================== ] 36.71% Loading: [======================== ] 46.34% Loading: [============================ ] 55.25% Loading: [================================= ] 64.16% Loading: [===================================== ] 73.78% Loading: [========================================== ] 83.05% Loading: [=============================================== ] 92.31% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1308.730 ; gain = 0.023 ; free physical = 1515 ; free virtual = 23831 # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v # read_verilog /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v # read_verilog -sv /eda/processor_ci/rtl/Baby-Risco-5.sv # read_verilog -sv /eda/processor-ci-controller/modules/uart.sv # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv # read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv # read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv # read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv # read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv # read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv # set_param general.maxThreads 16 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "processorci_top" -part "xc7a100tcsg324-1" Command: synth_design -top processorci_top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3878881 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.547 ; gain = 403.746 ; free physical = 374 ; free virtual = 22699 --------------------------------------------------------------------------------- WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Baby-Risco-5.sv:5] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1] INFO: [Synth 8-6157] synthesizing module 'Core' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:1] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:38] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:34] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:11] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/src/core/core.v:1] WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/eda/processor_ci/rtl/Baby-Risco-5.sv:123] WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 10 connections declared, but only 9 given [/eda/processor_ci/rtl/Baby-Risco-5.sv:123] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1] Parameter CYCLES bound to: 32'sb00000000000000000000000000010100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32] INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Baby-Risco-5.sv:175] WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/rtl/Baby-Risco-5.sv:175] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/rtl/Baby-Risco-5.sv:175] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/Baby-Risco-5.sv:5] WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25] WARNING: [Synth 8-3848] Net data_memory_ack in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:119] WARNING: [Synth 8-3848] Net data_memory_read_data in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:120] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/Baby-Risco-5.sv:25] WARNING: [Synth 8-7129] Port func7[6] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[4] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[3] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[2] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[1] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port func7[0] in module ALU_Control is either unconnected or has no load WARNING: [Synth 8-7129] Port readRegister1[4] in module Registers is either unconnected or has no load WARNING: [Synth 8-7129] Port readRegister2[4] in module Registers is either unconnected or has no load WARNING: [Synth 8-7129] Port halt in module Core is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2121.516 ; gain = 492.715 ; free physical = 279 ; free virtual = 22605 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2139.328 ; gain = 510.527 ; free physical = 277 ; free virtual = 22603 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2139.328 ; gain = 510.527 ; free physical = 277 ; free virtual = 22603 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2139.328 ; gain = 0.000 ; free physical = 277 ; free virtual = 22603 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.078 ; gain = 0.000 ; free physical = 256 ; free virtual = 22582 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2287.113 ; gain = 0.000 ; free physical = 253 ; free virtual = 22579 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 203 ; free virtual = 22505 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 203 ; free virtual = 22505 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 203 ; free virtual = 22505 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0101 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- TX_FIFO_IDLE | 0001 | 00 TX_FIFO_READ_FIFO | 0010 | 01 TX_FIFO_WRITE_TX | 0100 | 10 TX_FIFO_WAIT | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 0000 | 0000 VALIDATE_FETCH | 0001 | 1111 DECODE | 0010 | 0001 MEMADR | 0011 | 0010 MEMREAD | 0100 | 0011 iSTATE | 0101 | 0100 * MEMWRITE | 0110 | 0101 EXECUTER | 0111 | 0110 EXECUTEI | 1000 | 1000 JAL | 1001 | 1001 BRANCH | 1010 | 1010 JALR | 1011 | 1011 AUIPC | 1100 | 1100 LUI | 1101 | 1101 ALUWB | 1110 | 0111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'Control_Unit' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT | 001 | 00 RESET_COUNTER | 010 | 01 IDLE | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 209 ; free virtual = 22508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 32 Bit Adders := 4 3 Input 32 Bit Adders := 1 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 6 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 64 Bit Registers := 2 32 Bit Registers := 34 24 Bit Registers := 4 10 Bit Registers := 2 8 Bit Registers := 11 6 Bit Registers := 1 4 Bit Registers := 6 3 Bit Registers := 2 1 Bit Registers := 25 +---RAMs : 64K Bit (2048 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 1 48 Input 64 Bit Muxes := 2 5 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 9 8 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 2 48 Input 24 Bit Muxes := 1 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 4 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 7 15 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 2 9 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 4 2 Input 3 Bit Muxes := 5 10 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 13 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 4 15 Input 2 Bit Muxes := 3 2 Input 1 Bit Muxes := 62 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 5 4 Input 1 Bit Muxes := 3 5 Input 1 Bit Muxes := 11 15 Input 1 Bit Muxes := 10 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-7129] Port readRegister1[4] in module Registers is either unconnected or has no load WARNING: [Synth 8-7129] Port readRegister2[4] in module Registers is either unconnected or has no load WARNING: [Synth 8-7129] Port halt in module Core is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[31] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[30] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[29] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[28] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[27] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[26] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[25] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[24] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[23] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[22] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[21] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[20] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[19] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[18] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[17] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[16] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[15] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[14] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[13] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[1] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[0] in module Memory is either unconnected or has no load WARNING: [Synth 8-7129] Port communication_tx_empty in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port memory_response in module Interpreter is either unconnected or has no load WARNING: [Synth 8-7129] Port intr_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port sck_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port cs_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port mosi_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port miso_o in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rw_i in module Controller is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module processorci_top is either unconnected or has no load --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:40 ; elapsed = 00:01:42 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 253 ; free virtual = 22459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +-------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +-------------+-------------------------+-----------+----------------------+------------------+ |u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | +-------------+-------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:51 ; elapsed = 00:01:53 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 254 ; free virtual = 22460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:53 ; elapsed = 00:01:55 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 261 ; free virtual = 22467 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +-------------+-------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +-------------+-------------------------+-----------+----------------------+------------------+ |u_Controller | Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |u_Controller | Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |u_Controller | Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | +-------------+-------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:57 ; elapsed = 00:01:59 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 266 ; free virtual = 22472 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:07 ; elapsed = 00:02:09 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 246 ; free virtual = 22452 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:07 ; elapsed = 00:02:09 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 244 ; free virtual = 22450 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:08 ; elapsed = 00:02:09 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 254 ; free virtual = 22460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 254 ; free virtual = 22460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 253 ; free virtual = 22460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 253 ; free virtual = 22460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 3| |2 |CARRY4 | 87| |3 |LUT1 | 68| |4 |LUT2 | 212| |5 |LUT3 | 332| |6 |LUT4 | 193| |7 |LUT5 | 389| |8 |LUT6 | 872| |9 |MUXF7 | 172| |10 |MUXF8 | 64| |11 |RAM256X1S | 256| |12 |RAM32M | 2| |13 |RAM32X1D | 4| |14 |FDCE | 32| |15 |FDRE | 1339| |16 |FDSE | 4| |17 |IBUF | 2| |18 |OBUF | 1| |19 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 253 ; free virtual = 22460 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 34 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:02:03 ; elapsed = 00:02:05 . Memory (MB): peak = 2287.113 ; gain = 510.527 ; free physical = 253 ; free virtual = 22459 Synthesis Optimization Complete : Time (s): cpu = 00:02:08 ; elapsed = 00:02:10 . Memory (MB): peak = 2287.113 ; gain = 658.312 ; free physical = 253 ; free virtual = 22459 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2287.113 ; gain = 0.000 ; free physical = 512 ; free virtual = 22718 INFO: [Netlist 29-17] Analyzing 585 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.109 ; gain = 0.000 ; free physical = 526 ; free virtual = 22733 INFO: [Project 1-111] Unisim Transformation Summary: A total of 262 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: e1c0bf5a INFO: [Common 17-83] Releasing license: Synthesis 69 Infos, 86 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:27 ; elapsed = 00:02:23 . Memory (MB): peak = 2351.145 ; gain = 1042.414 ; free physical = 526 ; free virtual = 22733 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2025.193; main = 1748.302; forked = 418.714 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3228.527; main = 2351.113; forked = 973.461 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2415.141 ; gain = 63.996 ; free physical = 557 ; free virtual = 22719 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1fc996e4b Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2522.953 ; gain = 107.812 ; free physical = 398 ; free virtual = 22633 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 180 ; free virtual = 22407 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 182 ; free virtual = 22407 Phase 1 Initialization | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 183 ; free virtual = 22408 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 199 ; free virtual = 22423 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 199 ; free virtual = 22423 Phase 2 Timer Update And Timing Data Collection | Checksum: 1fc996e4b Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 199 ; free virtual = 22423 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 31 inverters resulting in an inversion of 93 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1bc0c3ea5 Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 199 ; free virtual = 22423 Retarget | Checksum: 1bc0c3ea5 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 31 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 14248ad52 Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.6 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 193 ; free virtual = 22418 Constant propagation | Checksum: 14248ad52 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 15593a5a9 Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2767.891 ; gain = 0.000 ; free physical = 193 ; free virtual = 22418 Sweep | Checksum: 15593a5a9 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 15593a5a9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.9 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 BUFG optimization | Checksum: 15593a5a9 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 15593a5a9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.92 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 Shift Register Optimization | Checksum: 15593a5a9 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 15593a5a9 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 Post Processing Netlist | Checksum: 15593a5a9 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2456cf755 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22418 Phase 9.2 Verifying Netlist Connectivity | Checksum: 2456cf755 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 Phase 9 Finalization | Checksum: 2456cf755 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 31 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 1 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 2456cf755 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2799.906 ; gain = 32.016 ; free physical = 193 ; free virtual = 22418 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22418 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 2456cf755 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22417 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 2456cf755 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22417 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22417 Ending Netlist Obfuscation Task | Checksum: 2456cf755 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.906 ; gain = 0.000 ; free physical = 193 ; free virtual = 22417 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 2799.906 ; gain = 448.762 ; free physical = 193 ; free virtual = 22417 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.922 ; gain = 0.000 ; free physical = 195 ; free virtual = 22404 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 155fc0844 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2831.922 ; gain = 0.000 ; free physical = 195 ; free virtual = 22404 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2831.922 ; gain = 0.000 ; free physical = 195 ; free virtual = 22404 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 51d2f34f Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2831.922 ; gain = 0.000 ; free physical = 192 ; free virtual = 22397 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 14dd0e6e9 Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 195 ; free virtual = 22389 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 14dd0e6e9 Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 193 ; free virtual = 22387 Phase 1 Placer Initialization | Checksum: 14dd0e6e9 Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 191 ; free virtual = 22385 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: d02cbedd Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 210 ; free virtual = 22399 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: f52b2935 Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 210 ; free virtual = 22399 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: f52b2935 Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.949 ; gain = 7.027 ; free physical = 210 ; free virtual = 22399 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: eb93f2aa Time (s): cpu = 00:00:26 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 209 ; free virtual = 22392 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 132 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 56 nets or LUTs. Breaked 0 LUT, combined 56 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 208 ; free virtual = 22391 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 56 | 56 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 56 | 56 | 0 | 4 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: f20379f4 Time (s): cpu = 00:00:28 ; elapsed = 00:00:19 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 208 ; free virtual = 22391 Phase 2.4 Global Placement Core | Checksum: 848dcd22 Time (s): cpu = 00:00:56 ; elapsed = 00:00:33 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 610 ; free virtual = 22764 Phase 2 Global Placement | Checksum: 848dcd22 Time (s): cpu = 00:00:56 ; elapsed = 00:00:33 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 610 ; free virtual = 22764 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 90cb473a Time (s): cpu = 00:00:56 ; elapsed = 00:00:33 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 609 ; free virtual = 22763 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 169bff7dd Time (s): cpu = 00:00:57 ; elapsed = 00:00:34 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 608 ; free virtual = 22762 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1c1eed94f Time (s): cpu = 00:00:58 ; elapsed = 00:00:34 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 598 ; free virtual = 22753 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1bdc10a1a Time (s): cpu = 00:00:58 ; elapsed = 00:00:34 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 615 ; free virtual = 22769 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 119463046 Time (s): cpu = 00:01:00 ; elapsed = 00:00:37 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 600 ; free virtual = 22755 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1959c4701 Time (s): cpu = 00:01:00 ; elapsed = 00:00:37 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 600 ; free virtual = 22755 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1896a35d6 Time (s): cpu = 00:01:01 ; elapsed = 00:00:37 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 600 ; free virtual = 22755 Phase 3 Detail Placement | Checksum: 1896a35d6 Time (s): cpu = 00:01:01 ; elapsed = 00:00:37 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 600 ; free virtual = 22755 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 144ec66cb Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 20dad39e8 Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 598 ; free virtual = 22752 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 20dad39e8 Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 598 ; free virtual = 22752 Phase 4.1.1.1 BUFG Insertion | Checksum: 144ec66cb Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 18daafc48 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.1 Post Commit Optimization | Checksum: 18daafc48 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18daafc48 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 18daafc48 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.3 Placer Reporting | Checksum: 18daafc48 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 605 ; free virtual = 22760 Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a00afa4f Time (s): cpu = 00:01:07 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 Ending Placer Task | Checksum: 1309c48de Time (s): cpu = 00:01:08 ; elapsed = 00:00:41 . Memory (MB): peak = 2846.953 ; gain = 15.031 ; free physical = 605 ; free virtual = 22760 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:01:10 ; elapsed = 00:00:43 . Memory (MB): peak = 2846.953 ; gain = 47.047 ; free physical = 605 ; free virtual = 22760 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 595 ; free virtual = 22749 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2846.953 ; gain = 0.000 ; free physical = 595 ; free virtual = 22749 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: e8699282 ConstDB: 0 ShapeSum: 4832b65c RouteDB: 0 Post Restoration Checksum: NetGraph: 5d042c4b | NumContArr: cbf43901 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2ae4a5a86 Time (s): cpu = 00:01:27 ; elapsed = 00:01:15 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 492 ; free virtual = 22732 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2ae4a5a86 Time (s): cpu = 00:01:27 ; elapsed = 00:01:15 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 492 ; free virtual = 22731 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2ae4a5a86 Time (s): cpu = 00:01:27 ; elapsed = 00:01:15 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 492 ; free virtual = 22731 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 27f32fd8f Time (s): cpu = 00:01:35 ; elapsed = 00:01:19 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 459 ; free virtual = 22699 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 | Router Utilization Summary Global Vertical Routing Utilization = 0.00504853 % Global Horizontal Routing Utilization = 0.00539926 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 2849 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 2812 Number of Partially Routed Nets = 37 Number of Node Overlaps = 26 Phase 2 Router Initialization | Checksum: 24770d96b Time (s): cpu = 00:01:37 ; elapsed = 00:01:20 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 456 ; free virtual = 22695 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 24770d96b Time (s): cpu = 00:01:37 ; elapsed = 00:01:20 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 455 ; free virtual = 22695 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 26d9073ba Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 458 ; free virtual = 22698 Phase 3 Initial Routing | Checksum: 26d9073ba Time (s): cpu = 00:01:39 ; elapsed = 00:01:21 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 457 ; free virtual = 22697 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 273 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.529 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 256bd4e49 Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 454 ; free virtual = 22695 Phase 4 Rip-up And Reroute | Checksum: 256bd4e49 Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 454 ; free virtual = 22695 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 256bd4e49 Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 453 ; free virtual = 22694 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 256bd4e49 Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 453 ; free virtual = 22694 Phase 5 Delay and Skew Optimization | Checksum: 256bd4e49 Time (s): cpu = 00:01:44 ; elapsed = 00:01:24 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 453 ; free virtual = 22694 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1fb0b95ea Time (s): cpu = 00:01:45 ; elapsed = 00:01:25 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 444 ; free virtual = 22685 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.625 | TNS=0.000 | WHS=0.375 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1fb0b95ea Time (s): cpu = 00:01:45 ; elapsed = 00:01:25 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 442 ; free virtual = 22683 Phase 6 Post Hold Fix | Checksum: 1fb0b95ea Time (s): cpu = 00:01:45 ; elapsed = 00:01:25 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 442 ; free virtual = 22683 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.659964 % Global Horizontal Routing Utilization = 0.846334 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1fb0b95ea Time (s): cpu = 00:01:45 ; elapsed = 00:01:25 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 454 ; free virtual = 22695 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1fb0b95ea Time (s): cpu = 00:01:45 ; elapsed = 00:01:25 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 454 ; free virtual = 22694 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 17b98f639 Time (s): cpu = 00:01:46 ; elapsed = 00:01:26 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 445 ; free virtual = 22686 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.625 | TNS=0.000 | WHS=0.375 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 17b98f639 Time (s): cpu = 00:01:47 ; elapsed = 00:01:26 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 451 ; free virtual = 22692 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 19ea33fd8 Time (s): cpu = 00:01:47 ; elapsed = 00:01:26 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 451 ; free virtual = 22692 Ending Routing Task | Checksum: 19ea33fd8 Time (s): cpu = 00:01:47 ; elapsed = 00:01:27 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 451 ; free virtual = 22692 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:50 ; elapsed = 00:01:29 . Memory (MB): peak = 2894.977 ; gain = 0.000 ; free physical = 445 ; free virtual = 22686 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (25078) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (13515) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (25078) ---------------------------- There are 2422 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH) There are 708 register/latch pins with no clock driven by root clock pin: u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (13515) ---------------------------------------------------- There are 13515 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.649 0.000 0 1 0.391 0.000 0 1 4.500 0.000 0 2 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.649 0.000 0 1 0.391 0.000 0 1 4.500 0.000 0 2 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 3156.879 ; gain = 254.086 ; free physical = 204 ; free virtual = 22357 # exit INFO: [Common 17-206] Exiting Vivado at Tue Apr 8 00:29:09 2025... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Baby-Risco-5 -b digilent_arty_a7_100t -l File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5/build_digilent_arty_a7_100t.tcl Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [=============== ] 30.00% Load SRAM: [=============================== ] 62.00% Load SRAM: [=============================================== ] 94.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] dir Running in /var/jenkins_home/workspace/Baby-Risco-5/Baby-Risco-5 [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1 Running tests in {'name': 'coremark', 'path': '/eda/processor_ci_tests/tests/coremark'} [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: d011ca6f-73a3-45a6-b010-7a4464057e6b hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: No test report files were found. Configuration error? Finished: FAILURE