Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Running on Jenkins in /var/lib/jenkins/workspace/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -rf AUK-V-Aethia
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone <a href='https://github.com/veeYceeY/AUK-V-Aethia.git'>https://github.com/veeYceeY/AUK-V-Aethia.git</a>
Cloning into 'AUK-V-Aethia'...
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] dir
<span class="pipeline-node-13">Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-15">+ /usr/bin/iverilog -o test.o -s aukv_eggs_soc_tb tb/soc/aukv_eggs_soc_tb.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v rtl/core/aukv.v rtl/memory/cache.v rtl/memory/oc_ram.v rtl/memory/oc_rom.v rtl/soc/aukv_eggs_soc.v rtl/system/reset_sync.v rtl/wishbone/wb_arbiter.v rtl/wishbone/wb_interconnect.v rtl/wishbone/wb_master.v rtl/wishbone/wb_switch.v rtl/peripherals/fifo/fifo.v rtl/peripherals/gpio/gpio.v rtl/peripherals/spi/spi.v rtl/peripherals/uart/baud.v rtl/peripherals/uart/uart_rx.v rtl/peripherals/uart/uart_tx.v rtl/peripherals/uart/uart.v -I rtl/wishbone/
tb/soc/aukv_eggs_soc_tb.v:40: syntax error
I give up.
rtl/memory/oc_ram.v:27: error: malformed `include directive. Did you quote the file name?
rtl/memory/oc_ram.v:31: warning: macro WB_M2S undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:32: warning: macro WB_S2M undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:45: warning: macro addr undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:48: warning: macro sel undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:50: warning: macro data undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:53: warning: macro we undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:53: warning: macro stb undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:53: warning: macro cyc undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:70: warning: macro stb undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:70: warning: macro cyc undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:70: warning: macro we undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:90: warning: macro data undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:93: warning: macro ack undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:93: warning: macro stb undefined (and assumed null) at this point.
rtl/memory/oc_ram.v:93: warning: macro cyc undefined (and assumed null) at this point.
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE