Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/AUK-V-Aethia
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf AUK-V-Aethia
[Pipeline] sh
+ git clone https://github.com/JN513/AUK-V-Aethia.git
Cloning into 'AUK-V-Aethia'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
[Pipeline] {
[Pipeline] sh
+ /usr/bin/iverilog -o test.o -s aukv_eggs_soc_tb tb/soc/aukv_eggs_soc_tb.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v rtl/core/aukv.v rtl/memory/cache.v rtl/memory/oc_ram.v rtl/memory/oc_rom.v rtl/soc/aukv_eggs_soc.v rtl/system/reset_sync.v rtl/wishbone/wb_arbiter.v rtl/wishbone/wb_interconnect.v rtl/wishbone/wb_master.v rtl/wishbone/wb_switch.v rtl/peripherals/fifo/fifo.v rtl/peripherals/gpio/gpio.v rtl/peripherals/spi/spi.v rtl/peripherals/uart/baud.v rtl/peripherals/uart/uart_rx.v rtl/peripherals/uart/uart_tx.v rtl/peripherals/uart/uart.v -I rtl/wishbone/
rtl/soc/aukv_eggs_soc.v:171: warning: Port 12 (i_s2m2_wb) of wb_interconnect expects 33 bits, got 32.
rtl/soc/aukv_eggs_soc.v:171:        : Padding 1 high bits of the port.
rtl/soc/aukv_eggs_soc.v:171: warning: Port 16 (i_s2m4_wb) of wb_interconnect expects 33 bits, got 32.
rtl/soc/aukv_eggs_soc.v:171:        : Padding 1 high bits of the port.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS