Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Running on Jenkins in /var/lib/jenkins/workspace/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -rf AUK-V-Aethia
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone --recursive <a href='https://github.com/veeYceeY/AUK-V-Aethia.git'>https://github.com/veeYceeY/AUK-V-Aethia.git</a> AUK-V-Aethia
Cloning into 'AUK-V-Aethia'...
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
<span class="pipeline-node-13">Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-15">+ iverilog -o simulation.out -g2005 -s aukv rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v
+ vvp simulation.out
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
<span class="pipeline-node-30">Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
</span>[Pipeline] {
[Pipeline] lock
<span class="pipeline-node-32">Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
<span class="pipeline-node-38">Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] dir
<span class="pipeline-node-40">Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] echo
<span class="pipeline-node-42">Iniciando síntese para FPGA colorlight_i9.
</span>[Pipeline] sh
[Pipeline] echo
<span class="pipeline-node-44">Iniciando síntese para FPGA digilent_nexys4_ddr.
</span><span class="pipeline-node-43">+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9
</span>[Pipeline] sh
<span class="pipeline-node-43">Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 248, in &lt;module&gt;
    main(
  File "/eda/processor-ci/main.py", line 187, in main
    processor_data = get_processor_data(config, processor_name)
  File "/eda/processor-ci/main.py", line 173, in get_processor_data
    raise ValueError(
ValueError: Processador 'AUK-V-Aethia' n��o encontrado na configura����o.
</span><span class="pipeline-node-45">+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr
Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 248, in &lt;module&gt;
    main(
  File "/eda/processor-ci/main.py", line 187, in main
    processor_data = get_processor_data(config, processor_name)
  File "/eda/processor-ci/main.py", line 173, in get_processor_data
    raise ValueError(
ValueError: Processador 'AUK-V-Aethia' n��o encontrado na configura����o.
</span>[Pipeline] }
[Pipeline] }
[Pipeline] // dir
[Pipeline] // dir
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-74">Lock released on resource [Resource: colorlight_i9]
</span>[Pipeline] }
<span class="pipeline-node-75">Lock released on resource [Resource: digilent_nexys4_ddr]
</span>[Pipeline] // lock
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
<span class="pipeline-node-82">Failed in branch colorlight_i9
</span>[Pipeline] }
<span class="pipeline-node-83">Failed in branch digilent_nexys4_ddr
</span>[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
<span class="pipeline-node-89">Running in /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia
</span>[Pipeline] {
[Pipeline] sh
<span class="pipeline-node-91">+ rm -rf LICENSE README.md doc rtl simulation.out sw tb
</span>[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE