Currently supported Build processes:
Note: The infrastructure is still in a state of implementation, some processors may be in an error state due to problems in the configuration of the infrastructure.
| Name | Links | Extensions | Status | Full Log |
|---|---|---|---|---|
| AUK-V-Aethia | Github | I | Log | |
| DarkRISCV | Github | I | Log | |
| DV-CPU-RV | Github | I | Log | |
| e203 | Github | I | Log | |
| Klessydra-F03 | Github | IA | Log | |
| Klessydra-T02 | Github | IA | Log | |
| Klessydra-T03 | Github | IA | Log | |
| Klessydra-T13 | Github | IA | Log | |
| Mriscv | Github | IM | Log | |
| neorv32 | Github | I/EMACBUXZicntr | Log | |
| Pequeno Risco 5 | Github | I | Log | |
| RISC-V Steel | Github, Website | IZcsr | Log | |
| Risco 5 | Github, Website | I/E[M] | Log | |
| riskow | Github | I | Log | |
| RPU | Github | I | Log | |
| SERV | Github | I | Log | |
| TinyRiscv | Github | I | Log | |
| biriscv | Github | Log | ||
| PicoRV32 | Github | Log | ||
| Tethorax | Github | Log | ||
| Nerv | Github | Log | ||
| cv32e40p | Github | Log | ||
| Ibex | Github | Log | ||
| RV12 | Github | Log | ||
| scr1 | Github | Log | ||
| SweRV | Github | Log | ||
| SweRV-EL2 | Github | Log | ||
| SweRV-EH2 | Github | Log | ||
| RPU | Github | Log | ||
| Taiga | Github | Log | ||
| Maestro | Github | Log | ||
| RSD | Github | Log | ||
| Kronos | Github | Log | ||
| RV3N | Github | Log | ||
| riskow | Github | Log | ||
| Riscado-V | Github | Log | ||
| RS5 | Github | Log | ||
| VeeR-EH2 | Github | Log | ||
| VeeR-EL2 | Github | Log | ||
| VeeR-EH1 | Github | Log | ||
| VexRiscv | Github | I | Log |
Frequency vs LUT4 in Colorlight i9 FPGA Board
