Skip to content

Currently supported Build processes:

Note: The infrastructure is still in a state of implementation, some processors may be in an error state due to problems in the configuration of the infrastructure.

Name Links Extensions XLEN Language Status Full Log
RVX Github I 32 Verilog Build Status Log
Minerva Github Amaranth HDL(Python) Build Status Log
mriscv Github 32 Verilog Build Status Log
e200_opensource Github Verilog Build Status Log
serv Github I[M] 32 Verilog Build Status Log
biriscv Github 32 Verilog Build Status Log
picorv32 Github 32 Verilog Build Status Log
DarkRISCV Github E/I 32 Verilog Build Status Log
Tinyriscv Github IM 32 Verilog Build Status Log
Auk-V Github 32 Verilog Build Status Log
DV-CPU-RV Github 32 Verilog Build Status Log
NeoRV32-Verilog Github 32 Verilog Build Status Log
NeoRV32 Github 32 VHDL Build Status Log
Tethorax Github VHDL Build Status Log
Baby Risco 5 Github E 32 Verilog Build Status Log
Pequeno Risco 5 Github I 32 Verilog Build Status Log
Risco 5 Github IM 32 Verilog Build Status Log
Grande Risco 5 Github IMBC_Zicsr 32 SystemVerilog Build Status Log
Nerv Github I 32 SystemVerilog Build Status Log
CV32e40p Github 32 SystemVerilog Build Status Log
Ibex (formerly Zero-riscy) Github EC IMC[B] SystemVerilog Build Status Log
CVA6 Github SystemVerilog Build Status Log
Roa Logic RV12 Github I 32 SystemVerilog Build Status Log
SCR1 Github SystemVerilog Build Status Log
ReonV Github 32 VHDL Build Status Log
SweRV EH1 Github SystemVerilog Build Status Log
SweRV EL2 Github SystemVerilog Build Status Log
SweRV EH2 Github SystemVerilog Build Status Log
RPU Github IMZcsr 32 VHDL Build Status Log
RV01 Github VHDL Build Status Log
Taiga Github SystemVerilog Build Status Log
Maestro Github VHDL Build Status Log
SSRV Github IMC 32 Verilog Build Status Log
RSD Github IMF 32 SystemVerilog Build Status Log
Kronos Github I_Zicsr_Zifencei 32 SystemVerilog Build Status Log
Klessydra-T03 Github [I/E][M][A] + Kless-Vect 32 VHDL-2008 Build Status Log
Klessydra-T02 Github I[A] 32 VHDL-2008 Build Status Log
Klessydra-F03 Github I[A] 32 VHDL-2008 Build Status Log
Klessydra-T13 Github I[A] 32 VHDL-2008 Build Status Log
Starsea_riscv Github Verilog Build Status Log
NOEL-V Github GC 32/64 VHDL Build Status Log
RV3N Github Verilog Build Status Log
RISCuinho Github I 32 Verilog Build Status Log
Riskow Github I 32 Verilog Build Status Log
Riscado-V Github I 32 Verilog Build Status Log
Vexriscv Github I[M][A][F[D]][C] 32 Chisel Build Status Log
WARP-V Github TL-Verilog Build Status Log
VeeR EH1 RISC-V Github SystemVerilog Build Status Log
VeeR EL2 RISC-V Github SystemVerilog Build Status Log
VeeR EH2 RISC-V Github SystemVerilog Build Status Log
cdl_hardware Github CDL Build Status Log
mr1 Github Chisel Build Status Log
rocket Github 32 Chisel Build Status Log
freedom Github 32/64 Chisel Build Status Log
BOOM Github 64 Chisel Build Status Log
e203 Github Verilog Build Status Log
RS5 Github SystemVerilog Build Status Log
Black Parrot Github SystemVerilog Build Status Log
FabScalar Github Verilog Build Status Log
MicroRV32 Github IMC 32 Chisel Build Status Log
Piccolo Github Verilog Build Status Log
Flute Github BlueSpec Build Status Log
Toooba Github Verilog Build Status Log
RISC-V core (ultraembedded) Github Verilog Build Status Log
XiangShan Github Chisel Build Status Log
Hazard3 Github 32 Verilog Build Status Log
NutShell Github GC 32/64 Chisel Build Status Log
Lizard Github IM 64 PyMTL Build Status Log
RiscyOO Github G 64 BlueSpec Build Status Log
MYTH Cores Github TL-Verilog Build Status Log
Anfield/Balotelli Github IM 64 Verilog Build Status Log
I2SRV32-S-v1 Github 32 Verilog Build Status Log
I2SRV64-SS-v1 Github GC 64 Verilog Build Status Log
Leaf Github I 32 VHDL Build Status Log
AIRisc Github I[/E[M][C] Zocsr Zicntr 32 Verilog Build Status Log
CV32e41p Github IM[F][Zfinx]C[Zce] 32 SystemVerilog Build Status Log
CVE2 Github IMC/EMC 32 SystemVerilog Build Status Log
CV32E40S Github I/E[M][Zmmul] 32 SystemVerilog Build Status Log
CV32E40X Github 32 SystemVerilog Build Status Log
CVA5 Github IMD 32 SystemVerilog Build Status Log
Fedar F1 Github IM 64 Verilog Build Status Log
Harv Github I 32 VHDL Build Status Log
Hornet Github IM 32 Verilog Build Status Log
SprintRV Github IMZicsr 32 Verilog Build Status Log
mmRISC-1 Github IMAFC 32 Verilog Build Status Log
Openpiton Github 64 Verilog Build Status Log
Paranut Github SystemC Build Status Log
Pulpino Github 32 SystemVerilog Build Status Log
Rift2Core Github GC 64 Chisel Build Status Log
RiftCore Github IMC 64 Verilog Build Status Log
Riscv Atom Github IC_Zicsr 32 Verilog Build Status Log
RV32IC-CPU Github IC 32 Verilog Build Status Log
Simodense Github Verilog Build Status Log
SparrowRV Github IMZicsr 32 Verilog Build Status Log
arRISCado Github IMAC 32 Verilog Build Status Log
Kant-V Github I 32 Verilog Build Status Log
Mor1kx Github 32/64 Verilog Build Status Log
openc910 Github GCV 64 Verilog Build Status Log
Potato Github I 32 VHDL Build Status Log
muntjac Github IMAC[F][D]_ZiCSR_Zifencei 64 SystemVerilog Build Status Log
zero-riscy Github IMC 32 SystemVerilog Build Status Log

Frequency vs LUT4 in Digilent Arty A7 FPGA Board

Scatter Plot: Frequency vs. LUT4